KR101180715B1 - An array substrate for In-Plane switching mode LCD - Google Patents

Abstract

The present invention is a substrate; A data line and a gate line intersecting each other on the substrate to define a pixel region, the data line and the gate line formed above and below the gate insulating layer; A thin film transistor connected to the gate line and the data line; A common wiring extending in the same direction as the gate wiring and formed in the same layer; First and second common electrode connection patterns respectively branching from the common line in the same direction as the data line; A protective layer having a drain contact hole exposing the drain electrode of the thin film transistor over the data line and a first contact hole exposing the second common electrode connection pattern; A pixel electrode connection pattern contacting the drain electrode through the drain contact hole on the protective layer and overlapping the first common electrode connection pattern, and a plurality of pixel electrodes branched from the pixel electrode connection pattern; A third common electrode connection pattern overlapping the second common electrode connection pattern on the passivation layer and simultaneously contacting through the first contact hole, and branched from the third common electrode connection pattern and intersected with the pixel electrode; It includes a plurality of common electrodes, the protective layer of the plurality of pixel electrodes and the region where the common electrode is formed by providing an array substrate for a transverse electric field type liquid crystal display device characterized in that the surface is flat, to prevent light leakage due to poor rubbing, Improve the contrast ratio.

Description

An array substrate for in-plane switching mode LCD

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views showing operations in off and on states of a general transverse electric field type liquid crystal display device, respectively.

3 is a plan view showing a part of a conventional array substrate for a transverse electric field type liquid crystal display device.

4 is a plan view showing one pixel area of a conventional array substrate for a transverse electric field type liquid crystal display device having a multi-domain structure.

5 is a cross-sectional view taken along the line V-V of FIG. 4.

6 is a cross-sectional view taken along the line VI-VI of FIG. 4.

FIG. 7 is a photograph of one pixel area in which a liquid crystal display device is constructed by using a conventional multi-domain structure transverse field type liquid crystal display array substrate, and light is transmitted from a lower surface thereof. FIG.

8 is a plan view schematically showing one pixel area of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

9 is a cross-sectional view taken along the line VII-VII of FIG. 8;

10 is a cross-sectional view taken along the line VII-VII of FIG. 8.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

101 substrate 104 gate electrode

107: gate electrode 116: gate insulating film

120 semiconductor layer 128 source electrode

130: drain electrode 135: protective layer

138: drain electrode 150: pixel electrode connection pattern

155: pixel electrode 161: common electrode

Tr: Thin Film Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device having improved light leakage and a high CR ratio.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the highest resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other, and the liquid crystal layer 11 is interposed between the upper and lower substrates 9, 10. It is.

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views illustrating operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystal moves by the horizontal electric field, the viewing angle is widened.

Therefore, when the transverse electric field type liquid crystal display device is viewed from the front, it can be seen in the up / down / left / right directions even in the about 80 to 85 ^o direction without inversion phenomenon.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

3 is a plan view schematically illustrating a part of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the drawings, the conventional array substrate 10 for a transverse electric field type liquid crystal display device includes a plurality of gate wires 12 arranged in one direction in parallel with a predetermined interval therebetween, and in parallel with and adjacent to the gate wires 12. The common wiring 16 configured in one direction and the data wiring 24 intersecting the two wirings, and in particular the gate wiring 12, define the pixel region P.

The thin film transistor Tr including the gate electrode 14, the active layer 20, the source electrode 26, and the drain electrode 28 is formed at the intersection of the gate line 12 and the data line 24. The source electrode 26 is connected to the data line 24, and the gate electrode 14 is configured as part of the gate line 12.

The pixel electrode 30 connected to the drain electrode 28 and the pixel electrode 30 are arranged in parallel with the pixel electrode 30 on the pixel region P and branched from the common wiring 16. ) Is configured.

In this case, the pixel electrode 30 extends vertically from the first pixel wiring 29a extending from the drain electrode 28 to be spaced apart from each other by a predetermined distance, and the plurality of pixel electrodes 30 The ends are connected by the second pixel wiring 29b provided on the common wiring 16.

In addition, the common electrode 17 extends vertically downward from the common wiring 16 and intersects with the pixel electrode 30. In addition, one end of the plurality of common electrodes 17 is common. It is comprised by the wiring 18 connected to one.

However, the above-described configuration of the general transverse electric field type liquid crystal display has a problem in that gray scale inversion occurs.

To solve this problem, a transverse field type liquid crystal display device having a multi-domain by implementing a common electrode and a pixel electrode having different angles in one pixel area has been proposed.

Hereinafter, a structure of an array substrate for a transverse electric field type liquid crystal display device having a multi-domain structure will be described with reference to FIG. 4.

4 is a plan view showing one pixel area of a conventional array substrate for a transverse electric field type liquid crystal display device having a multi-domain structure.

As illustrated, the array substrate 50 for a transverse electric field type liquid crystal display device having a multi-domain includes a plurality of gate lines 53 arranged in one direction in parallel with each other, and a plurality of pixel regions (intersecting the gate lines 53). A data line 74 is defined and a common line 59 is formed in the same direction as the gate line 53 to be adjacent to the gate line 53. In P), the thin film transistor Tr is connected to the gate line 53 and the data line 74 as a switching element.

Further, in each pixel area P, first and second common electrode connection patterns 61a and 61b are formed to branch from the common line 59 to each pixel area P to be parallel to the data line 74. Branched from the first and second common electrode connection patterns 61a and 61b, and both ends thereof contact the first and second common electrode connection patterns 61a and 61b, and the first and second directions (that is, The first direction is a direction having a predetermined angle counterclockwise with respect to the gate wiring, and the second direction is a direction having a predetermined angle clockwise with respect to the gate wiring. The electrode 65 is formed. In this case, the common wiring 59, the first and second common electrode connection patterns 61a and 61b, and the common electrode 65 may be shaped like a ladder in the pixel area P. In addition, each common electrode 65 is formed in a wiring shape having a predetermined width except for a portion formed in the center of the pixel region, and is connected only to the second common electrode connection pattern 61b only in the center portion. The first common electrode 65a having a triangular shape is formed, and has a different arrangement direction up and down based on the first common electrode 65a having a triangular shape, and the second and third common electrodes 65b, 65c) is characterized. Accordingly, the second and third common electrodes 65b and 65c disposed above and below the triangular first common electrode 65a in the center of the pixel region P are symmetrically formed.

In addition, each pixel region P is connected to the drain electrode 78 of the thin film transistor Tr, and a plurality of pixel electrodes 88 are formed to be alternately arranged with the common wiring 65 as a transparent conductive material. It is becoming. In this case, each of the pixel electrodes 88, more specifically, the first, second, and third pixel electrodes 88a, 88b, and 88c may also be connected to the drain electrode 78 and parallel to the data line 74. The first and second pixel electrodes P1 and B2 are formed in a branched shape from the first and second pixel electrode connection patterns 86a and 86b formed to overlap the common electrode connection patterns 61a and 61b, respectively. A plurality of second and third pixel electrodes 88b and 88c are symmetrically formed in different directions up and down based on 88a).

Next, the cross-sectional structure will be described with reference to FIGS. 5 and 6, which are cross-sectional views taken along cut lines V-V and VI-VI.

As illustrated, a gate wiring 53 including a gate electrode 56 is formed on the substrate 50, and the common electrode 65 and the same electrode are formed on the same layer using the same metal material forming the gate wiring 53. First and second common electrode connection patterns 61a and 61b and a common wiring (not shown) are formed.

In addition, a gate insulating film 68 is formed on the entire surface of the gate wiring 53 and the common wiring 59 as an inorganic insulating material, and intersects with the gate wiring 53 on the gate insulating film 68. A data line 74 defining P) is formed, and a source electrode 76 is formed by overlapping with the gate electrode 56 and branching from the data line 74 to form the source electrode 76. A spaced apart drain electrode 78 is formed. In this case, a semiconductor layer 71 including an ohmic contact layer 71b of impurity amorphous silicon and an active layer 71a of pure amorphous silicon is further disposed on the gate insulating layer 68 under the source and drain electrodes 76 and 78. Formed.

Next, a passivation layer 81 is formed over the source and drain electrodes 76 and 78, the data line 74, the exposed semiconductor layer 71, and the gate insulating layer 68, and the passivation layer 81. Contact with the drain electrode 78 and the drain contact hole 83 and correspond to the first and second common electrode connection patterns 61a and 61b, respectively, and correspond to the first and second pixel electrode connection patterns 86a and 86b. And a plurality of pixel electrodes 88 branch from the first and second pixel electrode connection patterns 86a and 86b as a transparent conductive material in a region between the plurality of common electrodes 65 spaced apart from each other. Both ends are formed in contact with the first and second pixel electrode connection patterns 86a and 86b.

However, when the array substrate for a transverse electric field type liquid crystal display device having the above-described structure is driven after being interposed between the color filter substrate and the liquid crystal, and then driven, the upper side of the transverse electric field type liquid crystal display device is shown as shown in FIG. That is, there is a problem that light leakage occurs along the upper surface of the common electrode formed at a predetermined angle in a counterclockwise direction with respect to the gate wiring.

Although not shown in the drawing, in the array substrate, an alignment layer is formed over the pixel electrode for the initial alignment of the liquid crystal, and rubbing is performed for the initial alignment of liquid crystal molecules with respect to the alignment layer. In the direction parallel to the gate wiring, due to the step caused by the common electrode in the protective layer, rubbing defects are generated along the lower common electrode, especially in the upper part of the pixel region P, and light leakage occurs. Will be done.

The present invention has been made to solve the problems described above, by eliminating the step in the protective layer by the common electrode to enable uniform rubbing to prevent light leakage phenomenon due to poor rubbing, and also by contrast light prevention An object of the present invention is to provide an array substrate for a transverse electric field type liquid crystal display device having an improved ratio.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object is a substrate; A data line and a gate line intersecting each other on the substrate to define a pixel region, the data line and the gate line formed above and below the gate insulating layer; A thin film transistor connected to the gate line and the data line; A common wiring extending in the same direction as the gate wiring and formed in the same layer; First and second common electrode connection patterns respectively branching from the common line in the same direction as the data line; A protective layer having a drain contact hole exposing the drain electrode of the thin film transistor over the data line and a first contact hole exposing the second common electrode connection pattern; A pixel electrode connection pattern contacting the drain electrode through the drain contact hole on the protective layer and overlapping the first common electrode connection pattern, and a plurality of pixel electrodes branched from the pixel electrode connection pattern; A third common electrode connection pattern overlapping the second common electrode connection pattern on the passivation layer and simultaneously contacting through the first contact hole, and branched from the third common electrode connection pattern and intersected with the pixel electrode; And a plurality of common electrodes, wherein the passivation layer of the pixel electrode and the region in which the common electrode is formed has a flat surface, and the pixel electrode connection pattern overlaps the first common electrode connection pattern. And second and third regions bent in parallel with the pixel electrode at both ends of the first region, respectively, and an upper first region overlaps the first common electrode connection pattern, and the second region is the common region. It overlaps with wiring to form a storage capacitor.

In this case, the pixel electrode is positioned at the center of the pixel area, and the pixel electrode formed in parallel with the gate line is positioned on the first pixel electrode and the plurality of pixel electrodes on the same pixel area with respect to the first pixel electrode. The second pixel electrode and a plurality of pixel electrodes disposed below the third pixel electrode, and the second and third pixel electrodes are symmetrical with respect to the first pixel electrode. When the plurality of common electrodes positioned above the first pixel electrode and the plurality of common electrodes positioned below the second common electrode are defined as the second common electrode in the same pixel region with respect to the one pixel electrode, It is characterized by symmetry with respect to the first pixel electrode.

In addition, the pixel electrode and the common electrode are formed on the same layer above the protective layer.

In addition, the common electrode and the pixel electrode is preferably made of a transparent conductive material, and in this case, the transparent conductive material is preferably indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, the first and second common electrode connection patterns between neighboring pixel areas based on the data line may be electrically connected to each other by further forming an auxiliary pattern at an end thereof.

The thin film transistor may include a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer overlapping the gate electrode on the gate insulating layer, and a source and drain electrode formed to be spaced apart from each other on the semiconductor layer.

In addition, a semiconductor pattern of impurity amorphous silicon and pure amorphous silicon is further formed under the data line.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

8 is a plan view schematically illustrating one pixel area of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown, the array substrate 101 for a transverse electric field type liquid crystal display device having a multi-domain includes a plurality of gate lines 104 arranged in one direction in parallel, and a plurality of pixel regions intersecting the gate lines 104. A plurality of data wires 125 are formed and a common wire 110 is formed close to the gate wire 104 in the same direction as the gate wire 104.

In addition, first and second common electrode connection patterns 113a and 113b branched from the common line 110 and branched in the same direction as the data line 125 are formed to form a first line together with the common line 110. And the second common electrode connection patterns 113a and 113b are formed in a pixel structure that is rotated 90 degrees clockwise in each pixel region P, that is, "??".

Next, in each pixel region P, the gate line 104 and the data line 125 are connected to each other, and a thin film transistor Tr is formed as a switching element.

In addition, in one pixel area P, a plurality of pixel electrodes 155 are connected to the drain electrode 130 of the thin film transistor Tr and spaced apart from each other by a transparent conductive material. In this case, the pixel electrode 155 has a first pixel electrode 155a parallel to the gate line 104 in a central portion of the pixel region P, and an upper portion of the first pixel electrode 155a above the first pixel electrode 155a. A plurality of second pixel electrodes 155b spaced apart from each other with a predetermined angle in a counterclockwise direction with respect to the pixel electrode 155a are formed, and a lower portion of the first pixel electrode 155a is formed under the first pixel electrode ( A plurality of third pixel electrodes 155c having a predetermined angle in a clockwise direction with respect to 155a and spaced apart from each other are formed.

Next, the first and second common electrode connection patterns 113a and 113b formed in parallel with the data line 125 by branching from the common line 110 into the data line 125 and the second common electrode. The third common electrode connection pattern 158 is formed as a transparent conductive material and is simultaneously overlapped with the connection pattern 113b through the first contact hole 141. In the third common electrode connection pattern 158, A plurality of common electrodes 161 are formed by branching to have a predetermined angle with respect to the direction in which the gate wiring 104 is formed. In this case, the common electrode 161 is in the pixel region P. The common electrode 161 is positioned on the first pixel electrode 155a formed at the center thereof in parallel with the gate wiring. A plurality of first common electrodes 161a having a predetermined angle in a counterclockwise direction and spaced apart from each other are formed, and a plurality of first common electrodes 161a are spaced apart from each other at a predetermined angle in a clockwise direction with respect to the first pixel electrode 155a. The second common electrode 161b is formed, wherein the plurality of first common electrodes 161a and the plurality of second common electrodes 161b are symmetrical with respect to the first pixel electrode 155a. It is characterized by being formed as an enemy.

In addition, the pixel electrodes 155 and the common electrode 161 are formed to be spaced apart from each other, and the two electrodes 155 and 161 are formed of a transparent conductive material on the same layer.

In more detail, the shapes of the common electrode and the pixel electrode will be described.

The most characteristic aspect of the present invention is that the common electrode 161 and the pixel electrode 155 are formed as a transparent conductive material on the same layer, wherein the common electrode 161 and the pixel electrode 155 are alternately arranged. The common electrode 161 and the pixel electrode 155 in the upper and lower regions diverge at different angles with respect to the center of the pixel region P to have a multi-domain structure. The pixel electrode 155 and the common electrode 161 ) Are formed in the pixel electrode connection pattern 150 and the third common electrode connection pattern 158 which are respectively branched in the direction parallel to the data line 125 and are alternately arranged. In this case, the pixel electrode 155 is electrically connected to the drain electrode 130 and the drain contact hole 138 of the thin film transistor Tr, and the common electrode 161 is the same as the gate line 104. The second common electrode connection pattern 113b branched from the common wiring 110 formed in the layer is connected to the first contact hole 141.

In addition, the pixel electrode connection pattern 150 and the lower portion of the first common electrode connection pattern 113a are formed to overlap each other, thereby forming a storage capacitor.

Next, the cross-sectional structure will be described with reference to FIGS. 9 and 10 showing cross sections taken along cut lines X-V and X-V, respectively.

As shown, the gate wiring 104 is formed in one direction on the transparent insulating substrate 101 as a metal material, wherein a part of the gate wiring 104 forms the gate electrode 107 by itself. It is characteristic that there is. In addition, a common wiring (not shown) is formed on the same layer in parallel with the gate wiring 104 using the same metal material constituting the gate wiring 104, and the common wiring (not shown) for each pixel region P is formed. First and second common electrode connection patterns 113a and 113b are formed inside the data line 125 to be branched later and parallel to the data line 125. In this case, in order to smoothly apply a common voltage to the common wiring (not shown) and the first and second common electrode connection patterns 113a and 113b, the first and second common electrode connection patterns between the pixel regions P ( One ends of the 113a and 113b are formed to be connected to each other by the auxiliary pattern 114.

Next, a gate insulating layer 116 is formed on the entire surface of the gate electrode 107, the gate wiring 104, the common wiring (not shown), and the first and second common electrode connection patterns 113a and 113b. The data line 125 may be formed on the gate insulating layer 116 to cross the gate line 104 to define the pixel region P. The data line 125 may overlap one end of the gate electrode 107. A source electrode 128 is formed by branching from the wiring 125 and is spaced apart from the source electrode 128, and one end thereof overlaps the gate electrode 107, and a drain electrode 130 is formed. An active layer 120a of pure amorphous silicon is formed under the source and drain electrodes 128 and 130, including a region where the gate electrode 107 and the source and drain electrodes 128 and 130 are spaced apart from each other. The source on the active layer 120a Has to correspond to the lower drain electrode (128, 130) is an ohmic contact layer (120b) of the impurity amorphous silicon is formed.

Next, a drain contact hole 138 exposing a part of the drain electrode 130 over the source and drain electrodes 128 and 130, the data line 125, and the exposed active layer 120a and the gate insulating layer 116. ) And the lower gate insulating layer 116 is formed to form a protective layer 135 having a first contact hole 141 exposing a part of the second common electrode connection pattern 113b.

Next, the drain electrode 130 and the drain contact hole 138 are contacted with each other on the passivation layer 135. The pixel electrode connection pattern 150 is formed to overlap the first common electrode connection pattern 113a. Each pixel region P may be branched from the pixel electrode connection pattern 150 to be symmetrical with each other in the upper and lower portions of the pixel region P, and may have a predetermined angle with respect to the gate wiring 104. The electrode 155 is formed.

Next, the second common electrode connection pattern 113b and the first contact hole 141 are contacted with each other on the passivation layer 135, and at the same time, the pixel electrode may overlap the second common electrode connection pattern 113b. The third common electrode connection pattern 158 is formed of a transparent conductive material, which is the same material forming the 155, and branches from the third common electrode connection pattern 158 to each other above and below the pixel region P, respectively. A plurality of common electrodes 161 are formed to be symmetrical and have a predetermined angle with respect to the gate line, and are disposed to cross the pixel electrode 155.

The array substrate 101 for a liquid crystal display device according to the present invention having the above-described structure causes a step below the protective layer 135 with respect to the pixel region P in which the pixel electrode 155 and the common electrode 161 are formed. Since only the gate insulating film 116 is formed on the entire surface without an electrode and wiring, the surface of the protective layer 135 becomes flat without a step, and thus the surface state is flat even when rubbing is performed after applying the alignment film. Due to the structure there is no step generation due to the rubbing non-uniformity can be prevented.

Although the first and second common electrode connection patterns 113a and 113b are formed under the passivation layer 135 in the inner edge portion of the pixel region P, a step is formed on the surface of the passivation layer 135. When the LCD is combined with the color filter substrate to form a liquid crystal display device, it is not covered by the black matrix, so even if a defect occurs during rubbing, it is not a problem.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 9 and 10 in the cross-sectional view.

First, a first metal material is deposited on the entire surface on the transparent insulating substrate 101, and the photoresist is applied, the photoresist is exposed using a mask of the photoresist, the exposed photoresist is developed, and the metal is exposed to the outside of the photoresist remaining after the development. The gate line 104 including the gate electrode 107 and extending in one direction through a mask process including a series of steps, such as etching of a material, and a common line in a direction parallel to the gate line 104. ) And first and second common electrode connection patterns 113a and 113b branching from the common wiring (not shown). At this time, in each pixel area P, an auxiliary pattern 114 is further formed such that one ends of the first and second common electrode connection patterns 113a and 113b between adjacent pixel areas P are electrically connected to each other. do. However, the auxiliary pattern 114 for electrically connecting the first and second common electrode connection patterns 113a and 113b between the neighboring pixel regions P may not be formed.

Next, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the gate wiring 104 and the common wiring (not shown) and the first and second common electrode connection patterns 113a and 113b. Is deposited to form a gate insulating film 116.

Next, pure amorphous silicon, impurity amorphous silicon, and a second metal material are deposited on the gate insulating layer 116 and patterned at the same time through a mask process or two mask processes to form an amorphous silicon layer and a second metal material layer. By patterning, the active layer 120a of pure amorphous silicon and the ohmic contact layer 120b of impurity amorphous silicon spaced apart from each other over the active layer 120a in portions corresponding to the gate electrodes in each pixel region P. And a data line 125 forming source and drain electrodes 128 and 130 spaced apart from each other on the ohmic contact layer 120b and defining the pixel region P by crossing the gate line 104. Form. In this case, the data line 125 and the source electrode 128 are formed to be electrically connected.

When the semiconductor layer 120 of the active layer 120a and the ohmic contact layer 120b, the data line 125, and the source and drain electrodes 128 and 130 are formed through one mask process, as shown in FIG. Likewise, the impurity amorphous silicon pattern 122b and the pure amorphous silicon pattern 122a are formed under the data line 125, and although not shown in the drawing, the gate electrode is island-shaped when patterned through two mask processes. The semiconductor layers of the active layer and the ohmic contact layer are formed only in the portion corresponding to the semiconductor layer, and the impurities and the pure amorphous silicon pattern are not formed in correspondence to the data lines.

Next, silicon oxide (SiO ₂ ) or silicon nitride (Inorganic insulating material) is formed on the entire surface of the data line 125, the source and drain electrodes 128 and 130, the exposed active layer 120a, and the gate insulating layer 116. By depositing SiNx, a protective layer 135 having a flat surface without a step is formed on the main portion of the pixel region P, that is, the region where the pixel electrode 155 and the common electrode 161 are to be formed, and a mask Forming a drain contact hole 138 that exposes a portion of the drain electrode 130 corresponding to the drain electrode 130 and a first contact hole 141 that exposes a portion of the drain contact hole 141 corresponding to the second common electrode connection pattern 113b. do. In this case, the first contact hole 141 is patterned to the gate insulating layer 116.

Next, an indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, is deposited on the entire surface of the passivation layer 135 having the drain contact hole 138 and the first contact hole 141. The pixel electrode connection pattern 150 contacts the drain electrode 130 through the drain contact hole 138 by patterning the mask process and overlaps the first common electrode connection pattern 113a. In addition, a plurality of pixel electrodes 155 branched from the pixel electrode connection patterns 150 are formed, and at the same time, a second common electrode connection pattern (not shown) connected to the common wiring (not shown) through the first contact hole 141 is formed. A plurality of common electrodes connected to and overlapping with the third common electrode connecting pattern 158 and the third common electrode connecting pattern 158 and alternately disposed with the plurality of pixel electrodes 155. Transverse field type liquid crystal table according to the present invention by forming 161 To complete the array substrate for a device.

The array substrate for a transverse electric field type liquid crystal display device according to the present invention forms a protective layer having a flat state without a step on a surface of a main portion of the pixel region where the pixel electrode and the common electrode are alternately arranged, and the pixel electrode on the protective layer. And forming the common electrode at the same time has the effect of preventing rubbing unevenness.

In addition, there is an effect of preventing the light leakage phenomenon by preventing the rubbing unevenness due to the step in the pixel area.

In addition, there is an effect of improving the contrast ratio by preventing light leakage.

Claims (9)

A substrate; A data line and a gate line intersecting each other on the substrate to define a pixel region, the data line and the gate line formed above and below the gate insulating layer; A thin film transistor connected to the gate line and the data line; A common wiring extending in the same direction as the gate wiring and formed in the same layer; First and second common electrode connection patterns respectively branching from the common line in the same direction as the data line; A protective layer having a drain contact hole exposing the drain electrode of the thin film transistor over the data line and a first contact hole exposing the second common electrode connection pattern; A pixel electrode connection pattern contacting the drain electrode through the drain contact hole on the protective layer and overlapping the first common electrode connection pattern, and a plurality of pixel electrodes branched from the pixel electrode connection pattern; A third common electrode connection pattern overlapping the second common electrode connection pattern on the passivation layer and simultaneously contacting through the first contact hole, and branched from the third common electrode connection pattern and intersected with the pixel electrode; Multiple common electrodes The protective layer of the plurality of pixel electrodes and the common electrode on which the protective layer is formed has a flat surface, and the pixel electrode connection pattern includes a first region and the first region overlapping the first common electrode connection pattern. Each of the second and third regions bent in parallel with the pixel electrode at both ends of the region, wherein the first and second regions overlap the first common electrode connection pattern and the second region overlaps the common wiring. An array substrate for a transverse electric field liquid crystal display characterized by forming a storage capacitor. The method of claim 1, The pixel electrode is positioned at the center of the pixel area, and the pixel electrode formed in parallel with the gate line is formed of a first pixel electrode and a plurality of pixel electrodes positioned in the same pixel area based on the first pixel electrode. And a second pixel electrode and a plurality of pixel electrodes disposed below the second pixel electrode, and the second and third pixel electrodes are symmetrical with respect to the first pixel electrode. The method of claim 2, The first common electrode and the plurality of common electrodes disposed below the first pixel electrode in the same pixel area based on the first pixel electrode are defined as the second common electrode. And 2 common electrodes are symmetrical with respect to the first pixel electrode. The method of claim 1, And the pixel electrode and the common electrode are formed on the same layer above the passivation layer. The method according to any one of claims 1 to 3, And the common electrode and the pixel electrode are formed of a transparent conductive material. 6. The method of claim 5, The transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO) array substrate for a transverse electric field liquid crystal display device. The method of claim 1, And the first and second common electrode connection patterns between adjacent pixel regions based on the data lines have a structure in which an auxiliary pattern is further formed at an end thereof to be electrically connected to each other. The method of claim 1, The thin film transistor is A gate electrode, a gate insulating layer over the gate electrode, a source layer and a drain electrode overlapping the gate electrode over the gate insulating layer and spaced apart from each other over the semiconductor layer Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, And a semiconductor pattern of impurity amorphous silicon and pure amorphous silicon is further formed below the data line.

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