KR100288771B1 - Flat drive liquid crystal display device - Google Patents

Abstract

On the transparent insulating substrate, a gate line made of a gate line in the horizontal direction, a gate electrode, and a gate line made of gate pads at the end of the gate line, and a common line made of a plurality of common electrodes and common electrode lines connecting them in the pixel region are formed. A data line defining a pixel region, a source / drain electrode, a data line formed of a data pad, and a pixel electrode facing at regular intervals in parallel with each other are formed to cross the gate line insulated through the gate insulating film. Redundant data lines and redundant gate pads formed of redundant data lines and redundant data pads respectively connected to the data lines, the data pads, and the gate pads are formed through the contact holes formed in the passivation layer. The light blocking film overlapping with the common electrode adjacent thereto is formed. Here, when the light blocking film blocks light leaking at the boundary of the pixel region, the double data line can prevent the disconnection of the wiring, and the data line and the common electrode do not overlap each other, so it is unlikely that they will be shorted. In addition, since the light blocking film overlaps with the data line, when the data line is disconnected, the light blocking film can be used as a repair line. In addition, the pad portion may be formed as a single layer of chromium, molybdenum, molybdenum alloy, or a multilayer including ITO to ensure reliability of contact characteristics.

Description

Flat Drive Liquid Crystal Display

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device of a planar driving method.

A liquid crystal display device mainly used at present is a twisted nematic (TN) type liquid crystal display device. In the twisted nematic method, electrodes are installed on two substrates, the liquid crystal directors are arranged to be twisted by 90 °, and a voltage is applied to the electrodes to drive the liquid crystal directors. However, such a liquid crystal display device has a problem that the viewing angle is narrow, and an in-plane switching (IPS) type liquid crystal display device has been developed to replace the liquid crystal display device. This prior art is shown in US Pat. No. 5,598,285.

However, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has the following problems.

Due to the difference between the two electrodes for applying the horizontal electric field, that is, the common electrode and the pixel electrode, rubbing of the alignment layer formed on the electrode is nonuniform, resulting in a light leakage phenomenon in this portion, resulting in a low contrast ratio.

In addition, a potential difference is generated between the data line and the pixel electrode or the common electrode adjacent thereto, and light leaks near the boundary of the data line, and the leaked light is directly seen from the side, which causes cross talk. .

In addition, at the end of the wiring, there is a pad portion exposed to the outside to receive a signal. When the wiring is formed of low-resistance aluminum, the exposed aluminum is easily oxidized, and electrical contact is poor at this portion. .

An object of the present invention is to eliminate the light leakage phenomenon in a flat drive type liquid crystal display device.

Another object of the present invention is to reduce the disconnection of the wiring and to reduce the failure of the pad portion.

Another object of the present invention is to provide a high definition and large screen liquid crystal display having low resistance wiring.

1 is a layout view of a liquid crystal display device of a planar driving method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1,

3 is a cross-sectional view taken along line III-III of the thin film transistor unit of FIG. 1;

4 and 5 are cross-sectional views taken along the line IV-IV of the gate pad portion and V-V of the data pad portion of FIG. 1;

6A to 9D are cross-sectional views illustrating a manufacturing process of a substrate for a liquid crystal display as shown in FIGS. 1 to 5.

10 and 11 illustrate structures of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

12 and 13 illustrate a structure of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 14 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention.

15 is a cross-sectional view taken along the line XV-XV in FIG. 14,

16 and 17 are layout views showing in detail the structure of the thin film transistor substrate for a liquid crystal display according to the fifth and sixth embodiments of the present invention.

In the liquid crystal display substrate according to the present invention for solving this problem, the pixel electrode is formed to be 1,000 Å or less, and overlaps with the data line and the adjacent pixel electrode or the common electrode to block light leaking near the data line. A light blocking film is formed. In addition, in order to prevent disconnection of the wiring, a double layer is formed, and the upper layer of the pad portion connected to the driving integrated circuit is preferably formed of chromium, molybdenum, molybdenum alloy or ITO, in particular ITO, in order to secure reliability of electrical contact. .

More specifically, in the present invention, a gate wiring including a gate line, a gate electrode, and a gate pad and a common wiring including a common electrode line and a common electrode are formed on a substrate, and a gate insulating film is formed over the gate wiring and the common wiring. A semiconductor layer and an ohmic contact layer are formed on the gate insulating layer on the gate electrode, and a data line including a source and drain electrode, a data line, a data pad, and a data line connection part and a pixel electrode are formed thereon as a first conductive layer. A protective film is formed on the data line and the pixel electrode, and a redundant data line including a redundant data line and a redundant data pad, a redundant gate pad, and a floating light blocking layer are formed on the protective layer as a second conductive layer. .

Here, the redundant data line is electrically connected to the data line through a contact hole formed in the passivation layer, a part of the light blocking layer overlaps the data line, and the other part overlaps the common electrode or the pixel electrode adjacent to the data line.

The pixel electrode may be formed in the process of forming the redundant data line using the second conductive layer instead of forming the data line using the first conductive layer, and the thickness of the pixel electrode may be 1,000 Å or less. It is good.

In addition, the liquid crystal display according to the present invention includes a gate electrode connected to the gate line, a source electrode connected to the data line or a redundant data line, and a drain electrode connected to the pixel electrode at a portion where the gate line and the data line cross each other. A thin film transistor is formed. The data pad and the redundant data pad respectively connected to the ends of the data line and the redundant data line are connected through a contact hole formed in the passivation layer, and the gate pad connected to the end of the gate line is formed in the gate insulating film or the passivation layer. A redundant gate pad is connected through the contact hole.

The redundancy data line may be removed to cover the data line, and the redundant data line may be formed wider than other portions in the pixel region to overlap the common electrode or the pixel electrode.

Next, embodiments of the planar driving type liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a layout view of a liquid crystal display device of a planar driving method according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. 3 is a thin film transistor unit of FIG. 1. It is sectional drawing along the III-III line. 4 and 5 are cross-sectional views of the gate pad portion IV-IV and the data pad portion V-V line in FIG. 1, respectively.

1 to 5, the gate line 20 is formed in the horizontal direction on the lower transparent insulating substrate 100, and the gate pad 22 is formed at the end of the gate line 20. Part of the gate line 20 becomes the gate electrode 21. The common electrode line 10 is formed in parallel with the gate line 20, and a plurality of common electrodes 11 are connected to the common electrode line 10 in the pixel area to receive a common signal from the common electrode line 10. , 12) is formed in the longitudinal direction. Here, various conductive materials may be used as the metals for the gate wirings 20, 21, 22 and the common wirings 10, 11, and 12, and chromium, aluminum, aluminum alloys, molybdenum, molybdenum alloys, or the like. It is also possible to form a double layer combining these metals.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20, 21, 22 and the common wirings 10, 11, 12.

An amorphous silicon layer 40, which is a semiconductor layer of a thin film transistor made of amorphous silicon, is formed in an island shape on the gate insulating layer 30 on the gate electrode 21, and phosphorus (P) or the like is formed on the amorphous silicon layer 40. Resistive contact layers 51 and 52 made of highly doped amorphous silicon are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed on the gate insulating film 30 in the vertical direction. The drain electrode 62 is connected to the pixel electrode 65 which is linearly formed alternately with the common electrodes 11 and 12 in the pixel area. At the end of the data line 60, a data pad 63 for receiving an image signal from the outside is formed.

In this case, the data wires 60, 61, 62, and 63 and the pixel electrode 65 may be formed of a metal layer such as chromium or an aluminum alloy, molybdenum or molybdenum alloy, and may be thinly formed to a thickness of about 1,000 μs or less. It is good. This is because the light leakage phenomenon can be reduced by reducing the step difference between the layers due to the pixel electrode 65 to suppress the unevenness of the alignment generated in the rubbing process.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, and the thin film transistor and the remaining data wirings. The protective film 70 covering the 60, 61, 62, 63 and the pixel electrode 65 is formed of silicon nitride or the like.

Contact holes 71 and 73 are formed in the passivation layer 70 to expose a portion of the data line 60 and the data pad 63, and the gate pads 22 are formed in the gate insulating layer 30 and the passivation layer 70. The contact hole 72 which exposes a part of) is formed.

The metal pattern is formed on the passivation layer 70 in the same manner as the data lines 60 and 63, and is connected to the data line 60 and 63 through the contact holes 71 and 73 formed in the passivation layer 70. The redundant data wirings 80 and 83 are formed. Further, on the passivation layer 70, a light blocking layer 81 is formed in which the redundant data line 80, the common electrode 12 adjacent thereto, and both edge portions overlap and float. The redundant gate pads 82 connected to the gate pads 22 are formed on the gate pads 22 through the contact holes 72 formed in the passivation film 70 and the gate insulating film 30.

1 and 2, the light blocking film 81 having both edge portions overlapped with the data line 60 and two adjacent common electrodes 12 includes the data line 60 and the redundant data line ( 80) Block out light leakage near the boundary. In addition, in order to increase the angle of light leaking obliquely outward with respect to the data line 60, the width Lb of the light blocking film 81 and the common electrode 12 overlaps the light blocking film 81 and the data line. It is preferable to design larger than the width La which (60) overlaps.

Here, the light blocking film 81 and the common electrode 12 may be formed so as not to overlap, and Lb may be 1 μm or less. In this case, light passing through a narrow gap of 1 μm or less is diffracted and dispersed in various directions, so the amount of light is greatly reduced. At this time, the parasitic capacitance of the data line 60 and the common electrode 12 can be sufficiently reduced.

Also, in this structure, the parasitic capacitance generated between the data line 60 and the common electrode 12 is significantly reduced than the case where the data line 60 and the common electrode 12 directly overlap, and thus the signal applied to the data line. Can reduce the delay. This is because two parasitic capacitors are connected in series between the data line 60 and the common electrode 12 through the floating light blocking film 81.

In addition, since the data line 60 and the common electrode 12 do not directly overlap each other, there is a very small possibility that they are shorted to each other. When the data line 60 or the redundant data line 80 is disconnected, the data line 60 is disconnected. And the light blocking film 81 may be shorted to bypass the data signal applied to the data line 60 with the light blocking film, and the light blocking film 81 may be used as a repair line of the data line 60.

The redundant data wirings 80 and 83 and redundant gate pads 82 may be formed of a single film of chromium, molybdenum, molybdenum alloy or aluminum alloy, or a plurality of films made thereof. Here, since the data lines 60, 61, 62, and 63 are not exposed to the outside, the data lines 60, 61, 62, and 63 are formed of aluminum or an aluminum alloy, which is a low resistance metal, in order to minimize resistance, and the redundant data lines 80, 83 and redundant gate pads 82 are used. Since the pad portion is formed of a pad portion, it is preferable to form the pad portion using chromium, molybdenum, molybdenum alloy or the like which can have reliability, and when forming a multilayer, it is preferable to use ITO having excellent reliability as the pad portion as an upper layer film. The redundancy data wirings 80 and 83 and the redundancy gate pads 82 are formed in a portion other than the pixel region, and have a smaller thickness than the pixel electrode 65 layer, so that the redundancy data wirings 80 and 83 and the redundancy gate pad 82 are formed to be thicker than about 2,000 to 2,500 kPa. It is desirable to lower the.

Here, the pixel area is an area defined by the intersection of the gate line 20 and the data lines 60 and 80.

Now, a method of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention will be described. 6A to 9D are cross-sectional views illustrating a process of manufacturing a substrate for a liquid crystal display as shown in FIGS. 1 to 5. The alphabets a to d shown in the numerals indicate that the figures show light blocking regions, thin film transistor regions, gate pad regions, and data pad regions.

First, as shown in FIGS. 6A to 6D, a metal layer having a thickness of about 3000 μs is deposited on a transparent insulating substrate 100 such as glass, and patterned by a photo process using a mask to form a gate line 20 and a gate electrode. 21, the gate pad 22, the gate line connecting portion 24, the common electrodes 11 and 12, and the common electrode line 10 are formed. In this case, various conductive materials may be used as the gate wiring metal, and chromium, aluminum, aluminum alloy, molybdenum, molybdenum alloy, or the like may be used, or the gate wiring may be formed by a double film combining these metals.

Next, as shown in FIGS. 7A to 7D, an insulating gate insulating film 30, such as silicon nitride or an organic insulating film, is formed on the entire surface of the substrate 100 to a thickness of 3,000 to 5,000 GPa, and is about 500 to 2,000 GPa thick. The silicon layer 40 and the amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 GPa are sequentially deposited. The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned together using a mask to form an island shape on the gate electrode 21. In this case, an amorphous silicon layer may be further left on the gate insulating layer 30 intersecting the data line, the common electrode line 10, and the gate line 20 formed later.

As shown in FIGS. 8A to 8D, a metal layer such as chromium, an aluminum alloy, or molybdenum is deposited at about 1,000 GPa or less, and patterned by a photo process using a mask to intersect the gate line 20 with the data line ( 60, the source and drain electrodes 61 and 62, the data pad 63, and the pixel electrode 65 are formed. Next, the doped amorphous silicon layer 50 is etched by etching the doped amorphous silicon layer 50 using the source electrode 61 and the drain electrode 62 as a mask, and the resistive contact layer 51 is separated from each other by the gate electrode 21. , 52).

Next, as shown in FIGS. 9A to 9D, a protective film 70 having a thickness of 1,500 to 2,500 기판 is formed on the entire surface of the substrate using silicon nitride or an organic insulating film, and patterned by a photolithography process using a mask. Contact holes 71 and 73 exposing the data pads 63 are formed, and the gate insulating film 30 and the protective film 70 on the gate pad 22 are also removed to form the contact holes 72.

Finally, as shown in Figs. 2 to 5, chromium, aluminum, or aluminum alloy is deposited to a thickness of 2,000 to 2,500 microseconds, and patterned by a photo process using a mask to form a data line 60 and a data pad 63. The redundant data wirings 80 and 83 and the redundant gate pad 82 which are similar in shape to the gate pad 22 are formed. In addition, a light blocking film 81 is formed in which both edge portions overlap the data line 60 and the common electrode 12, respectively.

In the liquid crystal display according to the exemplary embodiment of the present invention, the pixel electrode is reduced as much as possible to about 1,000 GPa, thereby reducing the step difference between layers and suppressing the uneven alignment generated in the rubbing process, thereby reducing the light leakage phenomenon. Since portions other than the pixel region have a smaller thickness limit than the pixel electrode layer, they are formed thicker, such as 2,000-2,500 Å, to lower the resistance of the wiring. In addition, since the redundant data wiring part constitutes a pad part, ITO, which is a material having high contact reliability, may be used when mounting a driver integrated circuit, and an upper layer may be formed of ITO with another metal layer underneath.

In the first embodiment, the redundancy data line, the pixel electrode, the source and drain electrodes, and the light blocking film are first formed, and then a protective film is formed, and the contact hole is formed in the protective film on the gate pad, the data pad, and the data line. Next, the data line may be formed. The structure of the thin film transistor substrate for a liquid crystal display according to the second exemplary embodiment of the present invention formed through the above method will be described in detail. Here, since the structure of the pad region and the thin film transistor region is similar to that of the first embodiment, a detailed description thereof will be omitted.

10 and 11 illustrate a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10.

As shown in FIGS. 10 and 11, the common electrode 12 is formed on the substrate 100. Although FIG. 11 is not shown in sectional drawing, the gate wirings 20, 21, 22 and the common wirings 10 and 11 are also formed in the same layer as the common electrode 12. As shown in FIG.

On the gate insulating layer 30, the redundant data line 80, the source and drain electrodes 81 and 82, the redundant data wiring including the redundant data pad 83, the pixel electrode 85, and the outer portion thereof are common electrodes 12, respectively. ), A light blocking film 84 is formed.

The data lines 60 and 63 and the redundant gate pads 62 are formed on the passivation layer 70 in a similar shape to the redundant data lines 80 and 83 and the gate pads 22. Here, the data lines 60 are formed so as to overlap the inner portions of the respective light blocking films 84. The passivation layer 70 includes a contact hole 73 to which the redundant data pad 83 and the data pad 63 are connected, a contact hole 71 to which the data line 60 and the redundant data line 80 are connected, and a gate pad ( A contact hole 72 is formed between the 22 and the redundant gate pad 62.

In this case, it is advantageous to form the thickness of the pixel electrode 85 at about 1,000 GPa or less in terms of preventing light leakage. On the other hand, when the data line 60 is formed of aluminum or aluminum in order to minimize the resistance of the wiring, it is preferable to form the auxiliary protective film 90 as shown in Fig. 11 because they are weak in physical and chemical properties.

In addition, since the data pad 63 and the redundant gate pad 62 are connected to the driver, the upper passivation layer 90 is removed, and the gate pad 22 and the redundant data pad 83 are used as pad portions. When formed of this excellent conductive material chromium, molybdenum, molybdenum alloy, or the like, the data pad and redundant gate pad may not be formed.

In addition, in the above-described first embodiment, the process order is reversed, the data wirings are first formed, a protective film is formed, and then contact holes are formed in the protective film on the gate pad, the data pad and the data line, and then the redundant data wiring and the pixel electrode. And a light blocking film. The structure of the thin film transistor substrate for a liquid crystal display according to the third exemplary embodiment of the present invention formed through the above method will be described in detail. Here again, the structures of the pad region and the thin film transistor region are similar to those of the first embodiment, and thus detailed description thereof will be omitted.

As such, when the pixel electrode is formed on the passivation layer 70, the photographic process may be reduced by one time in the manufacturing process, the driving voltage of the liquid crystal may be reduced, and the passivation layer on the pixel electrode 85 may be reduced in comparison with the first embodiment. Since there is no (70), a defect in which an afterimage appears can be reduced.

12 and 13 illustrate a structure of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view taken along the line XIII to XIII of FIG. 12.

As shown in Figs. 12 and 13, most of the structure is similar to that of the first embodiment.

However, the pixel electrode 85 is formed on the passivation layer 70, and the contact hole 75 for connecting the drain electrode 62 and the pixel electrode 85 is formed in the passivation layer 70.

In the third embodiment, the data wirings 60, 61, 62, and 63 are formed of a single film or multiple films of chromium, aluminum, and aluminum alloy, and the redundant data wirings 80, 83, the pixel electrode 85, and the redundant gate are formed. The pad 82 may be formed of a single layer of chromium or a double layer of chromium nitride to secure contact resistance with the driver, and ITO may be added to ensure reliability as the pad portion.

In the thin film transistor substrate for a liquid crystal display according to the third exemplary embodiment of the present invention, the pixel electrode may be formed on the passivation layer to reduce the driving voltage.

In addition, unlike the embodiment of the present invention in which a part of the passivation layer on the data line is removed to be electrically connected to the redundant data line, all the passivation layers formed on the data line are removed and the redundant data line is formed thereon to form the data wiring and the redundant data. Contact resistance between wirings can be reduced. In this case, since it is difficult to form a light blocking film separately as in the first to third embodiments, a part of the redundant data line passing through the pixel region may be formed to overlap the common electrode to block light leakage. This will be described with reference to the fourth embodiment.

FIG. 14 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along the line XV-XV in FIG. 14. Here, the drawings of the pad portion are omitted.

As shown in Figs. 14 and 15, most structures are similar to those of the first to third embodiments.

However, the data line 60 is covered with the redundant data lines 80 and 81, and the redundant data lines 80 and 81 are formed between the common electrode line 10 and the gate line 20. A portion 81 is formed to have a wide width and overlap with the adjacent common electrode 12. In addition, an amorphous silicon layer 41 made of amorphous silicon is formed between the gate line 20 and the data line 60 crossing the common electrode line 10, and the redundant data line 80 is a data line 60. It is formed in a narrower width and is formed on the data line 60.

In the method of manufacturing the thin film transistor substrate for a liquid crystal display device according to the fourth embodiment of the present invention, the redundant data lines 80 and 81 are formed of aluminum or an aluminum alloy to minimize resistance of the wiring. When the alloy is in contact with the amorphous silicon layer, the amorphous silicon layer erodes, so that the redundancy data line 80 does not contact the amorphous silicon layer 41 at the portion passing through the amorphous silicon layer 41. Should be formed in Here, the amorphous silicon layer 41 has a function of preventing the data line 60 from disconnecting due to a step that occurs at a portion where the gate line 20, the common electrode line 10, and the data line 60 cross each other. .

Here, since the pad part is made of aluminum or an aluminum alloy, the reliability of the pad part can be reduced, so that a step of forming the pad part with ITO having excellent contact characteristics with a driver can be added.

In addition, when lowering resistance is realized with only one data line, only the light blocking film may be formed. This will be described in detail with reference to the drawings.

16 and 17 are layout views showing in detail the structure of the thin film transistor substrate for a liquid crystal display according to the fifth and sixth embodiments of the present invention. Here, the drawings of the pad portion are omitted.

As shown in Figs. 16 and 17, most of the structures are similar to those of the first to third embodiments.

However, only one data line 60 is formed, and an amorphous silicon layer for preventing disconnection of the data line 60 at a portion where the gate line 20, the common electrode line 10, and the data line 60 cross each other. (41) is formed.

In addition, as shown in FIG. 17, light blocking films 81 formed on both sides of the data line 60 are connected through the connecting portion 82.

In the same structure as in the sixth embodiment, even if the data line 60 and the light blocking film 81 are misaligned, the overlapping area is constant, so that the parasitic capacitance generated thereby can be made constant.

Although not shown in the drawings, similar to the first embodiment, the pad portion may be additionally formed in the process of forming the light blocking film 81, and may be made of chromium, molybdenum, molybdenum alloy, or the like to improve contact characteristics with the driver. do.

In all the above embodiments, only the case where the common electrode 12 is formed adjacent to the data line 60 is mentioned. The pixel electrode 65 may be formed adjacent to the data line 60 and overlapped with the light blocking film.

As in the embodiment of the present invention, the wires can be prevented from being disconnected by the double data lines, the light leakage phenomenon can be eliminated by the floating light blocking film, and the crosstalk can be suppressed. The delay can be minimized. In addition, the light blocking film can be used as a repair line when the data line is disconnected, can improve the reliability of the pad portion, and can prevent a short circuit between the data line and the common electrode. In addition, by forming the pixel electrode on the passivation layer, the number of processes can be reduced, and the driving voltage of the liquid crystal can be minimized to reduce the afterimage.

Claims (34)

A plurality of gate lines formed parallel to each other on a transparent substrate, A plurality of data lines insulated from and intersecting the gate lines; A pixel region defined by the intersection of the gate line and the data line, wherein the common electrode and the pixel electrode are formed to face each other at a predetermined interval, A redundant data line formed below or above the data line and parallel to the data line and electrically connected to the data line; And a light blocking layer formed of the same conductive material layer as the redundant data line and overlapping the data line and a common electrode or a pixel electrode adjacent to the data line. In claim 1, And an insulating film formed between the data line and the redundant data line and having a contact hole connecting the data line and the redundant data line. In claim 2, And a common electrode line formed of the same conductive material layer as the gate line and connected to the common electrode. In claim 3, And an amorphous silicon layer between the data line or the redundant data line crossing the gate line and the common electrode line. In claim 4, A data pad formed at an end of the data line, Further comprising a redundant data pad made of a conductive material layer, such as the redundant data line, And the data pad and the redundant data pad are electrically connected to each other. In claim 5, And the insulating layer has a second contact hole to which the data pad and the redundant data pad are connected. In claim 6, A gate pad formed at an end of the gate line, The redundancy gate pad may further include a redundancy data line or a conductive material layer such as the data line. The gate pad and the redundant gate pad are electrically connected to each other. In claim 7, And a third contact hole in the insulating layer connecting the gate pad and the redundant gate pad. In claim 8, The upper layer of the data pad and the redundant data pad includes a layer made of ITO. In claim 9, And a layer formed above the gate pad and the redundant gate pad includes a layer made of ITO. In claim 10, And at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. In claim 11, The pixel electrode has a thickness of 1,000 mW or less. Board, A gate wiring formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate wiring on the substrate; A gate insulating film covering the gate wiring and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A data line including a source and a drain electrode formed on the ohmic contact layer and a data line formed on the gate insulating layer and connected to the source electrode, A linear pixel electrode formed alternately with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A protective film covering the data line and the pixel electrode and having a first contact hole exposing the data line; A redundant data line formed on the passivation layer and electrically connected to the data line through the first contact hole; A light blocking layer formed on the passivation layer and overlapping the data line and the common electrode or the pixel electrode adjacent to the data line; And at least one pixel electrode and at least one common electrode in each pixel area. In claim 13, A data pad formed at an end of the data line, Further comprising a redundant data pad made of a conductive material layer, such as the redundant data line, The passivation layer has a second contact hole, and the data pad and the redundant data pad are electrically connected to each other through the second contact hole. The method of claim 14, The redundant data pad includes a layer made of ITO. The method of claim 15, A gate pad formed at an end of the gate line, Further comprising a redundant gate pad made of the same metal layer as the redundant data line, And the gate insulating layer and the passivation layer have a third contact hole exposing the gate pad so that the gate pad and the redundant gate pad are electrically connected through the third contact hole. The method of claim 16, The redundancy gate pad includes a layer made of ITO. The method of claim 17, The pixel electrode has a thickness of 1,000 mW or less. Board, A gate wiring formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate wiring on the substrate; A gate insulating film covering the gate wiring and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A redundant data line formed of a source and drain electrode formed on the resistive contact layer and a redundant data line formed on the gate insulating layer and connected to the source electrode, A linear pixel electrode formed alternately with the common electrode on the gate insulating film in the pixel region defined by the intersection of the gate line and the redundant data line, and connected to the drain electrode; A light blocking film formed on the gate insulating film and overlapping the adjacent common electrode as the redundant data line; A protective film covering the redundant data line, the pixel electrode, and the light blocking film and having a first contact hole exposing the redundant data line; A data line formed on the passivation layer and electrically connected to the redundant data line through the first contact hole; And at least one pixel electrode and at least one common electrode in each pixel area. The method of claim 19, The light blocking layer and the data line partially overlap each other. Board, A gate wiring formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate wiring on the substrate; A gate insulating film covering the gate wiring and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A data line including a source and a drain electrode formed on the ohmic contact layer and a data line formed on the gate insulating layer and connected to the source electrode, A protective film covering the data wiring, And a linear pixel electrode on the passivation layer of the pixel region defined by the intersection of the gate line and the data line, alternately formed with the common electrode, and electrically connected to the drain electrode through a first contact hole of the passivation layer. And at least one pixel electrode and at least one common electrode in each pixel area. The method of claim 21, And a redundant data line formed on the passivation layer and electrically connected to the data line through a second contact hole formed in the passivation layer. The method of claim 22, And a light blocking layer formed on the passivation layer and overlapping the data line and the common electrode adjacent to the data line. Board, A gate wiring formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate wiring on the substrate; A gate insulating film covering the gate wiring and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A data line including a source and a drain electrode formed on the ohmic contact layer and a data line formed on the gate insulating layer and connected to the source electrode, A linear pixel electrode formed alternately with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A redundancy data line covering the data line and an edge of which overlaps the common electrode adjacent to the data line; And at least one pixel electrode and at least one common electrode in each pixel area. The method of claim 24, And a common electrode line formed on the gate insulating layer and connected to the common electrode and separated from the gate line. The method of claim 25, And an amorphous silicon layer under the data line where the gate line, the common electrode line, the data line, and the redundant data line intersect. The method of claim 26, The redundant data line is formed of aluminum or an aluminum alloy. The method of claim 27, And the redundant data line passing over the amorphous silicon layer is formed only on the data line. Board, A gate wiring formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate wiring on the substrate; A gate insulating film covering the gate wiring and the common electrode, A semiconductor layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the semiconductor layer; A data line including a source and a drain electrode formed on the ohmic contact layer and a data line formed on the gate insulating layer and connected to the source electrode, A linear pixel electrode formed alternately with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A protective film covering the data line and the pixel electrode; A light blocking layer formed on the passivation layer and overlapping the data line and the common electrode or the pixel electrode adjacent to the data line; And at least one pixel electrode and at least one common electrode in each pixel area. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the substrate, and a common wiring including a common electrode and a common electrode line; Forming a gate insulating film covering the gate wiring and the common wiring; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a data line and a pixel electrode including a source and drain electrode, a data line, and a data pad as a first conductive layer, Depositing a passivation layer on the first conductive layer; Forming first and second contact holes in the passivation layer to expose the data line and the data pad, respectively; Forming a redundancy data line including a redundancy data line, a redundancy data pad, and a light blocking layer on the passivation layer. The method of claim 30, Forming a third contact hole exposing the gate pad by etching the gate insulating layer together in forming the first contact hole in the passivation layer, And forming a redundant gate pad in the forming of the redundant data line. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the substrate, and a common wiring including a common electrode and a common electrode line; Forming a gate insulating film covering the gate wiring and the common wiring; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a redundancy data line including a source and drain electrode, a redundancy data line, a redundancy data pad, a pixel electrode, and a light blocking film as a first conductive layer, Depositing a passivation layer on the first conductive layer; Forming first and second contact holes in the passivation layer to expose the redundant data line and the redundant data pad, respectively; Forming a data line including a data line and a data pad as a second conductive layer on the passivation layer. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the substrate, and a common wiring including a common electrode and a common electrode line; Forming a gate insulating film covering the gate wiring and the common wiring; Forming a semiconductor layer and an ohmic contact layer on the gate insulating layer; Forming a data line including a source and drain electrode, a data line, and a data pad as a first conductive layer, Depositing a passivation layer on the first conductive layer; Forming first, second and third contact holes in the passivation layer to expose the data line, the data pad and the drain electrode, respectively; Forming a redundant data line, a redundant data line including a redundant data pad, and a pixel electrode on the passivation layer. The method of claim 33, And forming a light blocking film in the step of forming the pixel electrode.