JP2800956B2 - Active matrix substrate - Google Patents

Active matrix substrate

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JP2800956B2
JP2800956B2 JP5181792A JP5181792A JP2800956B2 JP 2800956 B2 JP2800956 B2 JP 2800956B2 JP 5181792 A JP5181792 A JP 5181792A JP 5181792 A JP5181792 A JP 5181792A JP 2800956 B2 JP2800956 B2 JP 2800956B2
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formed
electrode
insulating film
active matrix
interlayer insulating
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JPH05257164A (en
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俊弘 山下
尚幸 島田
康浩 松島
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シャープ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136209Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、例えばアクティブマトリクス液晶表示装置等に用いられるアクティブマトリクス基板の製造方法に関するものである。 The present invention relates, for example, a manufacturing method of an active matrix substrate used for an active matrix liquid crystal display device or the like.

【0002】 [0002]

【従来の技術】近年、液晶等を表示媒体として用いたアクティブマトリクス表示装置が、活発に研究されている。 In recent years, active matrix display device using a liquid crystal or the like as a display medium has been actively studied. 中でも、液晶を用いたアクティブマトリクス型の表示装置は平面ディスプレイとして研究され、その成果も着実に上がっている。 Among them, an active matrix display device using a liquid crystal is studied as a flat display, the results also risen steadily. このようなアクティブマトリクス型液晶表示装置は、絵素電極、薄膜トランジスタ(TF Such an active matrix type liquid crystal display device, pixel electrodes, thin film transistors (TF
T)等が形成されたアクティブマトリクス基板と、対向電極が形成された対向基板と、これらを対向させた間に封入された液晶層とによって構成されている。 An active matrix substrate T) or the like is formed, is composed a counter substrate on which a counter electrode is formed by a liquid crystal layer sealed between these were allowed to face each other.

【0003】特に、小型かつ高精細に設計されたアクティブマトリクス型液晶表示装置(LCD)では、その設計上、絵素の面積が小さくなるので、絵素電極及び対向電極との間で形成されるコンデンサ容量が小さくなる。 In particular, the compact and high definition designed active matrix type liquid crystal display device (LCD), its design, since the pixel area is reduced, is formed between the pixel electrode and the counter electrode the capacitance of the capacitor is reduced.
従って、映像信号を必要な時間保持することが出来なくなるという問題が生じる。 Therefore, a problem that can not be held necessary time video signals. 加えて、絵素電極の電位に対するバス配線の電位の変動が大きくなるという問題も生じる。 In addition, also caused a problem that fluctuation in the potential of the bus lines is increased with respect to the potential of the picture element electrode. そこで、絵素電極と対向電極との容量不足を補うために付加容量が設けられる。 Therefore, the additional capacitance is provided to compensate for insufficient capacity of the picture element electrode and the counter electrode.

【0004】図4は、付加容量を備えた従来のアクティブマトリクス基板の絵素1個分の平面図を示し、図5はそのアクティブマトリクス基板のTFT25を通る断面図(図4におけるB−B´に沿った断面図)である。 [0004] Figure 4 shows a plan view of a pixel one portion of a conventional active matrix substrate having the additional capacitance, B-B'in Fig. 5 is a sectional view through the TFT25 of the active matrix substrate (Fig. 4 it is a cross-sectional view) along. このアクティブマトリクス基板は、絶縁性基板11上に、 The active matrix substrate, on the insulating substrate 11,
チャネル層12a、12b、ソース電極23及びドレイン電極24を有する多結晶シリコンからなる半導体層3 Channel layer 12a, 12b, the semiconductor layer 3 made of polycrystalline silicon having a source electrode 23 and drain electrode 24
0が形成されている。 0 is formed. 半導体層30のチャネル層12 The channel layer 12 of the semiconductor layer 30
a、12b以外の部分は、イオン注入法によるドーピングを行うことにより電気抵抗が低減されている。 a, portions other than 12b, the electric resistance is reduced by performing doping by ion implantation.

【0005】半導体層30を覆って基板11の上には、 [0005] covering the semiconductor layer 30 on the substrate 11,
ゲート絶縁膜13が形成され、このゲート絶縁膜13上には、n +またはp +のどちらか一方の多結晶Siからなるゲート電極3a、3bおよび付加容量電極6が形成されている。 The gate insulating film 13 is formed, the on the gate insulating film 13, n + or p + either one of the gate electrode 3a made of polycrystalline Si, 3b and the additional capacitance electrode 6 is formed. 上述のドーピングは、このゲート電極3a、 Doping described above, the gate electrode 3a,
3bをマスクとして行われる。 It is performed using 3b as a mask. ゲート電極3aは、図1 The gate electrode 3a, as shown in FIG. 1
に示すようにゲートバス配線1自身の一部からなり、ゲート電極3bはゲートバス配線1から分岐した部分で構成される。 It becomes a part of the gate bus lines 1 itself as shown in, the gate electrode 3b is constituted by branched portion from the gate bus line 1. 付加容量電極6は、図1に示すように帯状をした付加容量共通配線8の一部であり、付加容量共通配線8と絵素電極4との対向部分で付加容量が形成される。 Additional capacitance electrode 6 is a part of the additional capacitor common line 8 in which the strip as shown in FIG. 1, the additional capacitor is formed in the opposing portion between the additional capacitor common line 8 and the pixel electrode 4.

【0006】更に、ゲート電極3a及び3bを覆って基板11上の全面には、第1層間絶縁膜14が形成されている。 Furthermore, the entire surface of the substrate 11 to cover the gate electrodes 3a and 3b, the first interlayer insulating film 14 is formed. 第1層間絶縁膜14には、スルーホール7a及び7bが設けられている。 The first interlayer insulating film 14, through holes 7a and 7b are provided. スルーホール7aの上には、ソースバス配線2から分岐した金属層10aが形成されている。 On the through-hole 7a, the metal layer 10a branched from the source bus line 2 is formed. 更に、分岐した金属層10aとは、別に同時に形成された金属層10bが存在する。 Furthermore, the branched metal layer 10a, there is a metal layer 10b which separately formed simultaneously. ソースバス配線2 The source bus line 2
は、スルーホール7aを介してTFT25のソース電極23に接続されている。 It is connected to the source electrode 23 of the TFT25 via a through hole 7a. ここで、TFT25は、ゲート電極3a及び3bを有するデュアルゲートと呼ばれる構造が用いられている。 Here, TFT 25, a structure called a dual gate having a gate electrode 3a and 3b are used. 一方のコンタクトホール7bは、 One of the contact hole 7b is,
TFT25のドレイン電極24と金属層10bとの間における電気的接続を確実に行うためにAlなどの金属を使用して埋められる。 Filled with a metal such as Al in order to ensure the electrical connection between the drain electrode 24 and the metal layer 10b of the TFT 25.

【0007】その上には、第2層間絶縁膜17、遮光膜15、第3の層間絶縁膜18及び絵素電極4がこの順に形成されている。 [0007] thereon, a second interlayer insulating film 17, the light shielding film 15, the third interlayer insulating film 18 and the pixel electrodes 4 are formed in this order. 遮光膜15と前記金属層10bとは、 The light shielding film 15 and the metal layer 10b is,
第2層間絶縁膜17に設けたコンタクトホール9bを介して接続される。 It is connected via a contact hole 9b provided in the second interlayer insulating film 17. 遮光膜15は、Ti−W合金などで形成する。 The light shielding film 15 is formed like Ti-W alloy. この遮光膜15は、コンタクトホール7bを埋めるAl等の金属と、ITO等からなる絵素電極4との間におけるオーミックコンタクトを実現させる役割も担っている。 The light shielding film 15 plays a role to realize an ohmic contact between the metal such as Al to fill the contact hole 7b, a picture element electrode 4 made of ITO or the like. 遮光膜15と絵素電極4とは、第3の層間絶縁膜18に形成したコンタクトホール16bを介して接続される。 The light shielding film 15 and the pixel electrode 4 is connected via a contact hole 16b formed in the third interlayer insulating film 18.

【0008】 [0008]

【発明が解決しようとする課題】ところで、この従来基板においては、ゲートバス配線1の1つがオン状態となった後、最初にオン状態となるソースバス配線2では、 [SUMMARY OF THE INVENTION Incidentally, in this conventional substrate, after one of the gate bus lines 1 but which turned on, the source bus line 2 first becomes the on state,
このゲートバス配線1がオフ状態となるまでの時間が十分に長いので、ソースバス配線2を送られる映像信号が、絵素電極4及び付加容量電極6に余裕をもって書き込まれる。 Since the gate bus line 1 is sufficiently long time until the OFF state, the video signal sent to the source bus line 2 is written with a margin to the picture element electrode 4 and the additional capacitance electrode 6. しかし、最後にオン状態となるソースバス配線2では、ゲートバス配線1がオフ状態となるまでの時間が短いため、映像信号の書き込み時間が制約されるという問題がある。 However, the source bus line 2 is the last in the ON state, the gate bus line 1 is shorter the time until the OFF state, there is a problem that the writing time of the video signal is constrained.

【0009】更に、付加容量共通配線8がn +の多結晶Siで形成されているので抵抗が十分に小さいとは言えない。 Furthermore, additional capacitor common line 8 can not be said resistor because it is formed of n + polycrystalline Si is sufficiently small. そのため、付加容量共通配線8を送られる信号は遅延し、上述の制約された書き込み時間内に映像信号を書き込むことができなくなり、絵素電極4に書き込まれた電位に変動が引き起こされるという問題もある。 Therefore, the signal sent to the additional capacitor common line 8 is delayed, can not write the video signal in the above-described constrained writing time, a problem that fluctuation in potential written to the picture element electrode 4 is caused is there. この問題を、図6に基づいて説明する。 This problem will be described with reference to FIG.

【0010】図6は、1つの絵素部分の等価回路図を示す。 [0010] Figure 6 is an equivalent circuit diagram of one picture element portion. TFT31のドレイン電極32に接続された絵素電極33と、この絵素電極33に対向し、かつ対向電極配線が接続された対向電極34との間では、液晶層を挟んで容量CLCが形成される。 A pixel electrode 33 connected to the drain electrode 32 of the TFT 31, in between the counter electrode 34 that the facing to the picture element electrode 33 and the counter electrode wiring is connected, the capacitance CLC is formed across the liquid crystal layer that. また、TFT31のドレイン電極32は、付加容量CSを介して付加容量共通配線に接続されている。 The drain electrode 32 of the TFT31 is connected to the additional capacitor common line through an additional capacitor CS. 更に、TFT31のゲート電極35及びドレイン電極32との間では容量Cgdが形成されている。 Further, there is formed a capacitance Cgd is between the gate electrode 35 and the drain electrode 32 of the TFT 31.

【0011】このとき、TFTのゲートバス配線にゲートオンの信号が送られると、TFTはオン状態となり、 [0011] At this time, the signal of the gate is fed to the gate bus lines of TFT, TFT is turned on,
ソースバス配線には映像信号Vdが書き込まれる。 Video signal Vd is written in the source bus lines. ここで、付加容量共通配線の信号伝達の時定数をτCS、絵素電極への信号書き込み時間TONとすると、τCS《TONの条件が満たされない場合には、付加容量CSへの充電が不十分となり、絵素電極の電位が変動するという問題が生じる。 Here, TauCS the time constant of the signal transmission of the additional capacitor common line, when a signal writing period TON to the picture element electrode, when TauCS "TON conditions are not met, the charging of the additional capacitor CS is insufficient , a problem that the potential of the picture element electrode is changed occurs.

【0012】ところで、TFTがオフ状態となり、τCS [0012] By the way, TFT is turned off, τCS
に比べて十分に長い時間が経過した後における実際の表示状態に対応する絵素電極の電位Vd´は、下記の1式で表される。 Potential Vd' of the picture element electrodes corresponding to actual display condition in after a sufficiently long time has passed in comparison with is expressed by Equation 1 below.

【0013】 Vd´=Vd−{Cgd/(Cgd+CLC+CS)・△Vg}−a …(1) ここで、ΔVgは、TFTのオン状態の時のゲート電位とオフ状態の時のゲート電位との差である。 [0013] Vd' = Vd- {Cgd / (Cgd + CLC + CS) · △ Vg} -a ... (1) where, [Delta] Vg is the difference between the gate potential when the gate potential and the OFF state when the ON state of the TFT it is. aは、書き込み時間内に付加容量を十分充電できないために生じる電位の変動を表し、下記の2式で示される。 a represents a change in the potential caused can not be sufficiently charged the additional capacity within the write time, represented by the two equations below.

【0014】 a=Vd・exp(−Ton/τCS)・{CS/(Cgd+CLC+CS)} …(2) 上記1式における第2項は、TFTをオフ状態とするためにゲートバス配線の電圧が変動することによる絵素電極の電位の変動を表す。 [0014] The second term in a = Vd · exp (-Ton / τCS) · {CS / (Cgd + CLC + CS)} ... (2) above Expression 1, the variation voltage of the gate bus lines to the TFT an OFF state It represents the change in the potential of the picture element electrode due to. 書き込まれた映像信号によって忠実な表示を行わせるためには、1式の第2項及び2式のaの値を小さくしなければならない。 To carry out the faithful displayed by the written video signal, it is necessary to reduce the value of the second term and two equations of a in equation (1). 1式の第2項の値を小さくするためには、 Cgd《CLC+CS …(3) が成り立つことが必要である。 In order to reduce the value of the second term of equation (1) is, Cgd "CLC + CS ... (3) it is necessary to hold. 高精細のアクティブマトリクス基板では絵素電極が、小さくCLCが小さいので、 Since the active matrix substrate of the high-definition picture element electrodes, small CLC is small,
3式の条件を満たすにはある程度の大きさの付加容量C 3 wherein additional capacitance C of a certain size to meet the
Sが必要となる。 S is required.

【0015】このように付加容量CSは或る程度の大きさが必要なので、aの値を小さくするためには、 Ton《τCS …(4) が成り立つことが必要である。 [0015] Since the need thus additional capacitor CS is the size of some extent, to reduce the value of a is, Ton "τCS ... (4) it is necessary to hold. 特に、駆動回路をTFT In particular, the driving circuit TFT
アレイと同一の基板上に形成した小型かつ高精細のアクティブマトリクス基板では、上記4式の条件を満たすには困難が伴う。 Array The small size and high definition active matrix substrate was formed on the same substrate and, with difficulty in satisfying the above four equations. その理由を次に示す。 The following reason.

【0016】ゲートバス配線の本数が多くなり、ゲートバス配線1本当たりに割り当てられる時間が短くなる。 [0016] increases the number of gate bus lines, time allocated per gate bus lines one is shorter.

【0017】ドライバICを実装する方式では、全てのソースバス配線に同時に映像信号が出力されるので問題ないが、パネルサンプルホールド方式を採用する場合には、それぞれのソースバス配線に順次映像信号が出力されるので、最後に書き込みが行われるソースバス配線における書き込み時間が短くなる。 [0017] in a manner that the driver IC is mounted is no problem since at the same time the video signal to all of the source bus lines is output, when employing a panel sample hold system is sequentially video signal to each source bus line since the output, the writing time in the last source bus wiring is written becomes short.

【0018】表示装置の高精細化に伴う開口率の低下を防ぐため、配線の線幅を狭くする必要がある。 [0018] In order to prevent a decrease in aperture ratio due to the high definition of the display device, it is necessary to narrow the line width of the wiring. そのため付加容量共通配線の抵抗が大きくなり、τCSを小さくすることができない。 Therefore the resistance of the additional capacitor common line becomes greater, it is impossible to reduce the TauCS.

【0019】絵素数が増加しても1絵素あたりの付加容量共通電極の大きさを小さくすることができない。 [0019] can not picture primes to reduce the size of the additional capacitor common electrode per pixel be increased. 従って、1本の付加容量共通配線に接続される付加容量の総和が大きくなり、τCSを小さくすることができない。 Therefore, the sum of the additional capacitance connected to one additional capacitor common line becomes greater, it is impossible to reduce the TauCS.

【0020】このような問題点の解決策として、付加容量共通配線の両端に対向電極と同電位の電圧を印加することが考えるが、それだけでは付加容量共通配線の抵抗が十分に小さくならないために十分な解決策とは言えない。 [0020] As a solution to this problem, because think applying a voltage of the counter electrode and the same potential to both ends of the additional capacitor common lines, but only the resistance of the additional capacitor common line is not sufficiently small not sufficient solution.

【0021】本発明はこのような問題点を解決するものであり、映像信号を送る配線の抵抗を小さくして信号遅延を生じにくくできるアクティブマトリクス基板を提供することを目的とする。 [0021] The present invention has been made to solve the above problems, and an object thereof is to provide an active matrix substrate which can hardly produce small to signal delay the resistance of the wiring for sending a video signal.

【0022】 [0022]

【課題を解決するための手段】本発明のアクティブマトリクス基板は、 薄膜トランジスタ、付加容量電極及び付 The active matrix substrate SUMMARY OF THE INVENTION The present invention relates to a thin film transistor, the additional capacitance electrode with and
加容量共通配線が形成された基板上に第1の層間絶縁膜 The first interlayer insulating film in pressurized capacitor common line is formed on the substrate
を介して形成された遮光膜と、該遮光膜上に第2の層間 A light shielding film formed over the second interlayer on the light shielding film
絶縁膜を介して形成された絵素電極とを有し、該遮光膜 And a pixel electrode formed through an insulating film, the light blocking film
が、該第1の層間絶縁膜に形成されたコンタクトホール Contact holes but formed in the first interlayer insulating film
を介して該付加容量共通配線に電気的に接続され、か Via electrically connected to said additional capacitor common lines, or
つ、該絵素電極が該第1の層間絶縁膜及び該第2の層間 One, an interlayer insulating said 1 picture elements electrode film and said second interlayer
絶縁膜に形成された各コンタクトホールを介して該薄膜 Thin film through the contact holes formed in the insulating film
トランジスタに電気的に接続されており、そのことにより上記目的を達成できる。 Are electrically connected to the transistor, the above object can be achieved by it.

【0023】前記遮光膜は、W、Ti、Mo又はTi− [0023] The light-shielding film, W, Ti, Mo or Ti-
W合金で形成してもよい。 It may be formed of a W alloy.

【0024】 [0024]

【作用】本発明にあっては、 遮光膜が、薄膜トランジス In the the present invention, light-shielding film, a thin film transistor
タ、付加容量電極及び付加容量共通配線が形成された基 Data, the additional capacitance electrodes and the additional capacitor common lines are formed based on
板上に第1の層間絶縁膜を介して形成されると共に 、遮光膜と付加容量共通配線とが第1の層間絶縁膜に設けたコンタクトホールを介して電気的に接続されているので、遮光膜と付加容量共通配線とが並列接続された回路構成となり、抵抗が小さくなる。 Together they are formed through the first interlayer insulating film on the plate, since the additional capacitor common line and the light shielding film is electrically connected through a contact hole formed in the first interlayer insulating film, the light-shielding becomes film and the additional capacitor common line and are connected in parallel circuit configuration, the resistance decreases.

【0025】 [0025]

【実施例】図3にアクティブマトリクス表示装置の平面模式図を示す。 It shows a schematic plan view of an active matrix display device in Embodiment] FIG.

【0026】この表示装置は、ガラス等の絶縁膜基板1 [0026] The display device includes an insulating film substrate 1 of glass or the like
1上にゲート駆動回路54、ソース駆動回路55及びT The gate drive circuit 54 on 1, the source driver circuit 55 and the T
FTアレイ部53が形成されている。 FT array part 53 is formed. TFTアレイ部5 TFT array part 5
3には、ゲート駆動回路54から延びる多数の平行する走査線としてのゲートバス配線1が配されている。 3, the gate bus lines 1 as scanning lines number of parallel extending from the gate drive circuit 54 is disposed. ソース駆動回路55からは信号線としての多数のソースバス配線2がゲートバス配線1に直交して配設されている。 Numerous source bus lines as signal lines 2 are arranged perpendicular to the gate bus line 1 from the source driving circuit 55.
更に、ソースバス配線2と平行に、付加容量共通配線8 Furthermore, in parallel to the source bus line 2, the additional capacitor common line 8
が配設されている。 There has been arranged.

【0027】2本のゲートバス配線1の間であって、ソースバス配線2及び付加容量共通配線8で挟まれた矩形の領域には、TFT25、絵素57及び付加容量27が設けられている。 [0027] A between the gate bus lines 1 two, in the rectangular region between the source bus lines 2 and additional capacitor common line 8, TFT 25, pixel 57 and additional capacitor 27 is provided . TFT25のゲート電極はゲートバス配線1に接続され、ソース電極はソースバス配線2に接続されている。 The gate electrode of the TFT25 is connected to the gate bus lines 1, the source electrode is connected to the source bus line 2. 絵素57は、TFT25のドレイン電極に接続された絵素電極と対向基板上の対向電極との間に、液晶が封入されて構成されている。 Picture element 57, between the counter electrode on the attached picture element electrode and the counter substrate to the drain electrode of the TFT 25, the liquid crystal is formed is sealed. また、付加容量共通配線8は、対向電極と同じ電位の電極に接続されている。 The additional capacitor common line 8 is connected to the electrodes of the same potential as the counter electrode.

【0028】図1は本実施例のアクティブマトリクス基板における絵素1個分の平面図を示す。 [0028] Figure 1 shows a plan view of a pixel one minute in the active matrix substrate of this embodiment. 図2は図1におけるA−A´に沿った断面図である。 Figure 2 is a sectional view taken along the A-A'in Fig. このアクティブマトリクス基板の構成を、製造工程に従って説明する。 The structure of the active matrix substrate will be described according to the manufacturing process.

【0029】まず、絶縁性基板11上に、例えばCVD Firstly, on the insulating substrate 11, for example, CVD
法によって多結晶Siからなる半導体層30をパターン形成した後、基板11上の全面にゲート絶縁膜13となる絶縁膜を形成した。 After the semiconductor layer 30 is patterned made of polycrystalline Si by law, to form an insulating film serving as a gate insulating film 13 on the entire surface of the substrate 11. この絶縁膜は、例えばCVD法、 The insulating film is, for example, a CVD method,
スパッタリング法、又は上記多結晶Si薄膜30の上面を熱酸化する方式により形成される。 Sputtering, or the upper surface of the polycrystalline Si thin film 30 is formed by method of thermal oxidation. ゲート絶縁膜13 Gate insulating film 13
の厚さは、例えば約100nmである。 The thickness of, for example, about 100 nm. また、半導体層30の層厚は、例えば40〜80nmである。 The layer thickness of the semiconductor layer 30 is, for example, 40 to 80 nm.

【0030】次に、低抵抗の多結晶Siを付着した後にパターニングを行って、ゲートバス配線1、ゲート電極3a、3b及び付加容量共通配線8を形成した。 Next, by patterning after depositing a polycrystalline Si of the low-resistance, gate bus lines 1, gate electrodes 3a, to form 3b and additional capacitor common line 8. 付加容量共通配線8は、図1のように突出形成した部分である付加容量電極6を含んだものである。 Additional capacitor common line 8 is one that includes the additional capacitance electrode 6 is protruded portion as shown in Fig. 次いで、上記ゲート電極3a及び3bをマスクとし、かつフォトリソグラフィー法によって形成されたマスクを用いて半導体層3 Then, the semiconductor layer 3 with the gate electrodes 3a and 3b as a mask, and is formed by a photolithography mask
0のゲート電極の下方以外の部分にイオン注入を行う。 Ions are implanted into a portion other than below the gate electrode of the 0.
これにより、半導体層30にチャネル層12a、12b Thus, the channel layer 12a on the semiconductor layer 30, 12b
が形成される。 There is formed.

【0031】その後、この基板上の全面に第1層間絶縁膜14を、例えば700nmの厚さに形成した。 [0031] Thereafter, a first interlayer insulating film 14 on the entire surface of the substrate was formed in a thickness of, for example, 700 nm. 次に、 next,
第1層間絶縁膜14の所定箇所にコンタクトホール7 Contact hole 7 at a predetermined position of the first interlayer insulating film 14
a、7b及びコンタクトホール7cを形成した。 a, to form 7b and the contact hole 7c. 各コンタクトホール7a、7b、7cは、それぞれソース電極23、ドレイン電極24、付加容量共通配線8の上に配設されている。 The contact holes 7a, 7b, 7c, the source electrode 23, respectively, the drain electrodes 24, are disposed above the additional capacitor common line 8.

【0032】次に、ソースバス配線2及び、金属層10 [0032] Next, the source bus line 2 and the metal layer 10
a、10b、10c等をAl等の低抵抗の金属を用いて同時に形成した。 a, 10b, and 10c, etc. by using a low resistance metal such as Al is formed at the same time. このとき、金属層10a、10b、1 The metal layer 10a, 10b, 1
0cは、それぞれコンタクトホール7a、7b、7cを埋めるように形成され、ソース電極23、ドレイン電極24、付加容量共通配線8と接続される。 0c each contact holes 7a, 7b, are formed so as to fill the 7c, the source electrode 23, drain electrode 24 is connected to the additional capacitor common line 8. 第1層間絶縁膜14の上に飛び出している金属層10a、10b、1 Metal layer 10a that protrudes on the first interlayer insulating film 14, 10b, 1
0cの層厚は、例えば600nmである。 The thickness of the 0c is, for example, 600nm. なお、金属層10aはソースバス配線2から分岐させた部分であり、 The metal layer 10a is a portion which is branched from the source bus line 2,
ソースバス配線2は金属層10a及びコンタクトホール7aを介してソース電極23に接続される。 Source bus lines 2 is connected to the source electrode 23 via the metal layer 10a and the contact hole 7a.

【0033】次に、この基板上の全面に第2層間絶縁膜17を、例えばCVD法によって600nmの厚さに形成した。 Next, a second interlayer insulating film 17 on the entire surface of the substrate, for example, formed to a thickness of 600nm by CVD. 次に、第2層間絶縁膜17にコンタクトホール9b、9cを形成した。 Next, a contact hole 9b in the second interlayer insulating film 17 was formed 9c. コンタクトホール9bはドレイン電極を接続するためのものであり、コンタクトホール9cは遮光膜15と付加容量共通配線8を電気的に接続するためのものである。 Contact hole 9b is for connecting the drain electrode, the contact hole 9c is for electrically connecting the additional capacitor common line 8 and the light-shielding film 15.

【0034】次に、遮光膜15を、TFT25の上部の他、コンタクトホール9b、9cを埋めるようにパターン形成した。 Next, the light shielding film 15, another upper portion of the TFT 25, and patterned so as to fill the contact hole 9b, the 9c. 遮光膜15の材料は、例えばTi−W合金などの金属を使用し、厚みは例えば120〜150nm Material of the light shielding film 15, for example using a metal such as Ti-W alloy, the thickness is for example 120~150nm
とした。 And the. コンタクトホール9bの周りは、遮光膜15が存在しないが、この部分には金属層10bが形成されているので、遮光膜15が無い部分から光が漏れるということはない。 Around the contact hole 9b is the light shielding film 15 is not present, since this is the part that the metal layer 10b is formed, is not that the light leaks from portions no light shielding film 15. なお、遮光膜15は、上述のTi−W合金の他に、W、Ti、Moなどの金属を使用できる。 Incidentally, the light-shielding film 15, in addition to the Ti-W alloy described above, W, Ti, a metal such as Mo may be used. また、コンタクトホール9b上の遮光膜15は、ドレイン電極24と、後述する絵素電極4とのオーミックコンタクトを取るためのものである。 The light-shielding film 15 on the contact hole 9b includes a drain electrode 24, is for the ohmic contact of the picture element electrode 4 to be described later.

【0035】その後、第3の層間絶縁膜18を200n [0035] Then, a third interlayer insulation film 18 200n
m形成し、コンタクトホール16bをあけて絵素電極4 And m is formed, the pixel electrode 4 at a contact hole 16b
を形成した。 It was formed.

【0036】したがって、このように構成された本実施例のアクティブマトリクス基板においては、遮光膜15 [0036] Thus, in the active matrix substrate of the present embodiment constructed as described above, the light-shielding film 15
と付加容量共通配線8とが平行に形成されており、遮光膜15と付加容量共通配線8とが第1、第2層間絶縁膜14、17にそれぞれ設けたコンタクトホール7c、9 The additional capacitance common line 8 are formed in parallel, the light-shielding film 15 and the additional capacitor common line 8 and the first contact hole 7c is provided respectively in the second interlayer insulating film 14 and 17, 9
cを介して電気的に接続されているので、遮光膜15と付加容量共通配線8とが並列接続された回路構成となって抵抗が小さくなり、信号遅延の発生を抑制できる。 Since they are electrically connected through the c, the light shielding film 15 and the additional capacitor common line 8 becomes parallel connected circuit structure resistance is reduced, it is possible to suppress the occurrence of signal delay.

【0037】また、付加容量共通配線8と遮光膜15とが2層構造となっているので、開口率を上げるために付加容量共通配線8の線幅を細くしたときに生じる断線を防ぐことができる。 Further, since the additional capacitor common line 8 and the light-shielding film 15 has a two-layer structure, it is possible to prevent disconnection occurring when the thin line width of the additional capacitor common line 8 in order to increase the aperture ratio it can.

【0038】 [0038]

【発明の効果】以上詳述したように、本発明のアクティブマトリクス基板は、遮光膜と付加容量共通配線とが並列接続された回路構成となって抵抗が小さくなり、信号遅延の発生を抑制できる。 As described in detail above, the active matrix substrate of the present invention, the additional capacitor common line and the light-shielding film is a parallel-connected circuit configuration resistance is reduced, it is possible to suppress the occurrence of the signal delay . また、付加容量共通配線と遮光膜とが2層構造となっているので、断線を防止した状態で付加容量共通配線の線幅を小さくなし得、これにより開口率の大きい、明るい画面を有する高精細な表示装置を提供することができる。 Further, since the additional capacitor common line and the light-shielding film has a two-layer structure, obtained Nashi reduce the line width of the additional capacitor common line while preventing disconnection, thereby the aperture ratio large, high has a bright screen it is possible to provide a fine display.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本実施例のアクティブマトリクス基板における絵素1個分を示す平面図。 Plan view showing one minute picture elements in the active matrix substrate disclosed exemplary embodiment.

【図2】図1のA−A´に沿った断面図。 2 is a cross-sectional view taken along the A-A'in Fig.

【図3】図1のアクティブマトリクス基板を備えたアクティブマトリクス表示装置の平面模式図。 Figure 3 is a plan schematic view of an active matrix display device including the active matrix substrate of FIG.

【図4】従来のアクティブマトリクス基板における絵素1個分の平面図。 [4] 1 pieces of plan view of a pixel in a conventional active matrix substrate.

【図5】図4のB−B´に沿った断面図。 5 is a sectional view taken along the B-B'in Fig.

【図6】絵素部分の等価回路図。 FIG. 6 is an equivalent circuit diagram of the pixel portion.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 ゲートバス配線 2 ソースバス配線 3a、3b ゲート電極 4 絵素電極 6 付加容量電極 7a、7b、7c コンタクトホール 8 付加容量共通電極 9b、9c コンタクトホール 10a、10b、10c 金属層 11 絶縁性基板 12a、12b チャネル層 13 ゲート絶縁膜 14 第1層間絶縁膜 15 遮光膜 16b コンタクトホール 17 第2層間絶縁膜 18 第3層間絶縁膜 23 ソース電極 24 ドレイン電極 25 TFT 30 半導体層 First gate bus line 2 source bus lines 3a, 3b gate electrode 4 pixel electrode 6 additional capacitor electrodes 7a, 7b, 7c contact hole 8 additional capacitor common electrode 9b, 9c contact holes 10a, 10b, 10c metal layer 11 insulating substrate 12a , 12b the channel layer 13 gate insulating film 14 first interlayer insulation film 15 shielding film 16b contact hole 17 second interlayer insulating film 18 third interlayer insulating film 23 source electrode 24 drain electrode 25 TFT 30 semiconductor layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl. 6 ,DB名) G02F 1/136 500 ────────────────────────────────────────────────── ─── of the front page continued (58) investigated the field (Int.Cl. 6, DB name) G02F 1/136 500

Claims (2)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】 薄膜トランジスタ、付加容量電極及び付 1. A thin film transistor, the additional capacitance electrodes with and
    加容量共通配線が形成された基板上に第1の層間絶縁膜 The first interlayer insulating film in pressurized capacitor common line is formed on the substrate
    を介して形成された遮光膜と、 該遮光膜上に第2の層間絶縁膜を介して形成された絵素 A light-shielding film formed through a picture element which is formed through the second interlayer insulating film on the light shielding film
    電極とを有し、 該遮光膜が、該第1の層間絶縁膜に形成されたコンタク And an electrode, the light-shielding film is formed on the first interlayer insulating film contactors
    トホールを介して該付加容量共通配線に電気的に接続さ Via Tohoru it is electrically connected to said additional capacitor common line
    れ、かつ、該絵素電極が該第1の層間絶縁膜及び該第2 Is, and, inter picture elements electrodes of the first insulating film and the second
    の層間絶縁膜に形成された各コンタクトホールを介して Through each contact hole formed in the interlayer insulating film
    該薄膜トランジスタに電気的に接続されているアクティブマトリクス基板。 Active matrix substrate are electrically connected to the thin film transistor.
  2. 【請求項2】 前記遮光膜がW、Ti、Mo、Ti−W Wherein said light-shielding film W, Ti, Mo, Ti-W
    合金からなる請求項1記載のアクティブマトリクス基板。 The active matrix substrate according to claim 1, wherein an alloy.
JP5181792A 1992-03-10 1992-03-10 Active matrix substrate Expired - Lifetime JP2800956B2 (en)

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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0926603A (en) 1995-05-08 1997-01-28 Semiconductor Energy Lab Co Ltd Display device
KR970011972A (en) * 1995-08-11 1997-03-29 쯔지 하루오 Transmission type liquid crystal display device and manufacturing method thereof
US5917563A (en) 1995-10-16 1999-06-29 Sharp Kabushiki Kaisha Liquid crystal display device having an insulation film made of organic material between an additional capacity and a bus line
JP3647542B2 (en) 1996-02-20 2005-05-11 株式会社半導体エネルギー研究所 The liquid crystal display device
US6940566B1 (en) 1996-11-26 2005-09-06 Samsung Electronics Co., Ltd. Liquid crystal displays including organic passivation layer contacting a portion of the semiconductor layer between source and drain regions
TW482918B (en) * 1998-03-19 2002-04-11 Seiko Epson Corp Liquid crystal device and projection-type display apparatus
JP2000075280A (en) * 1998-08-28 2000-03-14 Sony Corp Liquid crystal display device
US6850292B1 (en) 1998-12-28 2005-02-01 Seiko Epson Corporation Electric-optic device, method of fabricating the same, and electronic apparatus
JP4860293B2 (en) * 1999-02-12 2012-01-25 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6576924B1 (en) * 1999-02-12 2003-06-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having at least a pixel unit and a driver circuit unit over a same substrate
EP1031873A3 (en) * 1999-02-23 2005-02-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
JP2000276078A (en) 1999-03-23 2000-10-06 Sanyo Electric Co Ltd Organic electroluminescence display device
US6750835B2 (en) * 1999-12-27 2004-06-15 Semiconductor Energy Laboratory Co., Ltd. Image display device and driving method thereof
KR100626910B1 (en) 2002-05-21 2006-09-20 세이코 엡슨 가부시키가이샤 Electro-optical device and electronic equipment
JP2006243753A (en) * 2006-05-19 2006-09-14 Seiko Epson Corp Substrate device, optoelectronic device, and electronic instrument
JP4967631B2 (en) * 2006-12-07 2012-07-04 三菱電機株式会社 Display device
JP2008065356A (en) * 2007-11-26 2008-03-21 Sony Corp Liquid crystal display device
JP5158131B2 (en) * 2010-05-21 2013-03-06 セイコーエプソン株式会社 Electro-optical device and projector
JP2011002855A (en) * 2010-09-22 2011-01-06 Semiconductor Energy Lab Co Ltd Liquid crystal display
JP5526187B2 (en) * 2012-05-07 2014-06-18 株式会社半導体エネルギー研究所 Display device
JP2015007806A (en) * 2014-09-12 2015-01-15 株式会社半導体エネルギー研究所 Liquid crystal display device
CN106597771B (en) * 2017-01-19 2019-07-26 厦门天马微电子有限公司 Array substrate, liquid crystal display panel and display device

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