JP2800956B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix substrate used for, for example, an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, active matrix display devices using a liquid crystal or the like as a display medium have been actively studied. In particular, active matrix display devices using liquid crystals have been studied as flat displays, and the results have been steadily increasing. Such an active matrix type liquid crystal display device includes a pixel electrode, a thin film transistor (TF)
T) and the like, an active matrix substrate formed with a counter electrode, a counter substrate formed with a counter electrode, and a liquid crystal layer sealed between these substrates.

In particular, in an active matrix type liquid crystal display (LCD) designed to be small and high definition, the area of a picture element is small due to its design, so that it is formed between a picture element electrode and a counter electrode. The capacitance of the capacitor becomes smaller.
Therefore, there is a problem that the video signal cannot be held for a required time. In addition, there is a problem that the potential of the bus wiring greatly varies with respect to the potential of the pixel electrode. Therefore, an additional capacitance is provided to compensate for the lack of capacitance between the pixel electrode and the counter electrode.

FIG. 4 is a plan view of one picture element of a conventional active matrix substrate provided with an additional capacitor, and FIG. 5 is a cross-sectional view taken along a TFT 25 of the active matrix substrate (BB 'in FIG. 4). FIG. This active matrix substrate is provided on an insulating substrate 11,
Semiconductor layer 3 made of polycrystalline silicon having channel layers 12a and 12b, source electrode 23 and drain electrode 24
0 is formed. Channel layer 12 of semiconductor layer 30
The portions other than a and 12b are subjected to doping by ion implantation to reduce the electric resistance.

[0005] On the substrate 11 covering the semiconductor layer 30,
A gate insulating film 13 is formed, and on this gate insulating film 13, gate electrodes 3a, 3b and additional capacitance electrode 6 made of either n ⁺ or p ⁺ polycrystalline Si are formed. The above-described doping is performed by the gate electrode 3a,
3b is used as a mask. The gate electrode 3a is shown in FIG.
As shown in (1), the gate bus line 1 is composed of a part of itself, and the gate electrode 3b is composed of a portion branched from the gate bus line 1. The additional capacitance electrode 6 is a part of a band-shaped additional capacitance common line 8 as shown in FIG. 1, and an additional capacitance is formed at a portion where the additional capacitance common line 8 and the pixel electrode 4 face each other.

Further, a first interlayer insulating film 14 is formed on the entire surface of the substrate 11 covering the gate electrodes 3a and 3b. In the first interlayer insulating film 14, through holes 7a and 7b are provided. On the through hole 7a, a metal layer 10a branched from the source bus wiring 2 is formed. Further, there is a metal layer 10b formed simultaneously and separately from the branched metal layer 10a. Source bus wiring 2
Is connected to the source electrode 23 of the TFT 25 via the through hole 7a. Here, the TFT 25 has a structure called a dual gate having gate electrodes 3a and 3b. One contact hole 7b is
In order to ensure electrical connection between the drain electrode 24 of the TFT 25 and the metal layer 10b, it is filled with a metal such as Al.

A second interlayer insulating film 17, a light-shielding film 15, a third interlayer insulating film 18, and a pixel electrode 4 are formed thereon in this order. The light-shielding film 15 and the metal layer 10b
The connection is made via a contact hole 9b provided in the second interlayer insulating film 17. The light-shielding film 15 is formed of a Ti-W alloy or the like. The light-shielding film 15 also has a role of realizing an ohmic contact between the metal such as Al filling the contact hole 7b and the pixel electrode 4 made of ITO or the like. The light-shielding film 15 and the picture element electrode 4 are connected via a contact hole 16b formed in the third interlayer insulating film 18.

[0008]

By the way, in this conventional substrate, after one of the gate bus lines 1 is turned on, the source bus line 2 which is first turned on is:
Since the time until the gate bus line 1 is turned off is sufficiently long, the video signal sent through the source bus line 2 is written into the picture element electrode 4 and the additional capacitance electrode 6 with a margin. However, in the source bus line 2 which is finally turned on, the time until the gate bus line 1 is turned off is short, so that there is a problem that the writing time of the video signal is restricted.

Further, since the additional capacitance common wiring 8 is formed of n ⁺ polycrystalline Si, the resistance cannot be said to be sufficiently small. Therefore, the signal sent to the additional capacitance common line 8 is delayed, so that the video signal cannot be written within the above-mentioned limited writing time, and the potential written to the pixel electrode 4 fluctuates. is there. This problem will be described with reference to FIG.

FIG. 6 shows an equivalent circuit diagram of one picture element portion. A capacitor CLC is formed between a pixel electrode 33 connected to the drain electrode 32 of the TFT 31 and a counter electrode 34 facing the pixel electrode 33 and connected to a counter electrode wiring with a liquid crystal layer interposed therebetween. You. The drain electrode 32 of the TFT 31 is connected to an additional capacitance common line via an additional capacitance CS. Further, a capacitance Cgd is formed between the gate electrode 35 and the drain electrode 32 of the TFT 31.

At this time, when a gate-on signal is sent to the gate bus wiring of the TFT, the TFT is turned on,
The video signal Vd is written to the source bus wiring. Here, assuming that the time constant of signal transmission of the additional capacitance common wiring is τCS and the signal writing time TON to the picture element electrode is τCS << TON, if the condition of TON is not satisfied, the charging of the additional capacitance CS becomes insufficient. This causes a problem that the potential of the pixel electrode fluctuates.

By the way, the TFT is turned off, and τCS
The potential Vd 'of the picture element electrode corresponding to the actual display state after a sufficiently long time has elapsed is expressed by the following equation.

Vd '= Vd- {Cgd / (Cgd + CLC + CS) .multidot.Vg} -a (1) Here, .DELTA.Vg is the difference between the gate potential when the TFT is on and the gate potential when it is off. It is. “a” represents a change in potential caused by insufficient charging of the additional capacitance within the writing time, and is represented by the following two equations.

A = Vd · exp (−Ton / τCS) · {CS / (Cgd + CLC + CS)} (2) The second term in the above equation is that the voltage of the gate bus line fluctuates to turn off the TFT. This indicates a change in the potential of the picture element electrode due to the above. In order to perform a faithful display by the written video signal, the value of the second term in Equation 1 and the value of a in Equation 2 must be reduced. In order to reduce the value of the second term of the equation (1), it is necessary that Cgd << CLC + CS (3) holds. In a high-definition active matrix substrate, the pixel electrodes are small and the CLC is small.
In order to satisfy the condition of Equation (3), a certain amount of additional capacitance C is required.
S is required.

As described above, since the additional capacitance CS needs to have a certain size, it is necessary to satisfy Ton << τCS (4) in order to reduce the value of a. In particular, the driving circuit is TFT
With a small and high-definition active matrix substrate formed on the same substrate as the array, it is difficult to satisfy the above four conditions. The reason is as follows.

The number of gate bus lines increases, and the time allocated per gate bus line decreases.

In the method of mounting the driver IC, there is no problem because the video signal is output to all the source bus wirings at the same time. However, when the panel sample and hold method is adopted, the video signal is sequentially transmitted to each source bus wiring. Since the data is output, the writing time in the source bus line where the writing is performed last is shortened.

It is necessary to reduce the line width of the wiring in order to prevent a decrease in the aperture ratio due to the high definition of the display device. Therefore, the resistance of the additional capacitance common wiring increases, and τCS cannot be reduced.

Even if the number of picture elements increases, the size of the additional capacitance common electrode per picture element cannot be reduced. Therefore, the sum of the additional capacitances connected to one additional capacitance common wiring increases, and τCS cannot be reduced.

As a solution to such a problem, it is conceivable to apply a voltage having the same potential as that of the counter electrode to both ends of the additional capacitance common line. However, this alone does not reduce the resistance of the additional capacitance common line sufficiently. Not a good solution.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide an active matrix substrate in which the resistance of a wiring for transmitting a video signal is reduced so that a signal delay is hardly caused.

[0022]

According to the present invention, there is provided an active matrix substrate comprising: a thin film transistor; an additional capacitance electrode;
A first interlayer insulating film on the substrate on which the added capacitance common wiring is formed;
And a second interlayer on the light-shielding film
A pixel electrode formed with an insulating film interposed therebetween;
Are contact holes formed in the first interlayer insulating film.
Is electrically connected to the additional capacitance common wiring through
The pixel electrode is formed between the first interlayer insulating film and the second interlayer insulating film;
The thin film through each contact hole formed in the insulating film
The transistor is electrically connected to the transistor , so that the above object can be achieved.

The light shielding film is made of W, Ti, Mo or Ti-
It may be formed of a W alloy.

[0024]

According to the present invention, the light shielding film is a thin film transistor.
On which the capacitor, additional capacitance electrode and additional capacitance common wiring are formed.
Since the light-shielding film and the additional capacitance common wiring are electrically connected via the contact holes provided in the first interlayer insulating film, the light-shielding film is formed on the board via the first interlayer insulating film. The circuit configuration is such that the film and the additional capacitance common wiring are connected in parallel, and the resistance is reduced.

[0025]

FIG. 3 is a schematic plan view of an active matrix display device.

This display device has an insulating film substrate 1 made of glass or the like.
1, a gate drive circuit 54, a source drive circuit 55 and T
An FT array section 53 is formed. TFT array unit 5
3, a gate bus line 1 as a number of parallel scanning lines extending from the gate drive circuit 54 is provided. From the source drive circuit 55, a number of source bus lines 2 as signal lines are arranged orthogonal to the gate bus lines 1.
Further, in parallel with the source bus wiring 2, the additional capacitance common wiring 8
Are arranged.

A TFT 25, a picture element 57 and an additional capacitor 27 are provided in a rectangular area between the two gate bus lines 1 and between the source bus line 2 and the additional capacitor common line 8. . The gate electrode of the TFT 25 is connected to the gate bus line 1, and the source electrode is connected to the source bus line 2. The picture element 57 is configured such that liquid crystal is sealed between the picture element electrode connected to the drain electrode of the TFT 25 and the counter electrode on the counter substrate. Further, the additional capacitance common wiring 8 is connected to an electrode having the same potential as the counter electrode.

FIG. 1 is a plan view of one picture element on the active matrix substrate of this embodiment. FIG. 2 is a sectional view taken along the line AA ′ in FIG. The configuration of this active matrix substrate will be described according to the manufacturing process.

First, for example, CVD is performed on the insulating substrate 11.
After patterning the semiconductor layer 30 made of polycrystalline Si by the method, an insulating film to be the gate insulating film 13 was formed on the entire surface of the substrate 11. This insulating film is formed, for example, by a CVD method,
It is formed by a sputtering method or a method in which the upper surface of the polycrystalline Si thin film 30 is thermally oxidized. Gate insulating film 13
Is about 100 nm, for example. The thickness of the semiconductor layer 30 is, for example, 40 to 80 nm.

Next, patterning was performed after low-resistance polycrystalline Si was deposited, thereby forming the gate bus wiring 1, the gate electrodes 3a and 3b, and the additional capacitance common wiring 8. The additional capacitance common wiring 8 includes the additional capacitance electrode 6 which is a protruding portion as shown in FIG. Then, using the gate electrodes 3a and 3b as a mask and a mask formed by photolithography, the semiconductor layer 3 is formed.
Ion implantation is performed on portions other than below the 0 gate electrode.
Thereby, the channel layers 12a and 12b are formed in the semiconductor layer 30.
Is formed.

Thereafter, a first interlayer insulating film 14 was formed on the entire surface of the substrate to a thickness of, for example, 700 nm. next,
A contact hole 7 is formed in a predetermined portion of the first interlayer insulating film 14.
a, 7b and a contact hole 7c were formed. The contact holes 7a, 7b, 7c are provided on the source electrode 23, the drain electrode 24, and the additional capacitance common wiring 8, respectively.

Next, the source bus wiring 2 and the metal layer 10
a, 10b, 10c, etc. were simultaneously formed using a low resistance metal such as Al. At this time, the metal layers 10a, 10b, 1
0c is formed to fill the contact holes 7a, 7b, 7c, respectively, and is connected to the source electrode 23, the drain electrode 24, and the additional capacitance common wiring 8. The metal layers 10a, 10b, 1 protruding above the first interlayer insulating film 14
The layer thickness of 0c is, for example, 600 nm. The metal layer 10a is a portion branched from the source bus wiring 2,
Source bus line 2 is connected to source electrode 23 via metal layer 10a and contact hole 7a.

Next, a second interlayer insulating film 17 was formed on the entire surface of the substrate to a thickness of 600 nm by, for example, a CVD method. Next, contact holes 9b and 9c were formed in the second interlayer insulating film 17. The contact hole 9b is for connecting the drain electrode, and the contact hole 9c is for electrically connecting the light shielding film 15 and the additional capacitance common wiring 8.

Next, a pattern of the light-shielding film 15 was formed so as to fill the contact holes 9b and 9c in addition to the upper portion of the TFT 25. The light shielding film 15 is made of a metal such as a Ti-W alloy, and has a thickness of, for example, 120 to 150 nm.
And The light-shielding film 15 does not exist around the contact hole 9b, but since the metal layer 10b is formed in this portion, light does not leak from a portion where the light-shielding film 15 is not provided. The light-shielding film 15 can be made of a metal such as W, Ti, or Mo, in addition to the above-described Ti-W alloy. The light-shielding film 15 on the contact hole 9b is for obtaining an ohmic contact between the drain electrode 24 and a pixel electrode 4 described later.

After that, the third interlayer insulating film 18 is
m, the contact hole 16b is opened, and the pixel electrode 4 is formed.
Was formed.

Therefore, in the active matrix substrate of the present embodiment thus configured, the light shielding film 15
And the additional capacitance common wiring 8 are formed in parallel with each other, and the light shielding film 15 and the additional capacitance common wiring 8 are formed in the first and second interlayer insulating films 14 and 17 with contact holes 7c and 9 provided respectively.
Since they are electrically connected to each other via c, the circuit configuration is such that the light shielding film 15 and the additional capacitance common wiring 8 are connected in parallel, the resistance is reduced, and the occurrence of signal delay can be suppressed.

Further, since the additional capacitance common wiring 8 and the light shielding film 15 have a two-layer structure, it is possible to prevent disconnection that occurs when the line width of the additional capacitance common wiring 8 is reduced in order to increase the aperture ratio. it can.

[0038]

As described in detail above, the active matrix substrate of the present invention has a circuit configuration in which the light shielding film and the additional capacitance common wiring are connected in parallel, the resistance is reduced, and the occurrence of signal delay can be suppressed. . Further, since the additional capacitance common wiring and the light-shielding film have a two-layer structure, the line width of the additional capacitance common wiring can be reduced in a state where disconnection is prevented. A fine display device can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing one picture element in an active matrix substrate according to an embodiment.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a schematic plan view of an active matrix display device including the active matrix substrate of FIG.

FIG. 4 is a plan view of one picture element on a conventional active matrix substrate.

FIG. 5 is a sectional view taken along the line BB ′ of FIG. 4;

FIG. 6 is an equivalent circuit diagram of a picture element portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate bus wiring 2 Source bus wiring 3a, 3b Gate electrode 4 Pixel electrode 6 Additional capacitance electrode 7a, 7b, 7c Contact hole 8 Additional capacitance common electrode 9b, 9c Contact hole 10a, 10b, 10c Metal layer 11 Insulating substrate 12a , 12b Channel layer 13 Gate insulating film 14 First interlayer insulating film 15 Light shielding film 16b Contact hole 17 Second interlayer insulating film 18 Third interlayer insulating film 23 Source electrode 24 Drain electrode 25 TFT 30 Semiconductor layer

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/136 500

Claims (2)

(57) [Claims] 1. A thin film transistor, an additional capacitance electrode, and an
A first interlayer insulating film on the substrate on which the added capacitance common wiring is formed;
And a picture element formed on the light- shielding film via a second interlayer insulating film
And a contact formed on the first interlayer insulating film.
Electrically connected to the additional capacitance common wiring through a through hole.
And the picture element electrode is connected to the first interlayer insulating film and the second interlayer insulating film.
Through each contact hole formed in the interlayer insulating film of
An active matrix substrate electrically connected to the thin film transistor . 2. The light-shielding film is made of W, Ti, Mo, Ti-W.
2. The active matrix substrate according to claim 1, comprising an alloy.