JPH04335617A - Active matrix substrate - Google Patents
Active matrix substrateInfo
- Publication number
- JPH04335617A JPH04335617A JP3107647A JP10764791A JPH04335617A JP H04335617 A JPH04335617 A JP H04335617A JP 3107647 A JP3107647 A JP 3107647A JP 10764791 A JP10764791 A JP 10764791A JP H04335617 A JPH04335617 A JP H04335617A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- picture element
- insulating film
- element electrode
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 239000011159 matrix material Substances 0.000 title claims abstract description 34
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 abstract 2
- 239000010408 film Substances 0.000 description 40
- 239000010410 layer Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、液晶等の表示媒体と組
み合わせてマトリクス型の表示装置を構成するためのア
クティブマトリクス基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate for constructing a matrix type display device in combination with a display medium such as a liquid crystal.
【0002】0002
【従来の技術】アクティブマトリクス型表示装置は、高
いコントラストを有し、絵素数が制約されない等の利点
がある。そのため、アクティブマトリクス表示装置に用
いられるアクティブマトリクス基板に関する研究が盛ん
に行われている。しかし、アクティブマトリクス基板の
構造は複雑であり、光の利用効率(開口率)が低く、表
示画面が暗いという欠点がある。2. Description of the Related Art Active matrix display devices have advantages such as high contrast and no restrictions on the number of picture elements. Therefore, active matrix substrates used in active matrix display devices are being actively researched. However, active matrix substrates have a complicated structure, have low light utilization efficiency (aperture ratio), and have the drawbacks of dark display screens.
【0003】0003
【発明が解決しようとする課題】このような欠点を解決
したアクティブマトリクス基板の部分平面図を図6に、
図6のB−B線に沿った断面図を図7に示す。このアク
ティブマトリクス基板は、ガラス等の絶縁性基板1と、
基板1上に形成された薄膜トランジスタ(以下「TFT
」という)13とを有している。図6に示すように、T
FT13のゲート電極2はゲートバス配線3に接続され
、TFT13のソース電極6はソースバス配線7に接続
されている。絵素電極11はTFT13のドレイン電極
8に接続され、ゲートバス配線3及びソースバス配線7
上にも重畳されている。また、絵素電極11には後述の
ゲート電極4及び層間絶縁膜14を挟んで付加容量電極
17が対向している。絵素電極11と付加容量電極17
との間に付加容量19が形成されている。付加容量電極
17は付加容量配線18に接続されている。[Problems to be Solved by the Invention] FIG. 6 shows a partial plan view of an active matrix substrate that solves these drawbacks.
FIG. 7 shows a cross-sectional view taken along line BB in FIG. 6. This active matrix substrate includes an insulating substrate 1 made of glass or the like,
A thin film transistor (hereinafter referred to as "TFT") formed on the substrate 1
) 13. As shown in Figure 6, T
The gate electrode 2 of the FT 13 is connected to the gate bus wiring 3, and the source electrode 6 of the TFT 13 is connected to the source bus wiring 7. The picture element electrode 11 is connected to the drain electrode 8 of the TFT 13, and is connected to the gate bus wiring 3 and the source bus wiring 7.
It is also superimposed on top. Further, an additional capacitor electrode 17 faces the picture element electrode 11 with a gate electrode 4 and an interlayer insulating film 14, which will be described later, in between. Picture element electrode 11 and additional capacitance electrode 17
An additional capacitor 19 is formed between the two. Additional capacitance electrode 17 is connected to additional capacitance wiring 18 .
【0004】このように、絵素電極11がゲートバス配
線3及びソースバス配線7に重畳して形成されているア
クティブマトリクス基板の構成は、特に反射型表示装置
の開口率を増大させるのに有効である。As described above, the structure of the active matrix substrate in which the picture element electrode 11 is formed so as to overlap the gate bus wiring 3 and the source bus wiring 7 is particularly effective for increasing the aperture ratio of a reflective display device. It is.
【0005】図6及び図7に示すアクティブマトリクス
基板の製造方法を図8及び図9に示す。まず、ガラス等
の絶縁性基板1上に、Ta、Cr等からなるゲートバス
配線3及びゲート電極2を形成する。次に、ITO(I
ndium Tin Oxide)等の透明導電膜から
なる付加容量電極17及び付加容量配線18を形成する
。次に、SiNx、SiOx等からなるゲート絶縁膜4
、P(リン)をドープしたn+型のアモルファスシリコ
ン(以下では「a−Si」という)層からなるコンタク
ト層9、9、及びa−Si層からなる半導体層5を形成
する。次に、Mo、Ti、Al等からなるソース電極6
、ドレイン電極8、及びソースバス配線7を形成する(
図8)。以上により、TFT13が完成する。A method of manufacturing the active matrix substrate shown in FIGS. 6 and 7 is shown in FIGS. 8 and 9. First, a gate bus wiring 3 and a gate electrode 2 made of Ta, Cr, etc. are formed on an insulating substrate 1 made of glass or the like. Next, ITO (I
An additional capacitor electrode 17 and an additional capacitor wiring 18 made of a transparent conductive film such as ndium tin oxide are formed. Next, a gate insulating film 4 made of SiNx, SiOx, etc.
, contact layers 9 made of an n+ type amorphous silicon (hereinafter referred to as "a-Si") layer doped with P (phosphorus), and a semiconductor layer 5 made of an a-Si layer. Next, a source electrode 6 made of Mo, Ti, Al, etc.
, drain electrode 8, and source bus wiring 7 are formed (
Figure 8). Through the above steps, the TFT 13 is completed.
【0006】次に、ポリイミド、アクリル樹脂等からな
る層間絶縁膜10を基板1上の全面に形成し、ドレイン
電極8に対応する層間絶縁膜10の部分にコンタクトホ
ール12を形成する(図9)。更に、ITO膜を基板1
上の全面に形成しパターニングを行って、絵素電極11
を得る(図7)。これにより、絵素電極11はコンタク
トホール12を介してTFT13のドレイン電極8に電
気的に接続される。また、前述のように、絵素電極11
と付加容量電極17との間に付加容量19が形成される
。Next, an interlayer insulating film 10 made of polyimide, acrylic resin, etc. is formed on the entire surface of the substrate 1, and a contact hole 12 is formed in a portion of the interlayer insulating film 10 corresponding to the drain electrode 8 (FIG. 9). . Furthermore, the ITO film is attached to the substrate 1.
The picture element electrode 11 is formed and patterned on the entire upper surface.
(Figure 7). Thereby, the picture element electrode 11 is electrically connected to the drain electrode 8 of the TFT 13 via the contact hole 12. Furthermore, as described above, the picture element electrode 11
An additional capacitor 19 is formed between the additional capacitor electrode 17 and the additional capacitor electrode 17 .
【0007】このようなアクティブマトリクス基板では
、各絵素電極11に接続されたゲート電極2にゲートオ
ンの信号を印加し、ソース電極6からドレイン電極8を
介して絵素電極11に画像信号が書き込まれる。次に、
ゲートオフの信号がゲート電極2に出力され、次にゲー
トオンの信号が印加されるまでの1フレームの間、書き
込まれた画像信号が保持される。絵素電極11と付加容
量電極17との間に形成される付加容量19は、この画
像信号を保持する機能を果たしている。In such an active matrix substrate, a gate-on signal is applied to the gate electrode 2 connected to each picture element electrode 11, and an image signal is written from the source electrode 6 to the picture element electrode 11 via the drain electrode 8. It will be done. next,
The written image signal is held for one frame from when the gate-off signal is output to the gate electrode 2 until the next gate-on signal is applied. The additional capacitor 19 formed between the picture element electrode 11 and the additional capacitor electrode 17 functions to hold this image signal.
【0008】ところが、付加容量19を構成している絵
素電極11と付加容量電極17との間には、ゲート絶縁
膜4と層間絶縁膜10が存在するため、付加容量19は
ゲート絶縁膜4による容量と層間絶縁膜10による容量
とが直列に配列された構成を有することとなり、付加容
量19の容量値は小さくなってしまう。そのため、この
アクティブマトリクス基板を用いた表示装置では、コン
トラストの低下などの画像品位の低下が生ずることにな
る。However, since the gate insulating film 4 and the interlayer insulating film 10 are present between the picture element electrode 11 and the additional capacitor electrode 17 that constitute the additional capacitor 19, the additional capacitor 19 is The capacitance due to the capacitance due to the capacitance due to the interlayer insulating film 10 and the capacitance due to the interlayer insulating film 10 are arranged in series, and the capacitance value of the additional capacitance 19 becomes small. Therefore, in a display device using this active matrix substrate, a reduction in image quality such as a reduction in contrast occurs.
【0009】本発明はこのような問題点を解決するもの
であり、本発明の目的は、大きな容量値を有する付加容
量を備え、しかも開口率の大きなアクティブマトリクス
基板を提供することである。The present invention is intended to solve these problems, and an object of the present invention is to provide an active matrix substrate that is provided with an additional capacitance having a large capacitance value and has a large aperture ratio.
【0010】0010
【課題を解決するための手段】本発明のアクティブマト
リクス基板は、絶縁性基板上に形成された付加容量電極
と、該付加容量電極上に形成された絶縁膜と、該付加容
量電極に該絶縁膜を挟んで対向する第1絵素電極と、該
第1絵素電極に接続された出力端子を有するスイッチン
グ素子と、該スイッチング素子及び該第1絵素電極上に
形成された層間絶縁膜と、該層間絶縁膜に形成されたコ
ンタクトホールと、該コンタクトホールを介して該スイ
ッチング素子の該出力端子に電気的に接続された第2絵
素電極と、を有しており、そのことによって上記目的が
達成される。[Means for Solving the Problems] The active matrix substrate of the present invention includes an additional capacitor electrode formed on an insulating substrate, an insulating film formed on the additional capacitor electrode, and an insulating film formed on the additional capacitor electrode. a switching element having a first picture element electrode facing each other across a film, an output terminal connected to the first picture element electrode, and an interlayer insulating film formed on the switching element and the first picture element electrode; , has a contact hole formed in the interlayer insulating film, and a second picture element electrode electrically connected to the output terminal of the switching element via the contact hole, thereby achieving the above-mentioned effect. The purpose is achieved.
【0011】また、前記スイッチング素子に接続された
走査線を更に有し、前記第2絵素電極が該走査線に重畳
されている構成とすることができる。[0011] Furthermore, the display device may further include a scanning line connected to the switching element, and the second picture element electrode may be superimposed on the scanning line.
【0012】また、前記スイッチング素子に接続された
信号線を更に有し、前記第2絵素電極が該信号線に重畳
されている構成とすることができる。[0012] Furthermore, the display device may further include a signal line connected to the switching element, and the second picture element electrode may be superimposed on the signal line.
【0013】[0013]
【作用】本発明のアクティブマトリクス基板では、基板
上の付加容量電極と、付加容量電極上に絶縁膜を挟んで
対向する第1絵素電極との間に付加容量が形成されるの
で、付加容量の容量値を大きくすることができる。また
、第1絵素電極にはスイッチング素子の出力端子が接続
され、第1絵素電極及びスイッチング素子上に形成され
た層間絶縁膜にはコンタクトホールが形成されている。
層間絶縁膜上には第2絵素電極が形成され、第2絵素電
極はコンタクトホールを介してスイッチング素子の出力
端子に接続されている。従って、第2絵素電極はスイッ
チング素子に接続されている走査線及び/又は信号線に
層間絶縁膜を挟んで重畳形成され得るので、基板の開口
率を向上させることが可能となる。[Function] In the active matrix substrate of the present invention, additional capacitance is formed between the additional capacitance electrode on the substrate and the first picture element electrode that faces the additional capacitance electrode with an insulating film interposed therebetween. The capacitance value of can be increased. Further, the output terminal of the switching element is connected to the first picture element electrode, and a contact hole is formed in the interlayer insulating film formed on the first picture element electrode and the switching element. A second picture element electrode is formed on the interlayer insulating film, and the second picture element electrode is connected to the output terminal of the switching element via a contact hole. Therefore, since the second picture element electrode can be formed to overlap the scanning line and/or signal line connected to the switching element with the interlayer insulating film in between, it is possible to improve the aperture ratio of the substrate.
【0014】[0014]
【実施例】本発明の実施例について以下に説明する。本
実施例のアクティブマトリクス基板の一実施例の平面図
を図2に、図2のA−A線に沿った断面図を図1に示す
。本実施例のアクティブマトリクス基板は、ガラス等の
絶縁性基板1と、基板1上に形成されたTFT13とを
有している。図2に示すように、TFT13のゲート電
極2はゲートバス配線3に接続され、TFT13のソー
ス電極6はソースバス配線7に接続されている。絵素電
極11は下層の第1絵素電極11aと、該第1絵素電極
11a上に後述のゲート絶縁膜を挟んで重畳された第2
絵素電極11bからなる。第1絵素電極11a及び第2
絵素電極11bは共にTFT13のドレイン電極8に接
続され、第2絵素電極11bはゲートバス配線3及びソ
ースバス配線7上にも重畳されている。また、第1絵素
電極11aにはゲート電極4を挟んで付加容量電極17
が対向している。第1絵素電極11aと付加容量電極1
7との間に付加容量19が形成されている。付加容量電
極17は付加容量配線18に接続されている。[Examples] Examples of the present invention will be described below. FIG. 2 shows a plan view of an example of the active matrix substrate of this example, and FIG. 1 shows a cross-sectional view taken along line A--A in FIG. The active matrix substrate of this embodiment includes an insulating substrate 1 made of glass or the like, and a TFT 13 formed on the substrate 1. As shown in FIG. 2, the gate electrode 2 of the TFT 13 is connected to the gate bus wiring 3, and the source electrode 6 of the TFT 13 is connected to the source bus wiring 7. The picture element electrode 11 includes a first picture element electrode 11a in the lower layer, and a second picture element electrode 11a superimposed on the first picture element electrode 11a with a gate insulating film, which will be described later, in between.
It consists of a picture element electrode 11b. The first picture element electrode 11a and the second
The picture element electrodes 11b are both connected to the drain electrode 8 of the TFT 13, and the second picture element electrode 11b is also overlapped on the gate bus wiring 3 and the source bus wiring 7. Further, an additional capacitance electrode 17 is provided on the first picture element electrode 11a with the gate electrode 4 in between.
are facing each other. First picture element electrode 11a and additional capacitance electrode 1
An additional capacitor 19 is formed between the capacitor 7 and the capacitor 7. Additional capacitance electrode 17 is connected to additional capacitance wiring 18 .
【0015】図1及び図2に示すアクティブマトリクス
基板の製造方法を、図3〜図5に示す。本実施例のアク
ティブマトリクス基板を製造工程に従って説明する。ま
ず、ガラスからなる絶縁性基板1上に、スパッタリング
法により300nmの厚さのTa金属膜を形成し、この
金属膜をフォトリソグラフィ法及びエッチングによりパ
ターニングして、ゲートバス配線3及びゲート電極2を
形成する。次に、スパッタリング法により80nmの厚
さのITO膜を形成し、ホトリソグラフィ法及びエッチ
ングによりパターニングを行って、付加容量電極17及
び付加容量配線18を形成する。次に、プラズマCVD
法により、400nmの厚さのSiNxからなるゲート
絶縁膜4と、後に半導体層5となる厚さ100nmのa
−Si層と、後にコンタクト層9、9となるn+型a−
Si層とをこの順で連続的に形成する。次に、n+型a
−Si層とa−Si層のパターニングを行って、コンタ
クト層9、9及び半導体層5を形成する。A method of manufacturing the active matrix substrate shown in FIGS. 1 and 2 is shown in FIGS. 3 to 5. The active matrix substrate of this example will be explained according to the manufacturing process. First, a Ta metal film with a thickness of 300 nm is formed on an insulating substrate 1 made of glass by sputtering, and this metal film is patterned by photolithography and etching to form gate bus wiring 3 and gate electrode 2. Form. Next, an ITO film with a thickness of 80 nm is formed by sputtering, and patterned by photolithography and etching to form additional capacitor electrode 17 and additional capacitor wiring 18. Next, plasma CVD
A gate insulating film 4 made of SiNx with a thickness of 400 nm and a 100 nm thick a
-Si layer and n+ type a- which will later become contact layers 9, 9
and the Si layer are successively formed in this order. Next, n+ type a
-Si layer and a-Si layer are patterned to form contact layers 9, 9 and semiconductor layer 5.
【0016】次に、この基板上の全面に、厚さ200n
mのMo金属層をスパッタリング法によって形成し、こ
のMo金属層のパターニングを行って、ソース電極6、
ドレイン電極8、及びソースバス配線7を形成する。以
上により、TFT13が完成する。更に、TFT13を
覆って基板1上の全面に、100nmの厚さのITO膜
を形成し、パターニングを行って第1絵素電極11aを
形成する。本実施例では第1絵素電極11aと付加容量
電極17との間に付加容量19が形成される(図3)。Next, a film with a thickness of 200 nm is applied to the entire surface of this substrate.
A Mo metal layer of m is formed by a sputtering method, and this Mo metal layer is patterned to form the source electrode 6,
A drain electrode 8 and source bus wiring 7 are formed. Through the above steps, the TFT 13 is completed. Furthermore, an ITO film with a thickness of 100 nm is formed on the entire surface of the substrate 1, covering the TFT 13, and patterned to form the first picture element electrode 11a. In this embodiment, an additional capacitor 19 is formed between the first picture element electrode 11a and the additional capacitor electrode 17 (FIG. 3).
【0017】次に、TFT13及び第1絵素電極11a
を形成した基板1上の全面にポリイミド樹脂膜又はアク
リル樹脂膜からなる層間絶縁膜10を1μmの厚さに塗
布する(図4)。次に、層間絶縁膜10のドレイン電極
8に対応する部分にコンタクトホール12を形成する(
図5)。更に、層間絶縁膜10及びコンタクトホール1
2上にITO膜を形成し、パターニングを行って第2絵
素電極11bを形成する(図1)。これにより、第2絵
素電極11bは層間絶縁膜10に形成されたコンタクト
ホール12を介してTFT13のドレイン電極8に接続
される。また、図2に示すように、第2絵素電極11b
はゲートバス配線3及びソースバス配線7に、層間絶縁
膜10を挟んで重畳形成される。Next, the TFT 13 and the first picture element electrode 11a
An interlayer insulating film 10 made of a polyimide resin film or an acrylic resin film is applied to a thickness of 1 μm over the entire surface of the substrate 1 on which the film is formed (FIG. 4). Next, a contact hole 12 is formed in a portion of the interlayer insulating film 10 corresponding to the drain electrode 8 (
Figure 5). Furthermore, an interlayer insulating film 10 and a contact hole 1
An ITO film is formed on 2 and patterned to form a second picture element electrode 11b (FIG. 1). Thereby, the second picture element electrode 11b is connected to the drain electrode 8 of the TFT 13 via the contact hole 12 formed in the interlayer insulating film 10. Further, as shown in FIG. 2, the second picture element electrode 11b
is formed overlapping the gate bus wiring 3 and the source bus wiring 7 with an interlayer insulating film 10 in between.
【0018】本実施例では、付加容量19を構成する付
加容量電極17と第1絵素電極11aとの間には、比較
的薄いゲート絶縁膜4のみが存在するので、付加容量1
9の容量値を大きくすることができる。また、第2絵素
電極11bはゲートバス配線3及びソースバス配線7に
重畳して形成されているので、この基板の開口率を大き
くすることができる。In this embodiment, since only the relatively thin gate insulating film 4 is present between the additional capacitor electrode 17 and the first picture element electrode 11a constituting the additional capacitor 19, the additional capacitor 1
9 can be increased. Further, since the second picture element electrode 11b is formed to overlap the gate bus line 3 and the source bus line 7, the aperture ratio of this substrate can be increased.
【0019】本実施例ではスイッチング素子としてTF
Tを用いた場合について説明したが、他の例えば、MI
M(Metal−Insulator−Metal)素
子、ダイオード、バリスタ等を用いたアクティブマトリ
クス基板にも適用することができる。In this embodiment, a TF is used as a switching element.
Although we have explained the case where T is used, other cases such as MI
It can also be applied to an active matrix substrate using M (Metal-Insulator-Metal) elements, diodes, varistors, and the like.
【0020】[0020]
【発明の効果】本発明のアクティブマトリクス基板では
、付加容量は絶縁膜を挟んで対向する付加容量電極と第
1絵素電極との間に形成されているので、付加容量の容
量値を大きくすることができる。従って、本発明のアク
ティブマトリクス基板を用いて表示装置を構成すれば、
高いコントラストの表示画面が得られる。また、絵素電
極は層間絶縁膜上に形成された第2絵素電極を有してい
るので、絵素電極の面積を大きくすることができ、表示
装置の開口率を高めることができる。従って、本発明の
アクティブマトリクス基板を用いた表示装置では、明る
い表示画面が得られる。[Effects of the Invention] In the active matrix substrate of the present invention, since the additional capacitor is formed between the additional capacitor electrode and the first picture element electrode which face each other with an insulating film in between, the capacitance value of the additional capacitor can be increased. be able to. Therefore, if a display device is constructed using the active matrix substrate of the present invention,
A high contrast display screen can be obtained. Further, since the picture element electrode has the second picture element electrode formed on the interlayer insulating film, the area of the picture element electrode can be increased, and the aperture ratio of the display device can be increased. Therefore, in a display device using the active matrix substrate of the present invention, a bright display screen can be obtained.
【図1】本発明のアクティブマトリクス基板の一実施例
の断面図である。FIG. 1 is a cross-sectional view of an embodiment of an active matrix substrate of the present invention.
【図2】図1の基板の平面図である。FIG. 2 is a plan view of the substrate of FIG. 1;
【図3】図1及び図2のアクティブマトリクス基板の製
造工程を示す断面図である。3 is a cross-sectional view showing the manufacturing process of the active matrix substrate of FIGS. 1 and 2. FIG.
【図4】図1及び図2のアクティブマトリクス基板の製
造工程を示す断面図である。4 is a cross-sectional view showing the manufacturing process of the active matrix substrate of FIGS. 1 and 2. FIG.
【図5】図1及び図2のアクティブマトリクス基板の製
造工程を示す断面図である。5 is a cross-sectional view showing the manufacturing process of the active matrix substrate of FIGS. 1 and 2. FIG.
【図6】従来のアクティブマトリクス基板の平面図であ
る。FIG. 6 is a plan view of a conventional active matrix substrate.
【図7】図6のB−B線に沿った断面図である。7 is a sectional view taken along line BB in FIG. 6. FIG.
【図8】図6及び図7に示すアクティブマトリクス基板
の製造工程を示す図である。8 is a diagram showing a manufacturing process of the active matrix substrate shown in FIGS. 6 and 7. FIG.
【図9】図6及び図7に示すアクティブマトリクス基板
の製造工程を示す図である。9 is a diagram showing a manufacturing process of the active matrix substrate shown in FIGS. 6 and 7. FIG.
1 絶縁性基板 2 ゲート電極 3 ゲートバス配線 4 ゲート絶縁膜 5 半導体層 6 ソース電極 7 ソースバス配線 8 ドレイン電極 9 コンタクト層 10 層間絶縁膜 11 絵素電極 11a 第1絵素電極 11b 第2絵素電極 12 コンタクトホール 13 TFT 17 付加容量電極 18 付加容量配線 19 付加容量 1 Insulating substrate 2 Gate electrode 3 Gate bus wiring 4 Gate insulating film 5 Semiconductor layer 6 Source electrode 7 Source bus wiring 8 Drain electrode 9 Contact layer 10 Interlayer insulation film 11 Picture element electrode 11a First picture element electrode 11b Second picture element electrode 12 Contact hole 13 TFT 17 Additional capacitance electrode 18 Additional capacitance wiring 19 Additional capacity
Claims (3)
、該付加容量電極上に形成された絶縁膜と、該付加容量
電極に該絶縁膜を挟んで対向する第1絵素電極と、該第
1絵素電極に接続された出力端子を有するスイッチング
素子と、該スイッチング素子及び該第1絵素電極上に形
成された層間絶縁膜と、該層間絶縁膜に形成されたコン
タクトホールと、該コンタクトホールを介して該スイッ
チング素子の該出力端子に電気的に接続された第2絵素
電極と、を有するアクティブマトリクス基板。1. An additional capacitor electrode formed on an insulating substrate, an insulating film formed on the additional capacitor electrode, and a first picture element electrode facing the additional capacitor electrode with the insulating film interposed therebetween. , a switching element having an output terminal connected to the first picture element electrode, an interlayer insulating film formed on the switching element and the first picture element electrode, and a contact hole formed in the interlayer insulating film. , a second picture element electrode electrically connected to the output terminal of the switching element via the contact hole.
を更に有し、前記第2絵素電極が該走査線に重畳されて
いるアクティブマトリクス基板。2. An active matrix substrate further comprising a scanning line connected to the switching element, and the second picture element electrode is superimposed on the scanning line.
を更に有し、前記第2絵素電極が該信号線に重畳されて
いるアクティブマトリクス基板。3. An active matrix substrate further comprising a signal line connected to the switching element, and the second picture element electrode is superimposed on the signal line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10764791A JP2667304B2 (en) | 1991-05-13 | 1991-05-13 | Active matrix substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10764791A JP2667304B2 (en) | 1991-05-13 | 1991-05-13 | Active matrix substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04335617A true JPH04335617A (en) | 1992-11-24 |
JP2667304B2 JP2667304B2 (en) | 1997-10-27 |
Family
ID=14464494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10764791A Expired - Lifetime JP2667304B2 (en) | 1991-05-13 | 1991-05-13 | Active matrix substrate |
Country Status (1)
Country | Link |
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JP (1) | JP2667304B2 (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Production of active matrix substrate and its active matrix substrate |
JPH11243204A (en) * | 1998-02-25 | 1999-09-07 | Matsushita Electric Ind Co Ltd | Active matrix substrate and liquid crystal display device thereof |
KR100262227B1 (en) * | 1995-10-11 | 2000-07-15 | 니시무로 타이죠 | Lcd device |
JP2000227611A (en) * | 1999-02-05 | 2000-08-15 | Nec Corp | Liquid crystal display device and its production |
JP2001290172A (en) * | 1995-08-11 | 2001-10-19 | Sharp Corp | Liquid crystal display device |
JP2001296558A (en) * | 1995-08-11 | 2001-10-26 | Sharp Corp | Liquid crystal display device |
US6310669B1 (en) | 1997-05-26 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | TFT substrate having connecting line connect to bus lines through different contact holes |
JP2002189429A (en) * | 2000-09-06 | 2002-07-05 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
JP2002189232A (en) * | 1995-08-11 | 2002-07-05 | Sharp Corp | Liquid crystal display device, and active matrix substrate |
US7135705B2 (en) | 1995-06-06 | 2006-11-14 | Lg.Philips Lcd Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
JP2009003481A (en) * | 2002-07-08 | 2009-01-08 | Sharp Corp | Liquid crystal display |
USRE41363E1 (en) | 1995-11-21 | 2010-06-01 | Samsung Electronics Co., Ltd. | Thin film transistor substrate |
US7745825B2 (en) | 2007-04-03 | 2010-06-29 | Au Optronics Corp. | Pixel structure and method for forming the same |
US7977680B2 (en) | 2000-09-06 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistors on a metal substrate |
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JPS55518A (en) * | 1978-06-14 | 1980-01-05 | Suwa Seikosha Kk | Liquid crystal display unit |
JPS6370832A (en) * | 1986-09-12 | 1988-03-31 | Seiko Epson Corp | Active matrix panel |
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1991
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JPS55518A (en) * | 1978-06-14 | 1980-01-05 | Suwa Seikosha Kk | Liquid crystal display unit |
JPS6370832A (en) * | 1986-09-12 | 1988-03-31 | Seiko Epson Corp | Active matrix panel |
Cited By (21)
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US7135705B2 (en) | 1995-06-06 | 2006-11-14 | Lg.Philips Lcd Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
US8253890B2 (en) | 1995-06-06 | 2012-08-28 | Lg Display Co., Ltd. | High aperture LCD with insulating color filters overlapping bus lines on active substrate |
JP2001290172A (en) * | 1995-08-11 | 2001-10-19 | Sharp Corp | Liquid crystal display device |
JP2001296558A (en) * | 1995-08-11 | 2001-10-26 | Sharp Corp | Liquid crystal display device |
JP2002189232A (en) * | 1995-08-11 | 2002-07-05 | Sharp Corp | Liquid crystal display device, and active matrix substrate |
KR100262227B1 (en) * | 1995-10-11 | 2000-07-15 | 니시무로 타이죠 | Lcd device |
USRE41363E1 (en) | 1995-11-21 | 2010-06-01 | Samsung Electronics Co., Ltd. | Thin film transistor substrate |
JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Production of active matrix substrate and its active matrix substrate |
US6310669B1 (en) | 1997-05-26 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | TFT substrate having connecting line connect to bus lines through different contact holes |
US6650378B2 (en) | 1997-05-26 | 2003-11-18 | Mitsubishi Denki Kabushiki Kaisha | TFT array substrate and method of manufacturing the same and method of manufacturing liquid crystal display using the same |
JPH11243204A (en) * | 1998-02-25 | 1999-09-07 | Matsushita Electric Ind Co Ltd | Active matrix substrate and liquid crystal display device thereof |
US6894734B1 (en) | 1999-02-05 | 2005-05-17 | Nec Lcd Technologies, Ltd. | Liquid-crystal display device and method for production thereof |
JP2000227611A (en) * | 1999-02-05 | 2000-08-15 | Nec Corp | Liquid crystal display device and its production |
JP2002189429A (en) * | 2000-09-06 | 2002-07-05 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
US7977680B2 (en) | 2000-09-06 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistors on a metal substrate |
JP2012089839A (en) * | 2000-09-06 | 2012-05-10 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
JP2009003481A (en) * | 2002-07-08 | 2009-01-08 | Sharp Corp | Liquid crystal display |
US7745825B2 (en) | 2007-04-03 | 2010-06-29 | Au Optronics Corp. | Pixel structure and method for forming the same |
US8263445B2 (en) | 2007-04-03 | 2012-09-11 | Au Optronics Corp. | Pixel structure and method for forming the same |
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