JPH0244721U - - Google Patents

Info

Publication number
JPH0244721U
JPH0244721U JP12290588U JP12290588U JPH0244721U JP H0244721 U JPH0244721 U JP H0244721U JP 12290588 U JP12290588 U JP 12290588U JP 12290588 U JP12290588 U JP 12290588U JP H0244721 U JPH0244721 U JP H0244721U
Authority
JP
Japan
Prior art keywords
tft
tfts
electrode
gate
matrix array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12290588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12290588U priority Critical patent/JPH0244721U/ja
Publication of JPH0244721U publication Critical patent/JPH0244721U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Thin Film Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,b,cは本考案の異なる実施例を示
す平面図、第2図はTFTの断面図、を示す。第
3図は平面模式図である。 1…ゲート電極、2…ゲート絶縁膜、3…半導
体膜、4…ドレイン電極、5…ソース電極、6…
表示電極。
FIGS. 1a, b, and c are plan views showing different embodiments of the present invention, and FIG. 2 is a sectional view of the TFT. FIG. 3 is a schematic plan view. DESCRIPTION OF SYMBOLS 1... Gate electrode, 2... Gate insulating film, 3... Semiconductor film, 4... Drain electrode, 5... Source electrode, 6...
Display electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数本のゲートラインと複数本のドレインライ
ンが交差し、その交点にTFT(薄膜トランジス
タ)をマトリツクス状に形成したTFTマトリツ
クスアレイにおいて、前記TFTのゲート電極、
半導体膜、ゲート絶縁膜、ソース・ドレイン電極
、表示電極、パツシベーシヨン等の基本要素の形
状をTFTの一定配列周期毎に異ならしめたこと
を特徴とするTFTマトリクスアレイ。
In a TFT matrix array in which a plurality of gate lines and a plurality of drain lines intersect and TFTs (thin film transistors) are formed in a matrix at the intersections, the gate electrode of the TFT,
A TFT matrix array characterized in that the shapes of basic elements such as a semiconductor film, a gate insulating film, a source/drain electrode, a display electrode, and a passivation are made different for each fixed arrangement period of TFTs.
JP12290588U 1988-09-20 1988-09-20 Pending JPH0244721U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12290588U JPH0244721U (en) 1988-09-20 1988-09-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12290588U JPH0244721U (en) 1988-09-20 1988-09-20

Publications (1)

Publication Number Publication Date
JPH0244721U true JPH0244721U (en) 1990-03-28

Family

ID=31371275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12290588U Pending JPH0244721U (en) 1988-09-20 1988-09-20

Country Status (1)

Country Link
JP (1) JPH0244721U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104317A (en) * 1993-09-30 1995-04-21 Nec Corp Liquid crystal display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127178B2 (en) * 1982-10-06 1986-06-24 Toshuki Mano

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127178B2 (en) * 1982-10-06 1986-06-24 Toshuki Mano

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104317A (en) * 1993-09-30 1995-04-21 Nec Corp Liquid crystal display device

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