JPS6355557U - - Google Patents
Info
- Publication number
- JPS6355557U JPS6355557U JP14941186U JP14941186U JPS6355557U JP S6355557 U JPS6355557 U JP S6355557U JP 14941186 U JP14941186 U JP 14941186U JP 14941186 U JP14941186 U JP 14941186U JP S6355557 U JPS6355557 U JP S6355557U
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- line
- blocks
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図はこの考案の１実施例を示す薄膜トラン
ジスタアレイの平面図、第２図は従来の薄膜トラ
ンジスタアレイの等価回路図、第３図は従来の薄
膜トランジスタアレイの平面図である。
Ｂ（Ｂｍ，Ｂｍ＋１，Ｂｍ＋２…）……薄膜ト
ランジスタブロツク、Ｔｒ（Ｔｒｍ１…，Ｔｒ（
ｍ＋１）１…）……薄膜トランジスタ、Ｄ（Ｄｍ
１…，Ｄ（ｍ＋１）１…）……ドレインライン、
Ｓ（Ｓ１，Ｓ２…Ｓｎ）…ソースライン、Ｇ（Ｇ
ｍ，Ｇｍ＋１…）……ゲートライン。
FIG. 1 is a plan view of a thin film transistor array showing one embodiment of this invention, FIG. 2 is an equivalent circuit diagram of a conventional thin film transistor array, and FIG. 3 is a plan view of a conventional thin film transistor array. B (B m , B m+1 , B m+2 ...)...Thin film transistor block, T r (T rm1 ..., T r (
m+1 ) 1 ...)...Thin film transistor, D(D m
1 ...,D( m+1 ) 1 ...)...drain line,
S (S 1 , S 2 ...S n )...source line, G (G
m , G m+1 ...)...Gate line.
Claims (1)
れの薄膜トランジスタに接続されたドレインライ
ンとソースラインとにより薄膜トランジスタブロ
ツクを構成し、この薄膜トランジスタブロツクを
複数ブロツク絶縁基板上に配列した薄膜トランジ
スタアレイにおいて、前記薄膜トランジスタブロ
ツク間の境界領域にあつて、隣接して配置された
２つの薄膜トランジスタと、該薄膜トランジスタ
にそれぞれ接続されたドレインライン及びソース
ラインを、すべて前記薄膜トランジスタブロツク
間の仮想境界線に対して線対称となるように配線
パターンを形成することにより、前記ドレインラ
インとソースラインとがいかなる場所においても
並走しないようにしたことを特徴とする薄膜トラ
ンジスタアレイ。 In a thin film transistor array in which a thin film transistor block is constituted by n (n≧1) thin film transistors and a drain line and a source line connected to each thin film transistor, and a plurality of these thin film transistor blocks are arranged on an insulating substrate, the thin film transistor block is In the boundary area between the thin film transistor blocks, two thin film transistors arranged adjacent to each other, and drain lines and source lines respectively connected to the thin film transistors, are line-symmetrically arranged with respect to the virtual boundary line between the thin film transistor blocks. A thin film transistor array characterized in that the drain line and the source line do not run parallel to each other anywhere by forming a wiring pattern on the thin film transistor array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14941186U JPH0525251Y2 (en) | 1986-09-29 | 1986-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14941186U JPH0525251Y2 (en) | 1986-09-29 | 1986-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6355557U true JPS6355557U (en) | 1988-04-14 |
| JPH0525251Y2 JPH0525251Y2 (en) | 1993-06-25 |
Family
ID=31064593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14941186U Expired - Lifetime JPH0525251Y2 (en) | 1986-09-29 | 1986-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0525251Y2 (en) |
-
1986
- 1986-09-29 JP JP14941186U patent/JPH0525251Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0525251Y2 (en) | 1993-06-25 |
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