JPH0385659U - - Google Patents
Info
- Publication number
- JPH0385659U JPH0385659U JP14645889U JP14645889U JPH0385659U JP H0385659 U JPH0385659 U JP H0385659U JP 14645889 U JP14645889 U JP 14645889U JP 14645889 U JP14645889 U JP 14645889U JP H0385659 U JPH0385659 U JP H0385659U
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film circuit
- conductive substrate
- insulating film
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Description
第１図ａ及びｂは本考案の薄膜回路装置の一実
施例を示す平面図及びそのＡ−Ａ断面図、第２図
は薄膜トランジスタにより構成された複数のイン
バータを並列に多段接続した回路を示す回路図、
第３図ａ及びｂは従来の２層配線構造からなる薄
膜回路装置の一例を示す平面図及びそのＢ−Ｂ断
面図、第４図ａ及びｂは従来の３層配線構造から
なる薄膜回路装置の一例を示す平面図及びそのＣ
−Ｃ断面図である。
２……ゲート配線、４……ゲート絶縁膜、５…
…ａ−Ｓｉ半導体層、６……ソース及びドレイン
配線、７……電源ライン、８……スルーホール、
１１……導電性基板（接地ライン）、１２……絶
縁膜、１３……スルーホール、１４……埋込金属
。
Figures 1a and b are a plan view and a sectional view taken along the line A-A of the thin film circuit device according to the present invention, and Figure 2 shows a circuit in which a plurality of inverters each composed of thin film transistors are connected in parallel in multiple stages. circuit diagram,
FIGS. 3a and 3b are a plan view and a BB sectional view thereof showing an example of a thin film circuit device having a conventional two-layer wiring structure, and FIGS. 4a and b are thin film circuit devices having a conventional three-layer wiring structure. A plan view showing an example of and its C
-C sectional view. 2...gate wiring, 4...gate insulating film, 5...
... a-Si semiconductor layer, 6 ... source and drain wiring, 7 ... power supply line, 8 ... through hole,
11... Conductive substrate (ground line), 12... Insulating film, 13... Through hole, 14... Embedded metal.
Claims (1)
膜回路を形成すると共に、該薄膜回路の接地ライ
ン又は電源ラインとして前記導電性基板を用いた
ことを特徴とする薄膜回路装置。 A thin film circuit device, characterized in that a conductive substrate is covered with an insulating film, a thin film circuit is formed on the insulating film, and the conductive substrate is used as a ground line or a power supply line of the thin film circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14645889U JPH0385659U (en) | 1989-12-21 | 1989-12-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14645889U JPH0385659U (en) | 1989-12-21 | 1989-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0385659U true JPH0385659U (en) | 1991-08-29 |
Family
ID=31693038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14645889U Pending JPH0385659U (en) | 1989-12-21 | 1989-12-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0385659U (en) |
-
1989
- 1989-12-21 JP JP14645889U patent/JPH0385659U/ja active Pending
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