JPH0268453U - - Google Patents

Info

Publication number
JPH0268453U
JPH0268453U JP14766488U JP14766488U JPH0268453U JP H0268453 U JPH0268453 U JP H0268453U JP 14766488 U JP14766488 U JP 14766488U JP 14766488 U JP14766488 U JP 14766488U JP H0268453 U JPH0268453 U JP H0268453U
Authority
JP
Japan
Prior art keywords
drain
insulating film
source
read
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14766488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14766488U priority Critical patent/JPH0268453U/ja
Publication of JPH0268453U publication Critical patent/JPH0268453U/ja
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本考案の実施例を示す断面図、第２
図は、第１図に示された断面図に係わる平面図で
ある。 Fig. 1 is a sectional view showing an embodiment of the present invention;
The figure is a plan view related to the cross-sectional view shown in FIG. 1.

Claims (1)

【実用新案登録請求の範囲】 一導電型の半導体基板上にゲート絶縁膜を介し
て複数のシリコンゲートが形成され、該複数のシ
リコンゲート間の前記半導体基板内に逆導電型の
ソースあるいはドレインが形成されることによつ
て複数のＭＯＳＦＥＴが直列接続されてなるリー
ドオンリメモリにおいて、 前記ソースあるいはドレイン上に選択的に形成
されたコンタクト孔と、 前記シリコンゲート上に絶縁膜を介して形成さ
れ、前記ソースあるいはドレインを選択的に接続
する導電体と、 該導電体上に絶縁膜を介して形成されたデータ
ラインと、 を備えたリードオンリメモリ。[Claims for Utility Model Registration] A plurality of silicon gates are formed on a semiconductor substrate of one conductivity type via a gate insulating film, and a source or drain of an opposite conductivity type is formed in the semiconductor substrate between the plurality of silicon gates. In a read-only memory in which a plurality of MOSFETs are connected in series by forming a contact hole selectively formed on the source or drain, and a contact hole formed on the silicon gate via an insulating film, A read-only memory comprising: a conductor selectively connecting the source or drain; and a data line formed on the conductor via an insulating film.
JP14766488U 1988-11-11 1988-11-11 Pending JPH0268453U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14766488U JPH0268453U (en) 1988-11-11 1988-11-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14766488U JPH0268453U (en) 1988-11-11 1988-11-11

Publications (1)

Publication Number Publication Date
JPH0268453U true JPH0268453U (en) 1990-05-24

Family

ID=31418277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14766488U Pending JPH0268453U (en) 1988-11-11 1988-11-11

Country Status (1)

Country Link
JP (1) JPH0268453U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6240766A (en) * 1985-08-17 1987-02-21 Sanyo Electric Co Ltd Semiconductor read-only memory
JPS62120069A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Rom semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6240766A (en) * 1985-08-17 1987-02-21 Sanyo Electric Co Ltd Semiconductor read-only memory
JPS62120069A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Rom semiconductor device

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