JPH042025U - - Google Patents
Info
- Publication number
- JPH042025U JPH042025U JP4359490U JP4359490U JPH042025U JP H042025 U JPH042025 U JP H042025U JP 4359490 U JP4359490 U JP 4359490U JP 4359490 U JP4359490 U JP 4359490U JP H042025 U JPH042025 U JP H042025U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electrodes
- dielectric substrate
- dielectric
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
第１図はこの考案の一実施例である半導体装置
の上面図、第２図ａは従来およびこの考案共通の
ＦＥＴチツプの上面図、第２図ｂは従来の半導体
装置の断面図、第２図ｃは第２図ｂの半導体装置
の上面図である。
図において、１は半導体基板、２はソース電極
、３はゲート電極、４はドレイン電極、５は貫通
孔、６は厚めつき層、８はマイクロ波用ヘツダー
、９はソース電極端子、１０はＡｕワイヤ、１２
はメタライズパターン、１３はゲート電極端子、
１４はドレイン電極端子、１１１は誘電体基板を
示す。尚、図中、同一符号は同一、又は相当部分
を示す。
FIG. 1 is a top view of a semiconductor device which is an embodiment of this invention, FIG. 2a is a top view of an FET chip common to the conventional and this invention, FIG. Figure c is a top view of the semiconductor device of Figure 2b. In the figure, 1 is a semiconductor substrate, 2 is a source electrode, 3 is a gate electrode, 4 is a drain electrode, 5 is a through hole, 6 is a thick layer, 8 is a microwave header, 9 is a source electrode terminal, 10 is Au wire, 12
is a metallized pattern, 13 is a gate electrode terminal,
14 is a drain electrode terminal, and 111 is a dielectric substrate. In the drawings, the same reference numerals indicate the same or equivalent parts.
Claims (1)
チツプのインピーダンス整合を取るメタライズパ
ターンが形成された誘電体基板を有する半導体装
置において、前記誘電体基板の一部分に前記半導
体チツプを挿入する為の穴が設けられ、かつ複数
電極に対応する複数の誘電体基板が一体化された
ことを特徴とする半導体装置。 In a semiconductor device having a semiconductor chip having a plurality of electrodes and a dielectric substrate on which a metallized pattern for impedance matching of the semiconductor chip is formed, a hole for inserting the semiconductor chip is provided in a part of the dielectric substrate. , and a plurality of dielectric substrates corresponding to the plurality of electrodes are integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4359490U JPH042025U (en) | 1990-04-23 | 1990-04-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4359490U JPH042025U (en) | 1990-04-23 | 1990-04-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042025U true JPH042025U (en) | 1992-01-09 |
Family
ID=31556138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4359490U Pending JPH042025U (en) | 1990-04-23 | 1990-04-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042025U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4991171U (en) * | 1972-11-22 | 1974-08-07 | ||
| JP2015037132A (en) * | 2013-08-14 | 2015-02-23 | 住友電工デバイス・イノベーション株式会社 | Semiconductor device |
-
1990
- 1990-04-23 JP JP4359490U patent/JPH042025U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4991171U (en) * | 1972-11-22 | 1974-08-07 | ||
| JP2015037132A (en) * | 2013-08-14 | 2015-02-23 | 住友電工デバイス・イノベーション株式会社 | Semiconductor device |
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