JPS61183540U - - Google Patents
Info
- Publication number
- JPS61183540U JPS61183540U JP1985067584U JP6758485U JPS61183540U JP S61183540 U JPS61183540 U JP S61183540U JP 1985067584 U JP1985067584 U JP 1985067584U JP 6758485 U JP6758485 U JP 6758485U JP S61183540 U JPS61183540 U JP S61183540U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrode
- main surface
- integrated circuit
- facing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は、本考案の一実施例を示す斜視図、第
２図は、本考案の他の実施例を示す斜視図、第３
図は、本考案の更に他の実施例を示す断面図であ
る。
主要部分の符号の説明、１……半導体チツプ、
２，５……誘電体層、３，４，６……アルミ層。
FIG. 1 is a perspective view showing one embodiment of the present invention, FIG. 2 is a perspective view showing another embodiment of the present invention, and FIG.
The figure is a sectional view showing still another embodiment of the present invention. Explanation of symbols of main parts, 1...Semiconductor chip,
2, 5... dielectric layer, 3, 4, 6... aluminum layer.
Claims (1)
プの主面に対向する面を有する少なくとも１つの
電極と、前記チツプの主面と前記電極の前記チツ
プの主面に対向する面間に形成された誘電体層と
を含み、前記電極の所定基準電位点に接続したこ
とを特徴とする集積回路装置。 a chip on which an integrated circuit is formed; at least one electrode having a surface facing the main surface of the chip; and a surface formed between the main surface of the chip and the surface of the electrode facing the main surface of the chip. An integrated circuit device comprising: a dielectric layer; and connected to a predetermined reference potential point of the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985067584U JPS61183540U (en) | 1985-05-08 | 1985-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985067584U JPS61183540U (en) | 1985-05-08 | 1985-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61183540U true JPS61183540U (en) | 1986-11-15 |
Family
ID=30601547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985067584U Pending JPS61183540U (en) | 1985-05-08 | 1985-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61183540U (en) |
-
1985
- 1985-05-08 JP JP1985067584U patent/JPS61183540U/ja active Pending