JPS63132453U - - Google Patents
Info
- Publication number
- JPS63132453U JPS63132453U JP2437887U JP2437887U JPS63132453U JP S63132453 U JPS63132453 U JP S63132453U JP 2437887 U JP2437887 U JP 2437887U JP 2437887 U JP2437887 U JP 2437887U JP S63132453 U JPS63132453 U JP S63132453U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- semiconductor substrate
- memory device
- counter electrode
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案の一実施例を示す半導体記憶装
置の断面図、第２図は第１図の等価回路図、第３
図は第２の実施例を示す断面図、第４図は第３の
実施例を示す断面図、第５図は第１の従来例（ト
レンチ・キヤパシタ型）の断面図、第６図は第２
の従来例（突起部型）の断面図である。
１…半導体基板、４…ゲート電極、５…ソース
・ドレイン領域、６…ノード領域、７…ＭＯＳ型
トランジスタ、１１…誘電体膜、１２…対向電極
、１３…キヤパシタ。
FIG. 1 is a sectional view of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG.
The figure is a sectional view showing the second embodiment, FIG. 4 is a sectional view showing the third embodiment, FIG. 5 is a sectional view of the first conventional example (trench capacitor type), and FIG. 6 is a sectional view showing the third embodiment. 2
FIG. 2 is a sectional view of a conventional example (protrusion type). DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 4... Gate electrode, 5... Source/drain region, 6... Node region, 7... MOS type transistor, 11... Dielectric film, 12... Counter electrode, 13... Capacitor.
Claims (1)
ト電極とを具備したＭＯＳ型トランジスタが半導
体基板の表面側に形成されると共に、誘電体膜を
介して上記半導体基板の裏面にキヤパシタの対向
電極が形成され、かつ上記ＭＯＳ型トランジスタ
と上記対向電極とが上記ノード領域を介して電気
的に接続されたことを特徴とする半導体記憶装置
。 (2) 上記半導体基板にエピタキシヤル層が形成
され、該エピタキシヤル層の表面に上記ＭＯＳ型
トランジスタが形成されたことを特徴とする実用
新案登録請求の範囲第(1)項記載の半導体記憶装
置。[Claims for Utility Model Registration] (1) A MOS transistor having a source/drain region, a node region, and a gate electrode is formed on the surface side of a semiconductor substrate, and is connected to the semiconductor substrate through a dielectric film. 1. A semiconductor memory device, wherein a counter electrode of a capacitor is formed on a back surface, and the MOS transistor and the counter electrode are electrically connected via the node region. (2) The semiconductor memory device according to claim (1), wherein an epitaxial layer is formed on the semiconductor substrate, and the MOS transistor is formed on the surface of the epitaxial layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2437887U JPS63132453U (en) | 1987-02-20 | 1987-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2437887U JPS63132453U (en) | 1987-02-20 | 1987-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63132453U true JPS63132453U (en) | 1988-08-30 |
Family
ID=30823555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2437887U Pending JPS63132453U (en) | 1987-02-20 | 1987-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63132453U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02199862A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02262359A (en) * | 1989-04-03 | 1990-10-25 | Takehide Shirato | Semiconductor device |
| JPH06151709A (en) * | 1992-11-16 | 1994-05-31 | Matsushita Electric Works Ltd | Capacitor |
| CN109106401A (en) * | 2017-06-23 | 2019-01-01 | Rends股份有限公司 | Ejaculation stimulating device |
-
1987
- 1987-02-20 JP JP2437887U patent/JPS63132453U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02199862A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02262359A (en) * | 1989-04-03 | 1990-10-25 | Takehide Shirato | Semiconductor device |
| JPH06151709A (en) * | 1992-11-16 | 1994-05-31 | Matsushita Electric Works Ltd | Capacitor |
| CN109106401A (en) * | 2017-06-23 | 2019-01-01 | Rends股份有限公司 | Ejaculation stimulating device |
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