JPS63174464U - - Google Patents

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Publication number
JPS63174464U
JPS63174464U JP16149686U JP16149686U JPS63174464U JP S63174464 U JPS63174464 U JP S63174464U JP 16149686 U JP16149686 U JP 16149686U JP 16149686 U JP16149686 U JP 16149686U JP S63174464 U JPS63174464 U JP S63174464U
Authority
JP
Japan
Prior art keywords
region
channel
thin film
film transistor
channel region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16149686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16149686U priority Critical patent/JPS63174464U/ja
Publication of JPS63174464U publication Critical patent/JPS63174464U/ja
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る薄膜トランジスタの一実
施例を示す断面図である。第2図A〜第2図Dは
上記実施例の薄膜トランジスタの製造方法を工程
順に示す各断面図であり、第2図Aはシリコン膜
形成工程を示す図、第2図Bはエツチング工程を
示す図、第2図Cは酸化およびポリシリコン膜形
成工程を示す図、第2図DはRIE工程を示す図
である。第3図は本考案に係る薄膜トランジスタ
の他の実施例を示す断面図である。 2S……ソース領域、2D……ドレイン領域、
2C……チヤンネル領域、3……二酸化シリコン
膜、4G……ゲート電極。
FIG. 1 is a sectional view showing an embodiment of a thin film transistor according to the present invention. FIGS. 2A to 2D are cross-sectional views showing the manufacturing method of the thin film transistor of the above embodiment in the order of steps. FIG. 2A is a diagram showing a silicon film forming process, and FIG. 2B is a diagram showing an etching process. FIG. 2C is a diagram showing the oxidation and polysilicon film forming process, and FIG. 2D is a diagram showing the RIE process. FIG. 3 is a sectional view showing another embodiment of the thin film transistor according to the present invention. 2S...source region, 2D...drain region,
2C...Channel region, 3...Silicon dioxide film, 4G...Gate electrode.

Claims (1)

【実用新案登録請求の範囲】 絶縁基体上に被着形成された半導体層にチヤン
ネル領域を介してソース領域、ドレイン領域がそ
れぞれ形成されてなる薄膜トランジスタにおいて
、 ソース領域およびドレイン領域がこれらの間の
チヤンネル領域よりも厚く形成され、 上記チヤンネル領域上にゲート絶縁膜を介して
ゲート電極が配されてなる薄膜トランジスタ。
[Claims for Utility Model Registration] In a thin film transistor in which a source region and a drain region are respectively formed in a semiconductor layer formed on an insulating substrate via a channel region, the source region and the drain region are connected to a channel between them. A thin film transistor formed to be thicker than the channel region, and having a gate electrode disposed on the channel region with a gate insulating film interposed therebetween.
JP16149686U 1986-10-23 1986-10-23 Pending JPS63174464U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16149686U JPS63174464U (en) 1986-10-23 1986-10-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16149686U JPS63174464U (en) 1986-10-23 1986-10-23

Publications (1)

Publication Number Publication Date
JPS63174464U true JPS63174464U (en) 1988-11-11

Family

ID=31087862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16149686U Pending JPS63174464U (en) 1986-10-23 1986-10-23

Country Status (1)

Country Link
JP (1) JPS63174464U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154383A (en) * 1989-11-11 1991-07-02 Takehide Shirato Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154383A (en) * 1989-11-11 1991-07-02 Takehide Shirato Semiconductor device

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