JPS6312861U

JPS6312861U -

Info

Publication number: JPS6312861U
Application number: JP10491286U
Authority: JP
Priority date: 1986-07-10
Filing date: 1986-07-10
Publication date: 1988-01-27

Description

[Brief explanation of the drawing]

第１図はこの考案に係る電界効果トランジスタ
の一実施例を示す縦断面図、第２図は同上一実施
例の平面図、第３図はこの考案の他の実施例を示
す平面図、第４図は従来の電界効果トランジスタ
の縦断面図、第５図は同上従来例の平面図である
。２：ｐ形ウエル領域（ｐ形の基板領域）、４，
４ａ〜４ｄ：ソース領域、５，５ａ〜５ｅ：ｐ形
の高不純物濃度領域、６：ソースコンタクトホー
ル、８：ドレイン領域、９：チヤネル領域、１１
：ゲート絶縁膜、１２：ゲート電極、１４：ソー
ス電極。 FIG. 1 is a longitudinal sectional view showing one embodiment of a field effect transistor according to the invention, FIG. 2 is a plan view of the same embodiment, and FIG. 3 is a plan view showing another embodiment of the invention. FIG. 4 is a longitudinal sectional view of a conventional field effect transistor, and FIG. 5 is a plan view of the same conventional example. 2: p-type well region (p-type substrate region), 4,
4a to 4d: source region, 5, 5a to 5e: p-type high impurity concentration region, 6: source contact hole, 8: drain region, 9: channel region, 11
: gate insulating film, 12: gate electrode, 14: source electrode.

Claims

[Claims for Utility Model Registration] N-type source and drain regions are formed separately on the surface of a p-type substrate region, and a gate electrode is formed on the substrate region between the source and drain regions via a gate insulating film. in a field effect transistor in which a source electrode is connected to the source region, a p-type high impurity concentration region in contact with a substrate region is formed at a position adjacent to the source region, and the p-type high impurity concentration region is connected to the source electrode.