JPH0158960U - - Google Patents
Info
- Publication number
- JPH0158960U JPH0158960U JP15492287U JP15492287U JPH0158960U JP H0158960 U JPH0158960 U JP H0158960U JP 15492287 U JP15492287 U JP 15492287U JP 15492287 U JP15492287 U JP 15492287U JP H0158960 U JPH0158960 U JP H0158960U
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- high resistivity
- type high
- opposite conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案に係るＮ形ＭＯＳＦＥＴの一実
施例を示す断面図である。第２図ａ〜ｄはそのＭ
ＯＳＦＥＴの製造工程を示す断面図である。第３
図は変形例を示す断面図である。第４図および第
５図はそれぞれ従来例を示す断面図である。
２０，３０：Ｎ形半導体基板、２１，３１：Ｐ
ウエル、２２，３２：Ｐ＋ポリシリコン層、３３
：Ｎ＋ドレイン領域、３４：Ｎ＋ソース領域、３
５：Ｐ＋コンタクト領域、３６：ゲート電極。
FIG. 1 is a sectional view showing an embodiment of an N-type MOSFET according to the present invention. Figure 2 a to d are M
FIG. 3 is a cross-sectional view showing the manufacturing process of the OSFET. Third
The figure is a sectional view showing a modified example. FIGS. 4 and 5 are sectional views showing conventional examples, respectively. 20, 30: N-type semiconductor substrate, 21, 31: P
Well, 22, 32: P + polysilicon layer, 33
:N + drain region, 34:N + source region, 3
5: P + contact region, 36: gate electrode.
補正 昭６３．３．２６
考案の名称を次のように補正する。
考案の名称 ＭＯＳ型電界効果トランジスタ
実用新案登録請求の範囲を次のように補正する
。Amendment: March 26, 1981 The name of the invention is amended as follows. Title of the invention: MOS field effect transistor The scope of the claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
一導電形半導体基板中に形成された反対導電形
高比抵抗領域と、該反対導電形高比抵抗領域内で
チヤネル領域を挾さんで設けられた一導電形ソー
ス領域およびドレイン領域と、チヤネル領域の表
面に絶縁膜を介して形成されたゲート電極とを有
するＭＯＳ型電界効果トランジスタにおいて、
前記反対導電形高比抵抗領域中の少なくともソ
ース領域の真下に前記チヤネル領域と平行に延在
する多結晶半導体領域を配設したことを特徴とす
るＭＯＳ型電界効果トランジスタ。 [Claim for Utility Model Registration] An opposite conductivity type high resistivity region formed in a one conductivity type semiconductor substrate, and a one conductivity type source provided with a channel region sandwiched between the opposite conductivity type high resistivity region. In a MOS type field effect transistor having a drain region and a gate electrode formed on a surface of the channel region with an insulating film interposed therebetween, the channel region is located directly below at least the source region in the opposite conductivity type high resistivity region. A MOS type field effect transistor characterized by having a polycrystalline semiconductor region extending in parallel with the MOS transistor.
Claims (1)
高比抵抗領域と、該反対導電形高比抵抗領域内で
チヤネル領域を挾さんで設けられた一導電形ソー
ス領域およびドレイン領域と、チヤネル領域の表
面に絶縁膜を介して形成されたゲート電極とを有
するＭＯＳＦＥＴにおいて、 前記反対導電形高比抵抗領域中の少なくともソ
ース領域の真下に前記チヤネル領域と平行に延在
する多結晶半導体領域を配設したことを特徴とす
るＭＯＳＦＥＴ。[Claim for Utility Model Registration] An opposite conductivity type high resistivity region formed in a one conductivity type semiconductor substrate, and a one conductivity type source provided with a channel region sandwiched between the opposite conductivity type high resistivity region. In a MOSFET having a drain region and a gate electrode formed on the surface of the channel region with an insulating film interposed therebetween, a gate electrode extending in parallel to the channel region at least immediately below the source region in the opposite conductivity type high resistivity region. A MOSFET characterized in that a polycrystalline semiconductor region is disposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15492287U JPH0158960U (en) | 1987-10-08 | 1987-10-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15492287U JPH0158960U (en) | 1987-10-08 | 1987-10-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0158960U true JPH0158960U (en) | 1989-04-13 |
Family
ID=31432089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15492287U Pending JPH0158960U (en) | 1987-10-08 | 1987-10-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0158960U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009238936A (en) * | 2008-03-26 | 2009-10-15 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
-
1987
- 1987-10-08 JP JP15492287U patent/JPH0158960U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009238936A (en) * | 2008-03-26 | 2009-10-15 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
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