JPH0197567U - - Google Patents
Info
- Publication number
- JPH0197567U JPH0197567U JP19431887U JP19431887U JPH0197567U JP H0197567 U JPH0197567 U JP H0197567U JP 19431887 U JP19431887 U JP 19431887U JP 19431887 U JP19431887 U JP 19431887U JP H0197567 U JPH0197567 U JP H0197567U
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- field effect
- semiconductor substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Description
第１図は本考案の一実施例を示すＭＯＳトラン
ジスタの断面図、第２図および第３図はそれぞれ
従来公知のＭＯＳトランジスタの平面図およびそ
のＡ―Ａ′断面図である。
１…Ｐ型半導体基板、２…素子間分離用選択酸
化膜、３…ゲート酸化膜、４…ｎ型不純物領域、
５…ゲート電極、６…欠陥密度の高い領域、７…
高耐圧用酸化膜。
FIG. 1 is a sectional view of a MOS transistor showing an embodiment of the present invention, and FIGS. 2 and 3 are a plan view and a sectional view taken along line AA' of a conventionally known MOS transistor, respectively. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Selective oxide film for element isolation, 3... Gate oxide film, 4... N-type impurity region,
5... Gate electrode, 6... Region with high defect density, 7...
Oxide film for high voltage resistance.
Claims (1)
成し、両領域間の半導体基板上にゲート絶縁膜を
介してゲート電極を形成するＭＩＳ電界効果型半
導体装置において、前記素子間分離用選択酸化膜
と接するゲート絶縁膜の両端部の膜厚が局部的に
それぞれ前記ゲート絶縁膜より厚膜に設定される
ことを特徴とするＭＩＳ電界効果型半導体装置。 In a MIS field effect semiconductor device in which a source region and a drain region are formed on a semiconductor substrate, and a gate electrode is formed on the semiconductor substrate between both regions via a gate insulating film, the method is in contact with the selective oxide film for element isolation. A MIS field effect semiconductor device characterized in that the thickness of both ends of a gate insulating film is locally set to be thicker than that of the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19431887U JPH0197567U (en) | 1987-12-21 | 1987-12-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19431887U JPH0197567U (en) | 1987-12-21 | 1987-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0197567U true JPH0197567U (en) | 1989-06-29 |
Family
ID=31485050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19431887U Pending JPH0197567U (en) | 1987-12-21 | 1987-12-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0197567U (en) |
-
1987
- 1987-12-21 JP JP19431887U patent/JPH0197567U/ja active Pending
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