JPH0227751U - - Google Patents
Info
- Publication number
- JPH0227751U JPH0227751U JP10633888U JP10633888U JPH0227751U JP H0227751 U JPH0227751 U JP H0227751U JP 10633888 U JP10633888 U JP 10633888U JP 10633888 U JP10633888 U JP 10633888U JP H0227751 U JPH0227751 U JP H0227751U
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- offset
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000005669 field effect Effects 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Description
第１図は本考案の一実施例の構造説明図、第２
図は本考案の一実施例の製造工程図、第３図は従
来例の説明図である。
１……Ｐ型ウエル領域、２，２′……ソース領
域、３，３′……ドレイン領域、４……ゲート酸
化膜、５……ゲート電極、６，６′……ロコス絶
縁膜、７，７′……オフセツト領域、８……ソー
ス電極、９……ドレイン電極、１０……層間絶縁
膜。
Fig. 1 is a structural explanatory diagram of one embodiment of the present invention;
The figure is a manufacturing process diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional example. 1... P-type well region, 2, 2'... Source region, 3, 3'... Drain region, 4... Gate oxide film, 5... Gate electrode, 6, 6'... Locos insulating film, 7 , 7'... Offset region, 8... Source electrode, 9... Drain electrode, 10... Interlayer insulating film.
Claims (1)
接合近傍にオフセツト領域を有し、このオフセツ
ト領域がチヤンネル領域により分離される構造の
プレーナ型高耐圧絶縁ゲート電界効果型トランジ
スタを有する半導体装置において、上記チヤンネ
ル領域とオフセツト領域との間に上記ソース・ド
レイン領域と同極性の同不純物濃度の領域を有す
ることを特徴とする絶縁ゲート電界効果型トラン
ジスタを具備する半導体装置。 In a semiconductor device having a planar high-voltage insulated gate field effect transistor having an offset region near a junction between a drain region and a source region on a surface of a semiconductor substrate, and having a structure in which this offset region is separated by a channel region, the channel region 1. A semiconductor device comprising an insulated gate field effect transistor, comprising a region having the same polarity and the same impurity concentration as the source/drain region between the source/drain region and the offset region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10633888U JPH0227751U (en) | 1988-08-11 | 1988-08-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10633888U JPH0227751U (en) | 1988-08-11 | 1988-08-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227751U true JPH0227751U (en) | 1990-02-22 |
Family
ID=31339754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10633888U Pending JPH0227751U (en) | 1988-08-11 | 1988-08-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227751U (en) |
-
1988
- 1988-08-11 JP JP10633888U patent/JPH0227751U/ja active Pending