JPS63132457U - - Google Patents
Info
- Publication number
- JPS63132457U JPS63132457U JP2462287U JP2462287U JPS63132457U JP S63132457 U JPS63132457 U JP S63132457U JP 2462287 U JP2462287 U JP 2462287U JP 2462287 U JP2462287 U JP 2462287U JP S63132457 U JPS63132457 U JP S63132457U
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- impurity diffusion
- polygon
- constitutes
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案実施例の平面構造を示す図、第
２図と第３図は第１図の断面構造を示す図、第４
図は本考案の他の実施例の平面構造を示す図、第
５図、第７図は従来例の平面構造を示す図、第６
図、第８図は従来例の断面構造を示す図である。
１，１１…ゲート電極、２，３，１２，１３…
不純物拡散層、４…ゲート酸化膜、５…厚い酸化
膜、６…基板。
FIG. 1 is a diagram showing the planar structure of the embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the cross-sectional structure of FIG.
The figure shows a planar structure of another embodiment of the present invention, FIGS. 5 and 7 show a planar structure of a conventional example, and FIG. 6 shows a planar structure of a conventional example.
8 are diagrams showing a cross-sectional structure of a conventional example. 1, 11...gate electrode, 2, 3, 12, 13...
Impurity diffusion layer, 4...gate oxide film, 5...thick oxide film, 6...substrate.
Claims (1)
板上に絶縁膜を介して形成され、上記多角形の電
極の内側及び外側に上記多角形の角の付近を除い
て不純物拡散層が形成され、上記電極がゲートを
構成し、上記多角形の内側の不純物拡散層がドレ
インを構成し、上記多角形の外側の不純物拡散層
がソースを構成してなるＭＯＳ型ＦＥＴ。 An electrode having a hollow polygonal planar shape is formed on a semiconductor substrate via an insulating film, an impurity diffusion layer is formed inside and outside the polygonal electrode except near the corners of the polygon, A MOS FET in which the electrode constitutes a gate, the impurity diffusion layer inside the polygon constitutes a drain, and the impurity diffusion layer outside the polygon constitutes a source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2462287U JPS63132457U (en) | 1987-02-20 | 1987-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2462287U JPS63132457U (en) | 1987-02-20 | 1987-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63132457U true JPS63132457U (en) | 1988-08-30 |
Family
ID=30824026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2462287U Pending JPS63132457U (en) | 1987-02-20 | 1987-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63132457U (en) |
-
1987
- 1987-02-20 JP JP2462287U patent/JPS63132457U/ja active Pending