JPS63177051U - - Google Patents
Info
- Publication number
- JPS63177051U JPS63177051U JP6676387U JP6676387U JPS63177051U JP S63177051 U JPS63177051 U JP S63177051U JP 6676387 U JP6676387 U JP 6676387U JP 6676387 U JP6676387 U JP 6676387U JP S63177051 U JPS63177051 U JP S63177051U
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- depositing
- semiconductor device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図および第２図はこの考案をＣＭＯＳイン
バータに適用した第１実施例を示し、第１図はそ
の要部拡大断面図、第２図はその製造工程を示す
図、第３図および第４図はこの考案の第２実施例
を示し、第３図はその拡大断面図、第４図はその
製造工程を示す図である。
１……シリコン基板、２，３０……ｐウエル、
３，３１……ｎウエル、５……絶縁膜、６，７…
…ゲート絶縁膜、８，９……ゲート電極、１０，
１１……ソース領域、１２，１３……ドレイン領
域、Ｓ……素子分離領域、Ｅ１，Ｅ２……素子領
域。
1 and 2 show a first embodiment in which this invention is applied to a CMOS inverter. FIG. 1 is an enlarged cross-sectional view of the main part, FIG. 2 is a diagram showing the manufacturing process, and FIGS. FIG. 4 shows a second embodiment of this invention, FIG. 3 is an enlarged sectional view thereof, and FIG. 4 is a diagram showing its manufacturing process. 1...Silicon substrate, 2,30...P well,
3, 31...n-well, 5...insulating film, 6,7...
...Gate insulating film, 8, 9...Gate electrode, 10,
11...Source region, 12, 13...Drain region, S...Element isolation region, E1 , E2 ...Element region.
Claims (1)
してなる素子分離領域を形成したことを特徴とす
る半導体装置。 A semiconductor device characterized in that an element isolation region formed by depositing an insulating film is formed around each element region of an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6676387U JPS63177051U (en) | 1987-05-06 | 1987-05-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6676387U JPS63177051U (en) | 1987-05-06 | 1987-05-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63177051U true JPS63177051U (en) | 1988-11-16 |
Family
ID=30905058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6676387U Pending JPS63177051U (en) | 1987-05-06 | 1987-05-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63177051U (en) |
-
1987
- 1987-05-06 JP JP6676387U patent/JPS63177051U/ja active Pending