JPS61112642U - - Google Patents
Info
- Publication number
- JPS61112642U JPS61112642U JP20013684U JP20013684U JPS61112642U JP S61112642 U JPS61112642 U JP S61112642U JP 20013684 U JP20013684 U JP 20013684U JP 20013684 U JP20013684 U JP 20013684U JP S61112642 U JPS61112642 U JP S61112642U
- Authority
- JP
- Japan
- Prior art keywords
- current circuit
- circuit
- wiring
- small current
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の一実施例による断面図である
。第２図は本考案の一実施例による平面図である
。第３図は従来の半導体集積回路の断面図である
。第４図は従来の半導体集積回路の平面図である
。
１……大電流回路、２……小電流回路、３……
大電流回路の最低電位配線、４……小電流回路の
最低電位配線、５，５′……接触、６……Ｐ型絶
縁分離領域。
FIG. 1 is a sectional view of an embodiment of the present invention. FIG. 2 is a plan view of an embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional semiconductor integrated circuit. FIG. 4 is a plan view of a conventional semiconductor integrated circuit. 1... Large current circuit, 2... Small current circuit, 3...
Lowest potential wiring of large current circuit, 4...lowest potential wiring of small current circuit, 5, 5'...contact, 6...P type insulation isolation region.
Claims (1)
路の最低電位が分離されている半導体集積回路に
おいて、大電流回路のトランジスタの周囲の絶縁
分離領域にコンタクトを置き、その回路の最低電
位の配線を接触さし、この最低電位の配線との接
触部を前記小電流回路との間に配置したことを特
徴とする半導体集積回路装置。 In a semiconductor integrated circuit in which a large current circuit and a small current circuit coexist and the lowest potentials of both circuits are separated, a contact is placed in the isolation region around the transistor of the large current circuit, and the lowest potential of the circuit is separated. A semiconductor integrated circuit device, characterized in that a wiring is brought into contact with the wiring, and a contact portion with the lowest potential wiring is arranged between the small current circuit and the small current circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20013684U JPS61112642U (en) | 1984-12-26 | 1984-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20013684U JPS61112642U (en) | 1984-12-26 | 1984-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61112642U true JPS61112642U (en) | 1986-07-16 |
Family
ID=30760701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20013684U Pending JPS61112642U (en) | 1984-12-26 | 1984-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112642U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139390A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1984
- 1984-12-26 JP JP20013684U patent/JPS61112642U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139390A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Semiconductor integrated circuit device |