JPS63167755U - - Google Patents
Info
- Publication number
- JPS63167755U JPS63167755U JP6025787U JP6025787U JPS63167755U JP S63167755 U JPS63167755 U JP S63167755U JP 6025787 U JP6025787 U JP 6025787U JP 6025787 U JP6025787 U JP 6025787U JP S63167755 U JPS63167755 U JP S63167755U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- device including
- offset region
- region
- high voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Description
第１図は本考案の半導体装置の構造説明図、第
２図は本考案の半導体装置の製造方法工程図、第
３図は本考案と従来例のオン抵抗の比較図、第４
図は従来のボス・オフセツト構造の半導体装置の
構造説明図である。
１，４１……半導体基板、２，４２……ソース
領域、３，４３……ドレイン領域、４，４４……
ゲート酸化膜、５，４５……ゲート電極、６，４
６……ロコス絶縁膜、７，４７……オフセツト領
域、８……ソース電極、９……ドレイン電極。
Fig. 1 is a structural explanatory diagram of the semiconductor device of the present invention, Fig. 2 is a process diagram of the manufacturing method of the semiconductor device of the present invention, Fig. 3 is a comparison diagram of the on-resistance of the present invention and a conventional example, and Fig. 4
The figure is a structural explanatory diagram of a conventional boss-offset structure semiconductor device. 1,41...Semiconductor substrate, 2,42...Source region, 3,43...Drain region, 4,44...
Gate oxide film, 5, 45... Gate electrode, 6, 4
6...Locos insulating film, 7, 47...offset region, 8...source electrode, 9...drain electrode.
Claims (1)
を有する高耐圧絶縁ゲート電界効果型トランジス
タを含む半導体装置において、ドレイン領域側の
みに該オフセツト領域を形成したことを特徴とす
る高耐圧大電力用絶縁ゲート電界効果型トランジ
スタを含む半導体装置。 A semiconductor device including a high voltage insulated gate field effect transistor having an offset region at a junction near the surface of a semiconductor substrate, wherein the offset region is formed only on the drain region side. A semiconductor device including an effect type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6025787U JPS63167755U (en) | 1987-04-21 | 1987-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6025787U JPS63167755U (en) | 1987-04-21 | 1987-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63167755U true JPS63167755U (en) | 1988-11-01 |
Family
ID=30892511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6025787U Pending JPS63167755U (en) | 1987-04-21 | 1987-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63167755U (en) |
-
1987
- 1987-04-21 JP JP6025787U patent/JPS63167755U/ja active Pending