JPH0258346U - - Google Patents

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Publication number
JPH0258346U
JPH0258346U JP1988137144U JP13714488U JPH0258346U JP H0258346 U JPH0258346 U JP H0258346U JP 1988137144 U JP1988137144 U JP 1988137144U JP 13714488 U JP13714488 U JP 13714488U JP H0258346 U JPH0258346 U JP H0258346U
Authority
JP
Japan
Prior art keywords
mos transistor
transistor
mos
active layer
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988137144U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988137144U priority Critical patent/JPH0258346U/ja
Publication of JPH0258346U publication Critical patent/JPH0258346U/ja
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一実施例を示す平面図、第2図は第1
図のA―A線位置での断面図、第3図Aから同図
Fは一実施例の製造方法を示す断面図、第4図は
他の実施例を示す断面図である。 4……下部電極、6……下部ゲート酸化膜、8
……活性層、10……ソース、12……ドレイン
、14……上部ゲート酸化膜、16……上部電極
FIG. 1 is a plan view showing one embodiment, and FIG. 2 is a plan view showing one embodiment.
3A to 3F are sectional views showing a manufacturing method of one embodiment, and FIG. 4 is a sectional view showing another embodiment. 4... Lower electrode, 6... Lower gate oxide film, 8
...Active layer, 10... Source, 12... Drain, 14... Upper gate oxide film, 16... Upper electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体活性層の一方の側に第1のゲート絶縁膜
を介して第1のゲート電極が設けられて第1のM
OSトランジスタが形成されており、前記半導体
活性層の他方の側に第2のゲート絶縁膜を介して
第2のゲート電極が設けられて第2のMOSトラ
ンジスタが形成されており、かつ、第1のMOS
トランジスタと第2のMOSトランジスタはオン
電流値が異なつており、第1のMOSトランジス
タと第2のMOSトランジスタのオン・オフの組
合せにより4値をとる半導体装置。
A first gate electrode is provided on one side of the semiconductor active layer with a first gate insulating film interposed therebetween.
An OS transistor is formed, a second gate electrode is provided on the other side of the semiconductor active layer via a second gate insulating film to form a second MOS transistor, and a second MOS transistor is formed. MOS
A semiconductor device in which the transistor and the second MOS transistor have different on-current values, and take on four values depending on the on/off combination of the first MOS transistor and the second MOS transistor.
JP1988137144U 1988-10-20 1988-10-20 Pending JPH0258346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988137144U JPH0258346U (en) 1988-10-20 1988-10-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988137144U JPH0258346U (en) 1988-10-20 1988-10-20

Publications (1)

Publication Number Publication Date
JPH0258346U true JPH0258346U (en) 1990-04-26

Family

ID=31398303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988137144U Pending JPH0258346U (en) 1988-10-20 1988-10-20

Country Status (1)

Country Link
JP (1) JPH0258346U (en)

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