JPH0342123U - - Google Patents
Info
- Publication number
- JPH0342123U JPH0342123U JP10174389U JP10174389U JPH0342123U JP H0342123 U JPH0342123 U JP H0342123U JP 10174389 U JP10174389 U JP 10174389U JP 10174389 U JP10174389 U JP 10174389U JP H0342123 U JPH0342123 U JP H0342123U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- insulating film
- interface level
- gate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Description
第１図は本考案の一実施例を示す薄膜トランジ
スタの断面図、第２図は従来の薄膜トランジスタ
の断面図である。
１１……基板、１２……ゲート電極、１３……
ゲート絶縁膜、１４……半導体層、１５……ｎ型
半導体層、１６……ソース電極、１７……ドレイ
ン電極、１８……画素電極、１９……遮光膜、２
０……絶縁膜、２１……高界面準位絶縁膜。
FIG. 1 is a sectional view of a thin film transistor showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional thin film transistor. 11...Substrate, 12...Gate electrode, 13...
Gate insulating film, 14... Semiconductor layer, 15... N-type semiconductor layer, 16... Source electrode, 17... Drain electrode, 18... Pixel electrode, 19... Light shielding film, 2
0... Insulating film, 21... High interface state insulating film.
Claims (1)
、ドレイン電極を積層し、かつ前記半導体層をは
さんで前記ゲート電極と対向する側に絶縁膜を介
して金属からなる遮光膜を設けた薄膜トランジス
タにおいて、前記半導体層と前記遮光膜側の絶縁
膜との間に、前記半導体層との間の界面準位が前
記半導体層と前記ゲート絶縁膜との間の界面準位
より高い絶縁膜を設けたことを特徴とする薄膜ト
ランジスタ。 A thin film transistor in which a gate electrode, a gate insulating film, a semiconductor layer, a source and a drain electrode are stacked, and a light shielding film made of metal is provided on the side facing the gate electrode with the semiconductor layer interposed therebetween, An insulating film is provided between the semiconductor layer and the insulating film on the light-shielding film side, and the interface level with the semiconductor layer is higher than the interface level between the semiconductor layer and the gate insulating film. A thin film transistor featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10174389U JPH0342123U (en) | 1989-09-01 | 1989-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10174389U JPH0342123U (en) | 1989-09-01 | 1989-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342123U true JPH0342123U (en) | 1991-04-22 |
Family
ID=31650676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10174389U Pending JPH0342123U (en) | 1989-09-01 | 1989-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342123U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012077527A1 (en) * | 2010-12-10 | 2012-06-14 | シャープ株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
-
1989
- 1989-09-01 JP JP10174389U patent/JPH0342123U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012077527A1 (en) * | 2010-12-10 | 2012-06-14 | シャープ株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
| JP5336005B2 (en) * | 2010-12-10 | 2013-11-06 | シャープ株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
| US9030619B2 (en) | 2010-12-10 | 2015-05-12 | Sharp Kabushiki Kaisha | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
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