JPH0396052U - - Google Patents
Info
- Publication number
- JPH0396052U JPH0396052U JP422890U JP422890U JPH0396052U JP H0396052 U JPH0396052 U JP H0396052U JP 422890 U JP422890 U JP 422890U JP 422890 U JP422890 U JP 422890U JP H0396052 U JPH0396052 U JP H0396052U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- concentration layer
- low concentration
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 description 3
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の半導体装置の一実施例にかか
るパワー用電界効果型トランジスタの概略縦断面
図、第２図は同実施例の電界効果型トランジスタ
における内部抵抗を模式的に示す概略断面図、第
３図は従来の電界効果型トランジスタを示す概略
断面図である。
１……高濃度基板、３……低濃度層、４ａ……
チヤンネル領域、５……ソース層、７……ゲート
電極、８……ソース電極、９……高濃度層。
FIG. 1 is a schematic vertical cross-sectional view of a power field-effect transistor according to an embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic cross-sectional view schematically showing the internal resistance of the field-effect transistor of the same embodiment. , FIG. 3 is a schematic cross-sectional view showing a conventional field effect transistor. 1...High concentration substrate, 3...Low concentration layer, 4a...
Channel region, 5...source layer, 7...gate electrode, 8...source electrode, 9...high concentration layer.
Claims (1)
を形成し、該低濃度層に他導電形の一対のチヤン
ネル領域を設けると共に一導電形のソース層をそ
れぞれ形成し、ゲート電極とソース電極とをそれ
ぞれに設けてなる半導体装置であつて、 上記他導電形の一対のチヤンネル領域間の一導
電形の低濃度層に、一導電形の高濃度層を形成し
たことを特徴とする半導体装置。[Claims for Utility Model Registration] A low concentration layer of one conductivity type is formed on a high concentration substrate of one conductivity type, a pair of channel regions of the other conductivity type are provided in the low concentration layer, and a source layer of one conductivity type is provided. A semiconductor device comprising a gate electrode and a source electrode, wherein a low concentration layer of one conductivity type and a high concentration layer of one conductivity type are formed between the pair of channel regions of the other conductivity type. A semiconductor device characterized by forming:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP422890U JPH0396052U (en) | 1990-01-19 | 1990-01-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP422890U JPH0396052U (en) | 1990-01-19 | 1990-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0396052U true JPH0396052U (en) | 1991-10-01 |
Family
ID=31507986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP422890U Pending JPH0396052U (en) | 1990-01-19 | 1990-01-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0396052U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003046082A (en) * | 2001-05-25 | 2003-02-14 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
-
1990
- 1990-01-19 JP JP422890U patent/JPH0396052U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003046082A (en) * | 2001-05-25 | 2003-02-14 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP4559691B2 (en) * | 2001-05-25 | 2010-10-13 | 株式会社東芝 | Manufacturing method of semiconductor device |