JPH0379425U - - Google Patents
Info
- Publication number
- JPH0379425U JPH0379425U JP14095189U JP14095189U JPH0379425U JP H0379425 U JPH0379425 U JP H0379425U JP 14095189 U JP14095189 U JP 14095189U JP 14095189 U JP14095189 U JP 14095189U JP H0379425 U JPH0379425 U JP H0379425U
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- impurity diffusion
- semiconductor device
- gate electrode
- low concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図はこの考案の一実施例を示す半導体装置
の断面図、第２図はこの考案による半導体装置の
製造工程を示す断面図、第３図は従来の半導体装
置の製造工程を示す断面図である。
図において、１……半導体基板、２……ゲート
酸化膜、３……ゲート電極、５……濃度の薄い第
１の不純物拡散層、６……濃度が高く、かつ非常
に浅く形成された第２の不純物拡散層、７……サ
イドウオール、８……濃度の高い第３の不純物拡
散層である。なお、各図中の同一符号は同一また
は相当部分を示す。
FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of this invention, FIG. 2 is a cross-sectional view showing the manufacturing process of a semiconductor device according to this invention, and FIG. 3 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device. It is. In the figure, 1... semiconductor substrate, 2... gate oxide film, 3... gate electrode, 5... first impurity diffusion layer with low concentration, 6... first impurity diffusion layer with high concentration and formed very shallowly. 2 impurity diffusion layer, 7...side wall, 8... third impurity diffusion layer with high concentration. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
濃度の低い第１の不純物拡散層と、その表面に極
めて浅く、かつ濃度の高い第２の不純物拡散層と
、ゲート電極の両側に形成されたサイドウオール
をマスクにして注入された第３の不純物拡散層を
備えたことを特徴とする半導体装置。 A relatively low concentration first impurity diffusion layer formed in the source and drain regions, an extremely shallow and highly concentrated second impurity diffusion layer on the surface thereof, and sidewalls formed on both sides of the gate electrode. A semiconductor device comprising a third impurity diffusion layer implanted as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14095189U JPH0379425U (en) | 1989-12-04 | 1989-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14095189U JPH0379425U (en) | 1989-12-04 | 1989-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0379425U true JPH0379425U (en) | 1991-08-13 |
Family
ID=31687886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14095189U Pending JPH0379425U (en) | 1989-12-04 | 1989-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0379425U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009153932A (en) * | 2007-12-28 | 2009-07-16 | Hakubun:Kk | Motor robot |
-
1989
- 1989-12-04 JP JP14095189U patent/JPH0379425U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009153932A (en) * | 2007-12-28 | 2009-07-16 | Hakubun:Kk | Motor robot |
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