JPS6397252U - - Google Patents
Info
- Publication number
- JPS6397252U JPS6397252U JP19164386U JP19164386U JPS6397252U JP S6397252 U JPS6397252 U JP S6397252U JP 19164386 U JP19164386 U JP 19164386U JP 19164386 U JP19164386 U JP 19164386U JP S6397252 U JPS6397252 U JP S6397252U
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- high concentration
- concentration substrate
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図はこの考案に係る縦形ＭＯＳＦＥＴの一
実施例を示す縦断面図、第２図は寄生バイポーラ
トランジスタを含む同上一実施例の等価回路を示
す回路図、第３図はこの考案の他の実施例を示す
縦断面図、第４図は従来の縦形ＭＯＳＦＥＴを示
す縦断面図である。
１：Ｎ＋基板領域（第１導電形の高濃度基板領
域）、２：Ｎ形領域（第１導電形領域）、３：Ｐ
ウエル領域、４：Ｎ＋ソース領域、５：チヤネル
、６：ゲート絶縁膜、７：ゲート電極、９：ソー
ス電極、１１：ドレイン電極。
FIG. 1 is a longitudinal cross-sectional view showing one embodiment of a vertical MOSFET according to this invention, FIG. 2 is a circuit diagram showing an equivalent circuit of the same embodiment including a parasitic bipolar transistor, and FIG. 3 is a diagram showing another embodiment of this invention. FIG. 4 is a vertical cross-sectional view showing a conventional vertical MOSFET. 1: N + substrate region (first conductivity type high concentration substrate region), 2: N type region (first conductivity type region), 3: P
well region, 4: N + source region, 5: channel, 6: gate insulating film, 7: gate electrode, 9: source electrode, 11: drain electrode.
Claims (1)
ンとして作用する第１導電形領域と、 該第１導電形領域に形成され底部において前記
高濃度基板領域に接する第２導電形のウエル領域
と、 該ウエル領域内に形成され前記ウエル領域およ
び高濃度基板領域とともに低パンチスルー耐性を
有する寄生バイポーラトランジスタが形成される
第１導電形のソース領域と、 該ソース領域と前記第１導電形領域との間の前
記ウエル領域上にゲート絶縁膜を介して設けられ
当該ウエル領域にチヤネルを誘起させるゲート電
極と を有することを特徴とする縦形ＭＯＳＦＥＴ。[Claims for Utility Model Registration] A high concentration substrate region of a first conductivity type; a first conductivity type region formed on the high concentration substrate region and acting substantially as a drain; and a first conductivity type region formed in the first conductivity type region. a well region of a second conductivity type that is in contact with the high concentration substrate region at its bottom; and a first parasitic bipolar transistor formed in the well region and having low punch-through resistance together with the well region and the high concentration substrate region. A conductivity type source region; and a gate electrode provided on the well region between the source region and the first conductivity type region via a gate insulating film and inducing a channel in the well region. Vertical MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19164386U JPS6397252U (en) | 1986-12-15 | 1986-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19164386U JPS6397252U (en) | 1986-12-15 | 1986-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6397252U true JPS6397252U (en) | 1988-06-23 |
Family
ID=31145972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19164386U Pending JPS6397252U (en) | 1986-12-15 | 1986-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6397252U (en) |
-
1986
- 1986-12-15 JP JP19164386U patent/JPS6397252U/ja active Pending
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