JPH0160554U - - Google Patents
Info
- Publication number
- JPH0160554U JPH0160554U JP15474787U JP15474787U JPH0160554U JP H0160554 U JPH0160554 U JP H0160554U JP 15474787 U JP15474787 U JP 15474787U JP 15474787 U JP15474787 U JP 15474787U JP H0160554 U JPH0160554 U JP H0160554U
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- low concentration
- channel
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Description
第１図はこの考案に係る縦形ＭＩＳＦＥＴの実
施例を示す縦断面図、第２図は同上実施例の製造
工程の一例を示す工程図、第３図は従来の縦形Ｍ
ＩＳＦＥＴを示す縦断面図である。
１：Ｎ形基板領域、２：Ｐ形の低濃度チヤネル
領域、２ａ：チヤネル、３：Ｐ＋埋込み領域、４
：Ｎ＋ソース領域、５：Ｐ＋コンタクト領域、６
：Ｖ形溝、７：ゲート絶縁膜、８：ゲート電極、
１１：ドレイン電極、１０：第１のＮ形半導体基
板、２０：第２のＮ形半導体基板。
FIG. 1 is a vertical cross-sectional view showing an embodiment of the vertical MISFET according to this invention, FIG. 2 is a process diagram showing an example of the manufacturing process of the same embodiment, and FIG. 3 is a conventional vertical MISFET.
FIG. 2 is a longitudinal cross-sectional view showing an ISFET. 1: N-type substrate region, 2: P-type low concentration channel region, 2a: channel, 3: P + buried region, 4
:N + source region, 5:P + contact region, 6
: V-shaped groove, 7: Gate insulating film, 8: Gate electrode,
11: drain electrode, 10: first N-type semiconductor substrate, 20: second N-type semiconductor substrate.
Claims (1)
上に第２導電形の低濃度チヤネル領域が形成され
た基板体と、 該基板体との直接接合により前記低濃度チヤネ
ル領域上に形成された第１導電形のソース領域と
、 該ソース領域および前記低濃度チヤネル領域を
貫通して前記基板領域に達する溝の内壁面に形成
されたゲート絶縁膜と、 該ゲート絶縁膜上に設けられ前記低濃度チヤネ
ル領域にチヤネルを誘起させるゲート電極と、 前記低濃度チヤネル領域内に形成された第２導
電形の高濃度埋込み領域と を有することを特徴とする縦形ＭＩＳＦＥＴ。[Claims for Utility Model Registration] A substrate body in which a low concentration channel region of a second conductivity type is formed on a substrate region of a first conductivity type that acts as a drain, and the low concentration channel is formed by direct bonding with the substrate body. a source region of a first conductivity type formed on the region; a gate insulating film formed on an inner wall surface of a trench that penetrates the source region and the low concentration channel region and reaches the substrate region; and the gate insulating film. A vertical MISFET comprising: a gate electrode provided above to induce a channel in the lightly doped channel region; and a heavily doped buried region of a second conductivity type formed in the lightly doped channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15474787U JPH0160554U (en) | 1987-10-12 | 1987-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15474787U JPH0160554U (en) | 1987-10-12 | 1987-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0160554U true JPH0160554U (en) | 1989-04-17 |
Family
ID=31431754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15474787U Pending JPH0160554U (en) | 1987-10-12 | 1987-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0160554U (en) |
-
1987
- 1987-10-12 JP JP15474787U patent/JPH0160554U/ja active Pending
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