JPS61158961U - - Google Patents

Info

Publication number
JPS61158961U
JPS61158961U JP4288585U JP4288585U JPS61158961U JP S61158961 U JPS61158961 U JP S61158961U JP 4288585 U JP4288585 U JP 4288585U JP 4288585 U JP4288585 U JP 4288585U JP S61158961 U JPS61158961 U JP S61158961U
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
conductivity type
drain region
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4288585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4288585U priority Critical patent/JPS61158961U/ja
Publication of JPS61158961U publication Critical patent/JPS61158961U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る高耐圧MOS―FETの
断面の構成例を示した図、第2図は第1図の等価
回路を示す図、第3図は第4図の平面図、第4図
は従来のnチヤネルの高耐圧MOS―FETの断
面図、第5図は領域10と領域4の不純物濃度と
深さとの関係を示す図である。 1…基板、2…P領域、3…n領域、4…
領域、5…ドリフトチヤネル、6…絶縁層、
7…ソース電極、8…ゲート電極、9…ドレイン
電極、10…P領域。
1 is a diagram showing an example of the cross-sectional configuration of a high voltage MOS-FET according to the present invention, FIG. 2 is a diagram showing an equivalent circuit of FIG. 1, and FIG. 3 is a plan view of FIG. The figure is a cross-sectional view of a conventional n-channel high voltage MOS-FET, and FIG. 5 is a diagram showing the relationship between the impurity concentration and depth of regions 10 and 4. DESCRIPTION OF SYMBOLS 1...Substrate, 2...P + area, 3...n + area, 4...
n + region, 5... drift channel, 6... insulating layer,
7... Source electrode, 8... Gate electrode, 9... Drain electrode, 10... P region.

Claims (1)

【実用新案登録請求の範囲】 ドレイン領域が基板の半導体と反対の伝導型を
有するプレーナ型のFETにおいて、 ドレイン領域の内部に基板の半導体と同じ伝導
型であり、不純物濃度が基板の半導体より高く、
かつ深さがドレイン接合よりも深い拡散層を有し
たことを特徴とする高耐圧MOS―FET。
[Claim for Utility Model Registration] In a planar FET in which the drain region has a conductivity type opposite to that of the semiconductor in the substrate, the drain region has the same conductivity type as the semiconductor in the substrate and has a higher impurity concentration than the semiconductor in the substrate. ,
A high voltage MOS-FET characterized in that it has a diffusion layer that is deeper than the drain junction.
JP4288585U 1985-03-25 1985-03-25 Pending JPS61158961U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4288585U JPS61158961U (en) 1985-03-25 1985-03-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4288585U JPS61158961U (en) 1985-03-25 1985-03-25

Publications (1)

Publication Number Publication Date
JPS61158961U true JPS61158961U (en) 1986-10-02

Family

ID=30554039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4288585U Pending JPS61158961U (en) 1985-03-25 1985-03-25

Country Status (1)

Country Link
JP (1) JPS61158961U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56134773A (en) * 1980-03-26 1981-10-21 Nec Corp Mos semiconductor device
JPS5969957A (en) * 1982-10-15 1984-04-20 Nec Corp Protective device for output

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56134773A (en) * 1980-03-26 1981-10-21 Nec Corp Mos semiconductor device
JPS5969957A (en) * 1982-10-15 1984-04-20 Nec Corp Protective device for output

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