JPS5969957A - Protective device for output - Google Patents
Protective device for outputInfo
- Publication number
- JPS5969957A JPS5969957A JP18111182A JP18111182A JPS5969957A JP S5969957 A JPS5969957 A JP S5969957A JP 18111182 A JP18111182 A JP 18111182A JP 18111182 A JP18111182 A JP 18111182A JP S5969957 A JPS5969957 A JP S5969957A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- diode
- drain
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は相補型ＭＯ８集積回路の出力保護装置に関し、
特ｖｃ５■程度の低電圧動作の出力保護装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output protection device for a complementary MO8 integrated circuit;
This invention relates to an output protection device that operates at a low voltage of about VC5■.
一般ｇ、ＭＯ８トランジスタの出力部に、外部から静電
荷が加わった場合、ドレインとオーツ（−ラップしてい
るゲート酸化膜が破壊する場合が多い。その為、従来よ
り種々の保護装置が考えられているが、その基本的な考
え万は、ドレイ４ンと基板との間にダイオードを挿入し
て静電荷を逃がしてしまうということである。ところで
、従来ニジ用いられているダイオードの場合、その接合
部が。General g. When static charge is applied from the outside to the output section of an MO8 transistor, the drain and the gate oxide film that overlaps are often destroyed.For this reason, various protection devices have been considered in the past. However, the basic idea is to insert a diode between the drain and the board to release the static charge.By the way, in the case of the diode that is conventionally used, The joint.
電流集中のため破壊してしまうため、充分な強度を得る
ことができなかった。これラフ。、図面を用いて説明す
る。It was not possible to obtain sufficient strength because it would break due to current concentration. This is rough. , will be explained using drawings.
第１図は従来の出力保護装置の一例の回路図である。FIG. 1 is a circuit diagram of an example of a conventional output protection device.
出力端子４ｖｃ入った静電荷１’；［：Ｉ ＶＤＤ側へ
はダイオード１を介してｂ ＶＢ２側へはダイオード２
を介して吸収される。ところがこの場合、静電荷の吸収
されるパスがどちらか一万のダイオードのみであり、寄
生的に入っているｖｓｓ ＶＤＤ間のダイオード３に
、通常ダイオードｌ、 ２ニジも耐圧が高いたメニ電
荷の充放電パスとしては有効に働かないため、電流集中
奮起しやすく、ダイオードの接合破壊強度が弱いという
弱点がある。従って、従来はダイオード面積を太きくし
て強度向上を企って＠たが必ずしも満足のいく結果はイ
４１られていなく、充分な耐接合部破壊強度を有する出
力保護装置が得られていないという欠点があった。Static charge 1' that entered the output terminal 4vc;[:I B to the VDD side via diode 1 b to the VB2 side
absorbed through. However, in this case, the path through which the static charge is absorbed is only one of the 10,000 diodes, and the diode 3 between the Since it does not work effectively as a charge/discharge path, it is prone to current concentration and has weak diode junction breakdown strength. Therefore, conventional attempts have been made to increase the strength by increasing the diode area, but the results have not always been satisfactory, and the disadvantage is that an output protection device with sufficient junction breakdown strength has not been obtained. was there.
本発明は上記欠点を除去し、ゲー１− ’（Ｑ保護し、
かつ耐接合部破壊強度が充分に太きい出力保護袋！全提
供するものである。The present invention eliminates the above drawbacks and protects the game 1-' (Q).
An output protection bag with sufficient joint breakage strength! All that is offered.
本発明の出力保護装置ば、−導電型半導体基板に設けら
れた第１のＭＯＳＦＥＴのドレインに接続する一導電型
でかつ高濃度の第１領域と前記ドレインとで構成される
第１のダイオードと、前記半導体基板に設けられた反対
４を型ウェル内に設けられかつドレインが前記第１のＭ
ＯＳＦＥＴのドレインと接続する第２のＭＯＳＦＥＴの
ドレインに接続する反対４電型でかつ高濃度の第２領域
と前記第２のＭＯＳＦＥＴのドレインとで構成される第
２のダイオードと、前記第１領域と第２領域の両方に接
続する反対導電型でかつ高濃度の第３領域と前記第１領
域とで構成されかつ前記第１及び第２のダイオードと同
じ耐圧を有する第３のダイオードとを含んで構成される
。The output protection device of the present invention includes: - a first diode configured of the drain and a first region of one conductivity type and high concentration connected to the drain of the first MOSFET provided on the conductivity type semiconductor substrate; , the opposite 4 provided in the semiconductor substrate is provided in the mold well, and the drain is provided in the first M
a second diode comprising a second region of opposite quaternary electric type and high concentration connected to the drain of a second MOSFET connected to the drain of the OSFET; and the first region; and a third diode configured of a third region of an opposite conductivity type and of high concentration connected to both the first region and the first region and having the same breakdown voltage as the first and second diodes. Consists of.
次に１本発明の実施例について図面を用いて説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例の断面図、第３図μ第２図に
示す一実施例の等価回路図である。FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of the embodiment shown in FIG. 2.
−得電型全Ｎ型として説明する０−４を型金Ｐ型とする
場合は以下の説明においてすべての極性を逆にすれば良
い。- If 0-4, which will be described as an all-N type power gain type, is made into a P type mold, all polarities may be reversed in the following description.
Ｎ型半導体基板１１１’ｎ第１のＭＯＳＦＥＴ６のＰ型
ソース領域１２．Ｐ型ドレイン領域１３を設ける。N-type semiconductor substrate 111'n P-type source region 12 of first MOSFET 6. A P-type drain region 13 is provided.
また、Ｐウェル１４を設け、その内に第２のＭＯＳＦＥ
Ｔ７のＮ型ソース領域１５とＮ型ドレイン領域１６とを
設ける。第１のＭＯ８ＦＥ’ｌ’６のドレイン領域１３
ｖＣ接続するＮ型で高濃度の第１領域１７を陰極とする
第１のダイオード１を構成する。第２のＭＯＳＦＥＴ７
のドレイン領域１６に接続するＰ型で高濃度の第２領域
１８を設け、第２領域１８を陽極、ト２レイン領域１６
を陰極とする第２のダイオード２を構成する。更に、第
１領域１７と第２領域１８の両方に接続するＰ型で高濃
度の第３領域１９′ｆＫ：設け、第３領域１９を陽極、
第２領域１７を陰極とする第３のダイオード５を構成す
る。Further, a P-well 14 is provided, in which a second MOSFE is connected.
An N type source region 15 and an N type drain region 16 of T7 are provided. Drain region 13 of first MO8FE'l'6
A first diode 1 is configured with the N-type, high concentration first region 17 connected to vC as a cathode. Second MOSFET7
A P-type high concentration second region 18 connected to the drain region 16 of the drain region 16 is provided, and the second region 18 is used as an anode and the second region 16
A second diode 2 is configured with the cathode being . Furthermore, a P-type high concentration third region 19'fK connected to both the first region 17 and the second region 18 is provided, and the third region 19 is used as an anode.
A third diode 5 is configured using the second region 17 as a cathode.
第３のダイオード５は第１及び第２のダイオード１．２
と同じ耐圧を有するＬ９に形成することが必要である。The third diode 5 is the first and second diode 1.2
It is necessary to form L9 having the same breakdown voltage as .
尚、第２領域１８と第３領域１９とは１体構造で同時に
形成されるもので１通常ウェルのＰＮ接合上端部分に作
られるガードリングをウェル１４内のドレイン領域１６
ｖｃ接続する１で拡げたものとして良い、そして、第１
領域１７μドレイン領域１３とガードリングとの両方に
接続するように形成するとして良い。The second region 18 and the third region 19 are formed at the same time in one structure, and the guard ring formed at the upper end of the PN junction in the well 14 is connected to the drain region 16 in the well 14.
It may be expanded with 1 connected to vc, and the 1st
Region 17μ may be formed so as to be connected to both the drain region 13 and the guard ring.
以後の工程に通常の方法［ｊ５酸化膜２０、ゲーｈ絶縁
膜２１を設け、窓あけして配線２２．ゲート電極２３．
２４を設ける。配線２２が第３図の出力端子４に接続す
る。The subsequent steps are carried out using the usual method [J5 oxide film 20, GeH insulating film 21 are provided, a window is opened and wiring 22. Gate electrode 23.
24 will be provided. Wiring 22 connects to output terminal 4 in FIG.
次にこの夾施例の動作について説明する。出力端子４（
配線２２ ） ｄ−ら入った静電荷はＶＤＤ側へはダイ
オード１を介して吸収されると共に、ダイオード２．ダ
イオード５を介しても吸収されるＯ同ＲＶＣ％ Ｖｓｓ
側へはダイオード２ｆ介して吸収されると共にダイオー
ド１．ダイオード５を介しても吸収される。このように
′階流経路を増やすことによってダイオード部分の接合
破壊強度を高めることかでさる。Next, the operation of this embodiment will be explained. Output terminal 4 (
The static charge entering wiring 22) d- is absorbed to the VDD side via diode 1, and is also absorbed by diode 2. O RVC% also absorbed through diode 5 Vss
side is absorbed through diode 2f and is absorbed by diode 1. It is also absorbed through the diode 5. By increasing the number of stepwise paths in this way, the junction breakdown strength of the diode portion can be increased.
以上詳細に説明したようＶＣ，本発明ｖｃ、よれば耐接
合部破壊強度が充分大きい相補型ＭＯ８集積回路の出力
保護装置が得られるのでその効果に大きい０As explained in detail above, according to the VC and the VC of the present invention, an output protection device for a complementary MO8 integrated circuit with sufficiently high junction breakdown strength can be obtained, so that the effect is large.
【図面の簡単な説明】
第１図は従来の出力保護装置の一例の回路図。
第２図μ本発明の一実施例の断面図、第３図は第２図に
示す一実施例の等価回路図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an example of a conventional output protection device. FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of the embodiment shown in FIG.
Claims (1)
ドレインに接続する一導電型でかつ高濃度の第１領域と
前記ドレインとで構成される第１のダイオードと、前記
半導体基板に設けられた反対導電型ウェル内に設けられ
かつドレインが前記第１のＭＯＳＦＥＴのドレインと接
続する第２のＭＯＳＦＥＴのドレインに接続する反対導
電型でかつ高濃度の第２領域と前記第２のＭＯＳＦＥＴ
のドレインとで構成される第２のダイオードと、前記第
１領域と第２領域の両方に接続する反対導電型でかつ高
濃度の第３領域と前記第１領域とで構成されかつ前記第
１及び第２のダイオードと同じ耐圧を有する第３のダイ
オードとを含むことを特徴とする出力保護装置。a first diode connected to a drain of a first MOSFET provided on a semiconductor substrate of one conductivity type and configured of a first region of one conductivity type and having a high concentration and the drain; a second region of a high concentration and of an opposite conductivity type connected to a drain of a second MOSFET which is provided in a well of an opposite conductivity type and whose drain is connected to the drain of the first MOSFET; and the second MOSFET;
a second diode comprising a drain of the second diode, a third region of an opposite conductivity type and high concentration connected to both the first region and the second region, and the first region; and a third diode having the same breakdown voltage as the second diode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18111182A JPS5969957A (en) | 1982-10-15 | 1982-10-15 | Protective device for output |
| US06/542,369 US4607274A (en) | 1982-10-15 | 1983-10-17 | Complementary MOS field effect transistor integrated circuit with protection function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18111182A JPS5969957A (en) | 1982-10-15 | 1982-10-15 | Protective device for output |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5969957A true JPS5969957A (en) | 1984-04-20 |
Family
ID=16095035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18111182A Pending JPS5969957A (en) | 1982-10-15 | 1982-10-15 | Protective device for output |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5969957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61158961U (en) * | 1985-03-25 | 1986-10-02 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
-
1982
- 1982-10-15 JP JP18111182A patent/JPS5969957A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61158961U (en) * | 1985-03-25 | 1986-10-02 |
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