JP2839375B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device comprising a thin film field effect type MOS transistor formed on an insulator layer, and more particularly to a structure of a diode element and a resistance element.

[0002]

2. Description of the Related Art First, a thin film field effect MOS transistor (hereinafter referred to as SOI MOSFE) formed on an insulator layer.
The basic structure (denoted by T) will be described with reference to FIG. FIG. 9 shows a P-channel MOSFET (hereinafter, P-MO) on the same substrate.
SFET) and an N-channel MOSFET (hereinafter referred to as N
FIG. 4 is a cross-sectional view when a -MOSFET is formed.
Figure (a) shows the MO formed in a typical silicon wafer.
SFET (hereinafter referred to as bulk MOSFET), same figure
(b) is the SOI MOSFET. In the figure, 1 is a silicon wafer, 2 is an insulator layer formed on the silicon wafer 1, 3 is a p ^- impurity region forming a channel portion of an N-MOSFET, and 4 is a channel portion of a P-MOSFET. n ^- impurity region 5 _1, 5 ₂ n-MO
N ⁺ impurity region forming the source and drain of the SFET, 5 ₃ are n ^- n ⁺ impurity region formed for electrically bonded to the impurity regions 4, 6 _1, 6 ₂ P-MOSFET
P ⁺ impurity region forming the source / drain of P ₃ , and p ₃ formed to form an electrical junction with p ⁻ impurity region 3
⁺ Impurity region, 7 is a polysilicon layer forming a gate electrode, 10 is a side wall, 8 is a polysilicon layer 7 and p
^- impurity region 3 or n ^- oxide film layer between the impurity regions 4, LOCOS layer to separate from other potential of the p ⁺ impurity regions _{61 and} 62 ₂ or n ⁺ impurity regions 5 _1, 5 ₂ 9 ,
28 is a back gate potential for fixing the potential of the silicon wafer in the SOI MOSFET. 21 is VDD, 22 is VSS, 23 is the gate terminal of the N-MOSFET, 24 is the gate terminal of the P-MOSFET, 25 is the drain terminal of the N-MOSFET and the P-MOSFET, and is connected to the MOSFET by metal wiring. Have been.

Next, the operation will be described. For bulk MOSFET shown in FIG. 9 (a), p ^- V impurity region 3
By applying the potential of VDD21 to the SS22, n ^- impurity region 4, a stable depletion layer is generated in the channel portions of the P-MOSFET and the N-MOSFET.

On the other hand, the SOI MO shown in FIG.
In the case of the SFET, a thin layer is formed on the insulator layer 2 so that the p ^- impurity region 3 and the n ^- impurity region 4 are completely depleted. Therefore, VDD 21 and VSS 2 are added to the p ⁻ impurity region 3 and the n ⁻ impurity region 4 as described with reference to FIG.
2 is connected to the SOI MOSFET shown in FIG.
Is no longer necessary. However, when a semiconductor integrated circuit device is realized using only SOI MOSFETs, the withstand voltage with respect to a voltage when an instantaneously high potential difference such as surge is applied to a buffer circuit interfacing with the outside of the device decreases. This will be described below.

First, a buffer circuit using a bulk MOSFET will be described. FIG. 8 is a circuit diagram showing an example of a buffer circuit composed of a bulk MOSFET. FIG. 8A shows an output buffer circuit, and FIG. 8B shows an input buffer circuit. In the figure, 21 is VDD, 22 is VSS, 31 is an N-MOSFET, 32 is a P-MOSFET, and 23 is N
A gate input terminal of MOSFET 31;
Gate input terminal of SFET 32, 25 is N-MOSFE
It is assumed that the drain electrodes of the T31 and the P-MOSFET 32 are connected to the outside of the semiconductor integrated circuit device. Also 2
Reference numeral 6 denotes an inverter circuit for receiving an external signal, 29 denotes a resistor for protecting the inverter circuit 26 from a momentary high potential difference, and 27 denotes an output terminal of the input buffer circuit.

In FIG. 8, both an output buffer circuit and an input buffer circuit have a drain electrode 2 connected to the outside of the device.
5, when a voltage higher than VDD21 is applied, PM
A current flows to VDD 21 via OSFET 32,
When a voltage lower than VSS22 is applied to the drain electrode 25, the voltage of VSS22
Current flows from the As a result, in the buffer circuit composed of the bulk MOSFET, the N-MOSFET 31 and P
-High voltage is VDD21, VS by the action of MOSFET32
It escapes to the outside of the apparatus through S22.

Next, this operation will be described with reference to FIG. 9 (a), the case where the drain terminal 25 applied voltage higher than VDD21, n potential of the p ⁺ impurity regions ₆₁ and VDD21 to be connected to the drain terminal 25 is supplied ^- impurity region 4 the forward junction And the drain terminal 25
Through the n ⁻ impurity region 4 to VDD 21. Also, if the drain terminal 25 is lower voltage than VSS22 applied, the n ⁺ impurity region 5 ₁ connected to the drain terminal 25, p potential of VSS22 is supplied ^- impurity region 3 is forward junction , VSS 22 to the drain terminal 25 via the p ⁻ impurity region 3.

[0008] However, in the case of the SOI MOSFET, as shown in FIG. 9 (b), n ^- impurity region 4 and the p ^-
Since VDD 21 or VSS 22 is not connected to impurity region 3, when a voltage higher than VDD 21 is applied to drain terminal 25, n ⁻ impurity region 4 and VDD are not connected.
21 is to have p ⁺ impurity region 6 ₂ reverse junction connecting result, no charge will flow to VDD21. When a voltage lower than VSS22 is applied to the drain terminal 25, p
^- n ⁺ impurity region 5 ₂ where the impurity region 3 VSS22 is connected a result reversed junction, the charge does not flow from VSS22. Therefore, in the case of the SOI MOSFET, when a large voltage is momentarily applied to the drain terminal 25, the MOSI
The PN junction of the FET is destroyed.

In order to solve the problem described above,
In the semiconductor integrated circuit device constituted by the SOI MOSFET, a diode element connected from the drain terminal 25 connected to the outside to the VDD 21 and the VSS 22 is newly required.

An example of such a buffer circuit will be described with reference to FIG. Figure 5 shows SOI MOSFET
It is a circuit diagram showing an example of a buffer circuit configured by
FIG. 3A shows an output buffer circuit, and FIG. 3B shows an input buffer circuit. In the figure, 21 is VDD, 22 is VS
S and 31 are N-MOSFETs and 32 is a P-MOSFE
T and 23 are gate input terminals of the N-MOSFET 31;
4 is a gate input terminal of the P-MOSFET 32, 25 is N
-Assume that the drain electrodes of the MOSFET 31 and the P-MOSFET 32 are connected to the outside of the semiconductor integrated circuit device. Reference numeral 26 denotes an inverter circuit for receiving an external signal, and reference numeral 27 denotes an output terminal of the input buffer circuit. 29 is a resistance element, and 33 and 34 are diode elements.

In the example shown in FIG. 5, when a voltage higher than VDD 21 is applied to the terminal 25 connected to the outside, a current flows through the diode 34 to VDD 21,
When a voltage lower than VSS22 is applied, a current flows from VSS22 through diode 33. In this example, MOSFETs 31 and 32 and inverter circuit 26 do not need to be destroyed.

Next, an example of a conventional configuration of the diode described in FIG. 5 will be described. 6A and 6B show an example of a diode element obtained by a manufacturing flow for forming an SOI MOSFET. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along a line AB in FIG. . In Fig, 5 ₄ n ⁺ impurity region 6 ₄
Is a p ⁺ impurity region, 1 is a silicon wafer, 2 is an insulator layer, 9 is a LOCOS layer, 28 is a back gate potential, 42
Is a contact hole, and 43 and 44 are diode terminals. Further, portions 205 of doping an n ⁺ impurity at the time of manufacture, location 206 of doping p ⁺ impurity, 203 p ^- portion of doping impurities, respectively n ⁺ impurity region 5 ₄ 105, 106, p ⁺ impurity regions 6 shows a _fourth surface.

As shown in FIG. 6, when a diode is formed by a conventional technique, the same layer as p ⁺
Impurity regions 6 ₄ and the n ⁺ impurity region 5 ₄ adjacent, may do it by setting the n ⁺ doped portion 205 and p ⁺ doped portion 206 as PN junction is formed.

However, in recent years, even in SOI MOSFETs, the surface of the source, drain, and gate is often made to have a low resistance by silicidation or the like as a means of increasing the speed. In this case, no current flows through the PN junction, so that the diode does not operate. Therefore, in the prior art, it is necessary not to lower the resistance of only the diode portion.

Next, the resistance element shown in FIG. 5B will be described. Conventionally, as a method of realizing a resistor, MOSF
ET on resistance, polysilicon resistance, n impurity or p
A method using the resistance of the impurity is conceivable. However,
Resistor 2 for the purpose of making high voltage difficult to conduct as shown in FIG.
In the case of 9, the on-resistance of the MOSFET cannot be used because there is a risk of breaking the PN junction. Further, in the case of using the polysilicon resistance and the resistance of the n impurity or the p impurity, if the resistance of the polysilicon and the silicon surface is reduced by silicidation, the resistance value is significantly reduced. This will be described with reference to a case where p ⁺ impurity resistance is used.

FIG. 7 shows an example of a resistance element obtained by a manufacturing flow for forming an SOI MOSFET.
2 is a plan view, and FIG. 2B is a cross-sectional view taken along a line AB in FIG. In FIG, _{6. 4} p ⁺ impurity region, 1 is a silicon wafer, 2 denotes an insulating layer, 28 is a back gate potential, 9
Is a LOCOS layer, 42 is a contact hole, 45 and 46
Is a terminal of the resistance element. Further, 206 portions of doping p ⁺ impurity, 203 p ^- portion of doping impurities, 106 denotes a surface of the p ⁺ impurity region 6 _4.

As shown in FIG. 7, when a resistance element is formed by the conventional technique, ap ⁺ impurity layer 6 is formed on the insulator layer 2.
_The p ⁺ impurity-doped portion 206 may be set so as to form ₄ .

[0018] However, when a low-resistance silicon and polysilicon surfaces, such as silicidation, the surface 106 of the even resistor element p ⁺ impurity region 6 ₄ SOI M
Since the resistance is reduced at the same time as the OSFET, a sufficient resistance value cannot be obtained. If a sufficient resistance value is to be obtained, the area of the resistance element becomes very large. Therefore, in the prior art, it is necessary to prevent the resistance element portion from lowering its resistance.

[0019]

SUMMARY OF THE INVENTION Conventional SOI MOS
Since a semiconductor integrated circuit device using an FET is configured as described above, a diode or a resistor cannot be formed when a technology for lowering the silicon or polysilicon surface such as silicidation is applied. It is necessary to change the manufacturing method so that only the resistance portion does not lower the resistance, which causes problems such as an increase in the number of steps and an increase in the number of masks, and a reduction in the resistance of the entire semiconductor integrated circuit device. If not, a diode and a resistor can be formed, but the operation of the SOI MOSFET becomes slow.

The present invention has been made in order to solve the above-described problems. Even when the resistance of the silicon or polysilicon surface such as silicidation is reduced, the SOI MOS is used.
It is an object of the present invention to obtain a semiconductor integrated circuit device in which a diode element can be formed by the same flow as that for manufacturing an FET.

Further, according to the present invention, even when the resistance of the silicon or polysilicon surface is reduced, such as by silicidation, the SO
It is an object of the present invention to provide a semiconductor integrated circuit device in which a resistance element can be formed by the same flow as that for manufacturing an IMOSFET.

[0022]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention comprises an insulator layer and an MO formed on the insulator layer.
S field effect transistor, p-type semiconductor layer and n-type semiconductor
Element having junction of layers and first semiconductor layer
And a second semiconductor layer of the same conductivity type as the first semiconductor layer.
, A p-type semiconductor layer and an n-type semiconductor
Layer, a low-resistance layer formed inside the first semiconductor layer
And a MOS field effect transistor on a part of the semiconductor layer.
Polysilicon layer and oxide film formed during gate formation
Layer and the side of these silicon oxide and polysilicon layers
It has a side wall formed on a surface portion .

[0023]

[0024]

According to the present invention, an impurity region table of a resistance element is provided.
A part of the surface formed during MOSFET gate formation
The silicon oxide film layer, these silicon oxide film layers,
Mask the sidewall formed on the side of the recon layer
To form a low-resistance layer in a self-aligned manner
In the semiconductor integrated circuit device with reduced resistance,
A resistance element can be obtained.

[0025]

[0026]

1A and 1B are views showing the structure of a diode according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along a line AB in FIG. FIG. In the drawing, 1 is a silicon wafer, 28 is a back gate potential, 2 is an insulator layer, 3 is a p ⁻ impurity region, 5 ₄ is an n ⁺ impurity region, 6 ₄
Is a p ⁺ impurity region, 9 is a LOCOS layer, 7 is a polysilicon layer, 8 is an oxide film layer, 10 is a sidewall, 105,
Reference numeral 106 denotes a surface portion whose resistance has been reduced by silicidation or the like. Reference numerals 43 and 44 denote diode terminals, and reference numeral 42 denotes a contact hole. Further, reference numeral 205 denotes a portion to be doped with an n ⁺ impurity at the time of manufacturing;
Portions of doping p ⁺ impurity time, 203 during manufacturing p ^-
The portions where impurities are doped are shown.

In the case of the diode in this embodiment, p ⁻
Upper oxide film layer 8 of the impurity region 3, thereby forming a polysilicon layer 7, p ^- to form the n ⁺ impurity region 5 ₄ and the p ⁺ impurity region 6 ₄ on both sides of the impurity region 3. With this structure, due to silicidation, n ⁺ surface 106 of the impurity region 5 ₄ of the surface 105 and the p ⁺ impurity region 6 ₄
There also be low resistance, p for the oxide film layer 8 ^- junction of the impurity region 3 and the n ⁺ impurity region 5 ₄ is not lower resistance, which functions as a diode.

The structure described with reference to FIG. 1 can be realized as follows. First, L is placed on all sides of the insulator layer 2.
An undoped thin-film silicon layer surrounded by the OCOS layer 9 is formed, and a portion indicated by 203 is doped with ap ⁻ impurity so as to cover the silicon layer. The other part becomes the p ^- impurity layer. Next, the p ^- oxide film layer 8 and the polysilicon layer 7 so as to cross the impurity layer to form a side wall 10, and the polysilicon layer 7 as a boundary, the n ⁺ impurity to a position shown in 205, 206 Are doped with p ⁺ impurities, the p ⁻ impurity region 3 immediately below the polysilicon layer 7 is not doped, and the n ⁺ impurity regions 5 ₄ and p ⁺
Impurity regions 6 ₄ is formed. Thereafter, when the titanium silicide, but n ⁺ surface 105 of the impurity region 5 _4, p ⁺ surface 106 and the polysilicon layer 7 of impurity regions 6 ₄ is low resistance, n ⁺ impurity regions for the sidewall 10 5 ₄ surface 105 and the surface 10 of the P ⁺ impurity region 6 ₄
6 does not short circuit.

Here, since the oxide film layer 8 and the polysilicon layer 7 are formed at the time of forming the gate of the MOSFET, it is not necessary to increase the number of manufacturing steps to form them.

FIGS. 2 (a) and 2 (b) show the construction of a diode according to a second embodiment of the present invention. FIG. 2 (a) is a plan view and FIG. 2 (b) is a cross section taken along the line AB in FIG. FIG. In the figure, 1
Is a silicon wafer, 28 is a back gate potential, 2 is an insulator layer, 4 is an n ⁻ impurity region, 5 ₄ is an n ⁺ impurity region,
₄ is a p ⁺ impurity region, 9 is a LOCOS layer, 7 is a polysilicon layer, 8 is an oxide film layer, 10 is a sidewall, 10
Reference numerals 5 and 106 denote portions whose resistance has been reduced by silicidation or the like. 43 and 44 are diode terminals;
2 is a contact hole. Further, reference numeral 204 denotes a portion to be doped with an n ⁻ impurity during manufacturing, 205 denotes a portion to be doped with an n ⁺ impurity, and 206 denotes a portion to be doped with a p ⁺ impurity. Figure In the embodiment shown in 2, n ^- upper oxide film layer 8 of the impurity regions 4, thereby forming a polysilicon layer 7, n ^- n ⁺ impurity region 5 ₄ on both sides of the impurity regions 4
To form a p ⁺ impurity region 6 _4.

The implementation of the structure shown in FIG. 2 is similar to the method described with reference to FIG. 1, and instead of doping the p ^- impurity, the portion indicated by 204 may be doped with an n ^- impurity. In this case as well, with the polysilicon layer 7 as a boundary, 205
The n ⁺ impurity at positions shown in, by doping p ⁺ impurity respective locations shown in 206, p ⁺ impurity regions 6 ₄ and n ^- a diode with a junction of the impurity region 4 is formed.

As described above, in the first and second embodiments, the junction of the p-type semiconductor and the n-type semiconductor is provided on the insulating layer,
An oxide film layer and a polysilicon layer are provided on the top of the junction, and a silicide layer is formed on the surface using the mask as a mask to form a diode element. There is no. Moreover, since the oxide film layer and the polysilicon layer on the junction can be formed at the time of forming the gate of the MOSFET, it is not necessary to newly provide a manufacturing process.

[0033] In the above embodiments p ^- impurity region 3 or n ^- shows the case where the impurity region 4 is not low resistance but, p ^- junction of the impurity region 3 and the n ⁺ impurity region 5 ₄ or n, ^- bonding portions of the impurity region 4 and the p ⁺ impurity region 6 ₄ is in a directly under the oxide film layer 8 and the polysilicon layer 7, if no resistance is reduced, p ^- one impurity regions 4 ^- impurity region 3 or n The part may have low resistance. That is, in the example of FIG. 1, to reduce the width of the p ⁺ impurity region 6 ₄ and 206, p ^- portion of the impurity region 3 p ⁺ impurity region 6
With ₄ have a structure are low resistance, also to narrow the width of the n ⁺ impurity region 5 ₄ and 205 in the example of FIG. 2, n
^- it may have a structure in which a part of the impurity regions 4 is lower resistance with n ⁺ impurity region 5 _4.

In the above embodiment, the potential of the polysilicon layer 7 is not fixed. However, a configuration may be used in which the potential is fixed or variable by connecting a metal wiring. With this configuration, the threshold voltage of the diode element is reduced. Can be adjusted.

Next, a third embodiment of the present invention will be described with reference to the drawings. 3A and 3B show a configuration example of a resistance element according to a third embodiment of the present invention. FIG. 3A is a plan view, and FIG.
It is sectional drawing of AB section of (a). In FIG, 1 is a silicon wafer, the back gate potential 28, 2 an insulating layer, 3 p ^- impurity region, 6 _4, 6 ₅ p ⁺ impurity region,
9 is a LOCOS layer, 7 is a polysilicon layer, 8 is an oxide film layer, 10 is a side wall, and 106 is a surface portion whose resistance has been reduced by silicidation or the like. 45, 46
Is a terminal of the resistance element, and 42 is a contact hole. Further 203 p at the time of manufacture ^- portion of doping impurities, 2
Reference numeral 06 indicates a portion to be doped with ap ⁺ impurity.

[0036] In the embodiment shown in FIG. 3, p ^- impurity region 3
Upper oxide film layer 8, to form the polysilicon layer 7, so to form a p ⁺ impurity region 6 _4, 6 ₅ on both sides,
Also p ⁺ impurity region 6 _4, 6 ₅ surface 106 and the polysilicon layer 7 is low resistance p ^- impurity region 3 is not low resistance of several hundred Ω about the resistance element can be realized.

The method of forming the structure shown in FIG. 3 is the same as the method described with reference to FIG. That is, a thin film silicon layer surrounded by the LOCOS layer 9 is formed on the
After doping the portion indicated by 03 with ap ⁻ impurity, the oxide film layer 8, the polysilicon layer 7 and the side wall 10 are formed, and then the portion indicated by 206 may be doped with ap ⁺ impurity.

FIG. 4 shows a configuration example of a resistance element according to a fourth embodiment of the present invention. FIG. 4A is a plan view, and FIG. 4B is a cross section taken along a line AB in FIG. FIG. In the figure, n 4 ^- impurity region 5 _4, 5 ₅ n ⁺ impurity region 204 is n at the time of manufacture ^- portion of doping impurities, 205 locations doping n ⁺ impurity during manufacturing, 105 low resistance The same reference numerals as those in FIG. 3 indicate the same parts.

[0039] In the embodiment shown in FIG. 4, n ^- impurity region 4
Upper oxide film layer 8, to form the polysilicon layer 7, so to form an n ⁺ impurity region 5 _4, 5 ₅ on both sides,
Also n ⁺ surface 105 and the polysilicon layer 7 of impurity regions 5 _4, 5 ₅ is low resistance n ^- impurity region 4 is not a low resistance of several hundred Ω about the resistance element can be realized. This forming method is the same as the method described with reference to FIG.
^- impurities, ^- n at positions shown in 205 in place of the impurity
Instead of the n ⁺ impurity, the portion indicated by 204 may be doped with the n ⁺ impurity.

As described above, in the third and fourth embodiments, a p-type or n-type semiconductor layer is provided on an insulating layer, and a polysilicon layer and an oxide film layer are provided on a part of an upper portion thereof. By using this as a mask to form a resistance element by forming a silicide layer on the surface, high resistance can be maintained. Moreover,
The polysilicon layer and oxide layer on the semiconductor layer are MOSFE
Since it is formed when the T gate is formed, it is not necessary to provide a new manufacturing process.

In the above embodiment, the potential of the polysilicon layer 7 is not fixed. However, a configuration may be employed in which the potential is fixed or variable by connecting a metal wiring, and the potential is accumulated in the oxide film 8 during operation. The effect of the charge can be eliminated.

Next, a buffer circuit to which the present invention is applied will be described with reference to FIG. In FIG. 5, a diode 33,
1 and 2, the resistor 29 has the structure described in FIG. 3 or 4, and the oxide film 8 of the diode element and the resistance element is used when forming the gate of the MOSFET.
If the polysilicon layer 7 is also formed, the SOI MOSF
Even in the case of ET and when the resistance of silicon / polysilicon is reduced, the withstand voltage against the high potential difference applied to the input / output terminal can be improved without changing the mask and the manufacturing process required for the conventional SOI MOSFET formation.

[0043]

As described above, according to the present invention, the insulator layer
A p-type or n-type impurity layer formed on
Part formed at the same time when the MOSFET gate is formed.
Recon oxide film layer, polysilicon layer and these silicon
Sizes formed on the side surfaces of the oxide film layer and polysilicon layer
With the silicon wall
Resistance of the passivation film layer, polysilicon layer and sidewall
Source and drain are low resistance
Integrated circuit composed of SOI MOSFETs
Mask a high-resistance, small-area resistive element inside the device.
There is an effect that can be realized without adding a manufacturing process .

[0044]

[Brief description of the drawings]

FIG. 1A is a plan view showing the configuration of a diode element according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view showing the configuration of the diode element according to the first embodiment of the present invention.

FIG. 2A is a plan view illustrating a configuration of a diode element according to a second embodiment of the present invention, and FIG. 2B is a cross-sectional view illustrating a configuration of the diode element according to the second embodiment of the present invention.

3A is a plan view showing a configuration of a resistance element according to a third embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a configuration of the resistance element according to the third embodiment of the present invention.

FIG. 4A is a plan view illustrating a configuration of a resistance element according to a fourth embodiment of the present invention, and FIG. 4B is a cross-sectional view illustrating the configuration of the resistance element according to the fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a buffer circuit constituted by a conventional SOI MOSFET.

6A is a plan view showing a configuration of a conventional diode element, and FIG. 6B is a cross-sectional view showing a configuration of a conventional diode element.

FIG. 7A is a plan view showing a configuration of a conventional resistance element,
(b) is a cross-sectional view showing a configuration of a conventional resistance element.

FIG. 8 is a circuit diagram illustrating an example of a buffer circuit configured by a bulk MOSFET.

9A is a cross-sectional view illustrating a structure of a bulk MOSFET, and FIG. 9B is a cross-sectional view illustrating a structure of an SOI MOSFT.

[Explanation of symbols]

1 Silicon wafer 2 insulator layer 3 p ^- impurity region 4 n ^- impurity region 5 ₁ to 5 ₅ n ⁺ impurity regions 6 ₁ to 6 ₅ p ⁺ impurity regions 7 a polysilicon layer 8 oxide film layer 9 LOCOS layer 10 sidewalls 28 Back gate potential

Claims (1)

(57) [Claims] 1. An insulator layer, a MOS field effect transistor formed on the insulator layer, a diode element ,
At least one input / output buffer circuit including a resistance element
In the semiconductor integrated circuit device including the diode elements, and having a junction of p-type semiconductor and the n-type semiconductor on the insulating layer, the resistive element, the first formed in the insulating layer upper
A second semiconductor layer having the same conductivity type as the first semiconductor layer;
And the p-type semiconductor
Low resistance inside the body layer, n-type semiconductor layer and first semiconductor layer
And the diode element and the resistance element further include the semiconductor.
The gate of the MOS field effect transistor is provided on the body layer.
Silicon oxide film layer, polysilicon formed at the same time as
Layer and the side of these silicon oxide and polysilicon layers
Shall have a sidewall formed on the surface part,
These silicon oxide film layer, polysilicon layer, side wall
The low-resistance layer is formed in a self-aligned manner using
The junction of the diode element and
The semiconductor integrated circuit device , wherein the low resistance layer is not formed on the second semiconductor layer of the resistance element .