JP2780289B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2780289B2 JP2780289B2 JP63290604A JP29060488A JP2780289B2 JP 2780289 B2 JP2780289 B2 JP 2780289B2 JP 63290604 A JP63290604 A JP 63290604A JP 29060488 A JP29060488 A JP 29060488A JP 2780289 B2 JP2780289 B2 JP 2780289B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- resistor
- power supply
- pair
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路上に構成する保護装置に関
する。Description: TECHNICAL FIELD The present invention relates to a protection device configured on a semiconductor integrated circuit.
本発明は、端子と正側電源間に接続される第１のダイ
オード、もしくは、端子と負側電源間に接続される第２
のダイオードを有し、さらに正側電源と負側電源間に寄
生する第３のダイオードをもつ保護装置において、前記
端子を正負側電源に接続された第１のダイオード、もし
くは第２のダイオードに接続した後、抵抗を介して、前
記抵抗と正側電源間に接続される第４のダイオード、も
しくは負側電源間に接続される第５のダイオードを有
し、前記抵抗と第４もしくは第５のダイオードの接続関
係をもった回路を、少なくとも１つ以上具備する事によ
り、静電気による破壊を防止したものである。The present invention relates to a first diode connected between a terminal and a positive power supply, or a second diode connected between a terminal and a negative power supply.
And a third diode parasitic between the positive power supply and the negative power supply, wherein the terminal is connected to the first diode or the second diode connected to the positive or negative power supply. After that, a fourth diode connected between the resistor and the positive power supply or a fifth diode connected between the negative power supply via a resistor is provided. By providing at least one or more circuits having a connection relation of diodes, destruction due to static electricity is prevented.
従来の保護装置は第３図に示す様に、端子と保護ダイ
オードの間に抵抗６を接続し、抵抗６の他の端と電源電
極との間にダイオード１、２を接続し、さらに抵抗７を
通じてMOS型電界効果トランジスタ（以降MOSFETと称
す）に入力される保護回路が一般的に知られている。ダ
イオード３は、上記ダイオードをつくる事で電源端子に
寄生するダイオードである。In the conventional protection device, as shown in FIG. 3, a resistor 6 is connected between a terminal and a protection diode, diodes 1 and 2 are connected between the other end of the resistor 6 and a power supply electrode, and a resistor 7 is connected. A protection circuit which is input to a MOS field effect transistor (hereinafter, referred to as a MOSFET) through a MOSFET is generally known. The diode 3 is a diode that is parasitic on the power supply terminal by forming the diode.
端子10に正の静電気が印加された場合、電荷はダイオ
ード１を順方向で通り、電源電極９へ抜けるか、さらに
ダイオード３を逆方向で通り、電源電極11へ抜ける。ま
た端子10に負の静電気が印加された場合、ダイオード２
を順方向で通り、電源電極11へ抜けるか、ダイオード３
を逆方向で通り、電源電極９へ抜ける。これによりMOSF
ETのゲート端子に達する静電気は弱まり、静電気による
ゲート膜破壊を防止した。When positive static electricity is applied to the terminal 10, the charge passes through the diode 1 in the forward direction to the power supply electrode 9, or further passes through the diode 3 in the reverse direction to the power supply electrode 11. When a negative static electricity is applied to the terminal 10, the diode 2
In the forward direction to the power supply electrode 11 or the diode 3
Through the power supply electrode 9 in the reverse direction. This allows MOSF
The static electricity reaching the gate terminal of the ET was weakened, preventing the gate film from being damaged by the static electricity.
しかし前述の従来技術では、半導体集積回路の微細
化、高速化がすすむなかで、MOSFETのゲート膜厚がうす
くなってくると、ゲート膜の静電気耐量が低下し、従来
技術だけではゲート膜を保護できなくなってしまう。そ
こで本発明はこの様な問題点を解決するもので、その目
的とするところは、静電気に強い入力保護装置を提供す
るところにある。However, with the conventional technology described above, as the gate thickness of the MOSFET becomes thinner as the semiconductor integrated circuit becomes finer and faster, the gate film's electrostatic withstand capability decreases and the conventional technology alone protects the gate film. I can no longer do it. The present invention solves such a problem, and an object of the present invention is to provide an input protection device that is resistant to static electricity.
本発明の半導体装置は、入力端子から入力した信号が
それぞれのゲートに供給される一対のＰチャンネルMOSF
ETとＮチャンネルMOSFETと前記一対のMOSFETを前記入力
端子に印可される静電気による破壊から保護するための
保護回路を備える半導体装置において、前記保護回路
が、前記入力端子に一端が接続された第１の抵抗と、前
記第１の抵抗の他端に一端が接続された第２の抵抗と、
アノードを前記第１の抵抗と第２の抵抗の接続点に接続
し、カソードを正側電源に接続した第１のダイオード
と、カソードを前記第１の抵抗と第２の抵抗の接続点に
接続し、アノードを負側電源に接続した第２のダイオー
ドと、アノードを前記一対のＰチャンネルMOSFETとＮチ
ャンネルMOSFETそれぞれのゲートに接続された前記第２
の抵抗の他端に接続し、カソードを前記正側電源に接続
した第３のダイオードと、カソードを前記一対のＰチャ
ンネルMOSFETとＮチャンネルMOSFETそれぞれのゲートに
接続された前記第２の抵抗の他端に接続し、アノードを
前記負側電源に接続した第４のダイオードと、前記第１
のダイオードあるいは第２のダイオードを作るための第
１のウエルと、前記一対のMOSFETのうちＰチャンネルMO
SFETあるいはＮチャンネルMOSFETいづれかのトランジス
タを作るために前記第１のウエルとは別に離間して設け
られた第２のウエルとを備え、前記第３のダイオードと
第４のダイオードは前記一対のMOSFETに隣接して設けら
れ、前記第２のウエルを用いて前記第３のダイオードあ
るいは第４のダイオードが形成されてなることを特徴と
する。According to the semiconductor device of the present invention, a pair of P-channel MOSFs in which a signal input from an input terminal is supplied to each gate is provided.
A semiconductor device comprising a protection circuit for protecting an ET, an N-channel MOSFET, and the pair of MOSFETs from damage caused by static electricity applied to the input terminal, wherein the protection circuit includes a first terminal having one end connected to the input terminal. A second resistor having one end connected to the other end of the first resistor,
An anode is connected to a connection point between the first and second resistors, a cathode is connected to a positive diode, and a cathode is connected to a connection point between the first and second resistors. A second diode having an anode connected to the negative power supply; and a second diode having an anode connected to the gate of each of the pair of P-channel MOSFET and N-channel MOSFET.
A third diode having a cathode connected to the positive power supply, and a second diode having a cathode connected to the gate of each of the pair of P-channel MOSFET and N-channel MOSFET. A fourth diode connected to the first terminal and having an anode connected to the negative power supply;
A first well for forming a second diode or a second diode, and a P-channel MO of the pair of MOSFETs.
A second well separately provided from the first well to form an SFET or N-channel MOSFET transistor, wherein the third diode and the fourth diode are connected to the pair of MOSFETs. The third diode or the fourth diode is provided adjacent to the second well and formed using the second well.
端子10に入った正の静電気は、ダイオード１を順方向
で通過し、電源電極９にぬけるか、さらにはダイオード
３を逆方向で通り、電源電極11に抜ける。但し端子に加
わった静電気は電荷移動経路のインピーダンスによって
は、瞬間的に抵抗６、７間の電位上昇をまねき、一部は
ダイオード３を逆方向で通過し、電源電極11へ抜けたり
する。瞬間的な高い電位変化の場合、ダイオード面積は
それほど電荷移動経路のインピーダンスにきかず、MOSF
ETのゲート膜にかかる電位をさげる効果はうすい。Positive static electricity that has entered the terminal 10 passes through the diode 1 in the forward direction and penetrates the power supply electrode 9, or passes through the diode 3 in the reverse direction and escapes to the power supply electrode 11. However, the static electricity applied to the terminal causes an instantaneous increase in the potential between the resistors 6 and 7 depending on the impedance of the charge transfer path, and part of the static electricity passes through the diode 3 in the reverse direction and escapes to the power supply electrode 11. In the case of a momentary high potential change, the diode area is not so much as the impedance of the charge transfer path and the MOSF
The effect of lowering the potential applied to the gate film of ET is weak.
従来技術であれば、ダイオードを通して電荷が移動
し、端子への印加電圧に対し電位はさがるものの、抵抗
６、７間の瞬間的な高い電位はそのままMOSFETの入力に
もかかり、ゲート膜破壊を引き起こす。ゲート膜厚が薄
くなるほどゲート膜の電圧耐量は低下し、ゲート膜破壊
を引き起こしやすくなる。In the prior art, the charge moves through the diode, and although the potential drops with respect to the voltage applied to the terminal, the instantaneous high potential between the resistors 6 and 7 is applied to the MOSFET input as it is, causing gate film breakdown. . As the gate film thickness decreases, the withstand voltage of the gate film decreases, and the gate film is likely to be destroyed.
本発明の構造によれば、抵抗６、７間に瞬間的にかか
った高い電位は、ダイオード４を電荷が順方向で通過
し、MOSFETのゲート膜にかかる電位は低下する。According to the structure of the present invention, the high potential instantaneously applied between the resistors 6 and 7 causes the electric charge to pass through the diode 4 in the forward direction, and the potential applied to the gate film of the MOSFET decreases.
従って多段に保護抵抗と保護ダイオードを分離する事
により、より薄いゲート膜を保護する事ができる。Therefore, by separating the protection resistor and the protection diode in multiple stages, a thinner gate film can be protected.
第１図は本発明の実施例における保護装置の等価回路
である。第２図は本発明の実施例における保護装置を半
導体装置上に実現したときのパターン図例である。この
パターン図例はＰ型基板半導体装置の例である。FIG. 1 is an equivalent circuit of a protection device according to an embodiment of the present invention. FIG. 2 is an example of a pattern diagram when the protection device according to the embodiment of the present invention is realized on a semiconductor device. This pattern diagram is an example of a P-type substrate semiconductor device.
以下本発明を第２図のパターン図例を用いて具体的に
説明する。尚第１図第２図に明記されている各素子の番
号は対応している。Hereinafter, the present invention will be specifically described with reference to an example of a pattern diagram shown in FIG. The numbers of the elements specified in FIGS. 1 and 2 correspond to each other.
Ｐ基板上にＰ型の濃い拡散領域15（以降Ｐ+拡散と称
す）と、Ｎ型の島Ｎウェル領域13がありＮウェル近辺に
Ｎ型の濃い拡散領域14（以降Ｎ+拡散と称す）が存在す
る。入力端子に接続された金属配線10はポリシリコン抵
抗６の一端に接続され、ポリシリコン抵抗６の他の端は
金属配線を通じＮウェルとＰ+拡散からなるダイオード
１、及びＰ基板とＮ+拡散からなるダイオード２に接続
され、ポリシリコン抵抗７の一端に接続される。さらに
ポリシリコン抵抗７の別の一端は、金属配線を通じＰ基
板とＮ+拡散からなるダイオード５、およびＮウェルと
Ｐ+拡散からなるダイオードに接続され、ポリシリコン
抵抗８の一端に接続される。さらにポリシリコン抵抗８
の一端はMOSFET12のゲート端子に接続される。A P-type deep diffusion region 15 (hereinafter referred to as P + diffusion) and an N-type island N-well region 13 are provided on the P substrate, and an N-type deep diffusion region 14 (hereinafter referred to as N + diffusion) near the N well. Exists. The metal wire 10 connected to the input terminal is connected to one end of the polysilicon resistor 6, and the other end of the polysilicon resistor 6 is connected to the diode 1 composed of an N well and P + diffusion, and a P substrate and N + diffusion through a metal wire. And connected to one end of a polysilicon resistor 7. Further, another end of the polysilicon resistor 7 is connected to a diode 5 formed of a P substrate and N + diffusion and a diode formed of an N well and P + diffusion through a metal wiring, and is connected to one end of the polysilicon resistor 8. In addition, polysilicon resistor 8
Is connected to the gate terminal of MOSFET12.
Ｎウェル13はＮ+拡散14を通じ正側電極９に電気的に
接続され、Ｐ基板はＰ+拡散15を通じ負側電極11に電気
的に接続される。ダイオード３は、Ｎ+拡散とＰ基板と
の間にできるダイオードである。N well 13 is electrically connected to positive electrode 9 through N + diffusion 14, and P substrate is electrically connected to negative electrode 11 through P + diffusion 15. The diode 3 is a diode formed between the N + diffusion and the P substrate.
端子10に正の静電気が加わると、ダイオード１を順方
向に電荷が通過し、正側電極９へ、さらにはダイオード
３を逆方向に電荷が通過し、負側電極11へ抜けていく。
これにより抵抗６、７間の電位は低下するが、静電気印
加時の瞬間はそれほど電位はさがらず、抵抗７を介して
次段へつたわる。ここでさらにダイオード４、３を介し
て電荷を抜き、MOSFETのゲート入力にかかる瞬間的な電
位を下げる。When positive static electricity is applied to the terminal 10, charges pass through the diode 1 in the forward direction, pass through the positive electrode 9, pass through the diode 3 in the reverse direction, and pass through the negative electrode 11.
As a result, the potential between the resistors 6 and 7 decreases, but at the moment when the static electricity is applied, the potential does not decrease so much, and the current passes through the resistor 7 to the next stage. Here, the electric charge is further removed through the diodes 4 and 3 to reduce the instantaneous potential applied to the gate input of the MOSFET.
同様に負の静電気が加わると、ダイオード２、３及び
ダイオード５、３によりMOSFETのゲート入力にかかる瞬
間的な電位をさげる事ができる。Similarly, when negative static electricity is applied, the instantaneous potential applied to the gate input of the MOSFET can be reduced by the diodes 2, 3 and the diodes 5, 3.
MOSFETのゲート膜破壊電圧は、ゲート膜厚が薄いほど
低下し、本発明の保護装置を複数段構成する事により、
MOSFETのゲート入力に印加される瞬間的な電位をさげる
事ができ、MOSFETを静電気から保護する事ができる。The gate film breakdown voltage of the MOSFET decreases as the gate film thickness decreases, and by configuring the protection device of the present invention in multiple stages,
The instantaneous potential applied to the gate input of the MOSFET can be reduced, and the MOSFET can be protected from static electricity.
第１図に示す本発明の実施例は抵抗７の後に保護ダイ
オード４、５がそれぞれ正負側電極に接続されている
が、保護ダイオード１、２の電荷吸収経路のインピーダ
ンスによっては、ダイオード４もしくはダイオード５を
省略する事もできる。In the embodiment of the present invention shown in FIG. 1, the protection diodes 4 and 5 are respectively connected to the positive and negative electrodes after the resistor 7, but depending on the impedance of the charge absorption path of the protection diodes 1 and 2, the diode 4 or the diode may be used. 5 can be omitted.
第２図に示す本発明の実施例は、Ｐ型基板半導体装置
の例であるが、Ｎ型基板半導体装置でも、Ｐ型、Ｎ型の
関係を逆にする事により同様の説明が成り立つ。Although the embodiment of the present invention shown in FIG. 2 is an example of a P-type substrate semiconductor device, the same description can be applied to an N-type substrate semiconductor device by reversing the relationship between P-type and N-type.
第５図は本発明の別の実施例である。入力端子に接続
された金属配線10から、ダイオード１、２及びポリシリ
コン抵抗７までの接続関係は第２図で説明した内容と同
じである。FIG. 5 shows another embodiment of the present invention. The connection relationship from the metal wiring 10 connected to the input terminal to the diodes 1, 2 and the polysilicon resistor 7 is the same as that described in FIG.
保護ダイオード４、５は通常の論理ゲートセルのセル
列の中に組み込まれ、ウェルは論理ゲートセルと共有す
る。The protection diodes 4 and 5 are incorporated in a row of normal logic gate cells, and the well is shared with the logic gate cells.
ポリシリコン抵抗７の別の一端は金属配線を通じ上記
保護ダイオード４、５に接続され、MOSFET12のゲート端
子に接続される。第５図に示す実施例では、論理ゲート
セル列の内に静電気保護ダイオード４、５が設けられる
ため、その配置は自由に選択でき、本発明の保護装置を
半導体装置上に容易に実現できる。Another end of the polysilicon resistor 7 is connected to the protection diodes 4 and 5 through metal wiring, and is connected to the gate terminal of the MOSFET 12. In the embodiment shown in FIG. 5, since the static electricity protection diodes 4 and 5 are provided in the logic gate cell row, the arrangement can be freely selected, and the protection device of the present invention can be easily realized on a semiconductor device.
以上述べた本発明によれば、端子は正負電極にそれぞ
れ接続された第１及び第２の保護ダイオードの一方に接
続され、さらに保護抵抗に接続され、前記保護抵抗の別
の端子は、正負電極にそれぞれ接続された第４及び第５
の保護ダイオードの一方に接続される構造をとる事によ
り、MOS型半導体装置のゲート膜破壊耐量を大幅にアッ
プさせるというすぐれた効果を有する。According to the present invention described above, the terminal is connected to one of the first and second protection diodes connected to the positive and negative electrodes, respectively, and further connected to the protection resistor, and another terminal of the protection resistor is connected to the positive and negative electrodes. The fourth and the fifth connected respectively to
By adopting a structure connected to one of the protection diodes, there is an excellent effect that the gate film breakdown resistance of the MOS type semiconductor device is greatly increased.
また第５図に示す実施例によれば、正負電極にそれぞ
れ接続された第４及び第５の保護ダイオードは、通常の
ロジックセル内に作成する事ができ、本発明を半導体装
置上に実現する上で、パターンレイアウトの自由度が増
し、入出力端子周辺のパターン的な集中がなくなる。According to the embodiment shown in FIG. 5, the fourth and fifth protection diodes connected to the positive and negative electrodes, respectively, can be formed in a normal logic cell, and the present invention is realized on a semiconductor device. Above, the degree of freedom of the pattern layout is increased, and the pattern concentration around the input / output terminals is eliminated.
これにより半導体装置上の無駄なスペースが減り半導
体装置のチップサイズを小さくできるという効果も有す
る。This also has the effect that wasteful space on the semiconductor device is reduced and the chip size of the semiconductor device can be reduced.
第１図は本発明の保護装置の一実施例を示す等価回路
図。 第２図は本発明の一実施例における半導体装置上のパタ
ーン図。 第３図は従来の保護装置を示す等価回路図。 第４図は従来の保護装置における半導体装置上のパター
ン図。 第５図は本発明の一実施例における半導体装置上のパタ
ーン図。 １、４……正側電極との間の保護ダイオード ２、５……負側電極との間の保護ダイオード ３……正負電極間の保護ダイオード ６、７、８……保護抵抗 ９……正側電極 10……端子 11……負側電極 12……MOSFET 13……Ｎウェル 14……Ｎ+拡散 15……Ｐ+拡散 16……ポリシリコン−ALコンタクト 17……拡散−ALコンタクトFIG. 1 is an equivalent circuit diagram showing an embodiment of the protection device of the present invention. FIG. 2 is a pattern diagram on a semiconductor device in one embodiment of the present invention. FIG. 3 is an equivalent circuit diagram showing a conventional protection device. FIG. 4 is a pattern diagram on a semiconductor device in a conventional protection device. FIG. 5 is a pattern diagram on a semiconductor device according to one embodiment of the present invention. 1, 4, protection diode between positive side electrode 2, 5, protection diode between negative side electrode 3, protection diode between positive and negative electrode 6, 7, 8 ... protection resistor 9, positive Side electrode 10 Terminal 11 Negative electrode 12 MOSFET 13 N well 14 N + diffusion 15 P + diffusion 16 Polysilicon-AL contact 17 Diffusion-AL contact
Claims (1)
ートに供給される一対のＰチャンネルMOSFETとＮチャン
ネルMOSFETと前記一対のMOSFETを前記入力端子に印可さ
れる静電気による破壊から保護するための保護回路を備
える半導体装置において、 前記保護回路が、 前記入力端子に一端が接続された第１の抵抗と、 前記第１の抵抗の他端に一端が接続された第２の抵抗
と、 アノードを前記第１の抵抗と第２の抵抗の接続点に接続
し、カソードを正側電源に接続した第１のダイオード
と、 カソードを前記第１の抵抗と第２の抵抗の接続点に接続
し、アノードを負側電源に接続した第２のダイオード
と、 アノードを前記一対のＰチャンネルMOSFETとＮチャンネ
ルMOSFETそれぞれのゲートに接続された前記第２の抵抗
の他端に接続し、カソードを前記正側電源に接続した第
３のダイオードと、 カソードを前記一対のＰチャンネルMOSFETとＮチャンネ
ルMOSFETそれぞれのゲートに接続された前記第２の抵抗
の他端に接続し、アノードを前記負側電源に接続した第
４のダイオードと、 前記第１のダイオードあるいは第２のダイオードを作る
ための第１のウエルと、前記一対のMOSFETのうちＰチャ
ンネルMOSFETあるいはＮチャンネルMOSFETいづれかのト
ランジスタを作るために前記第１のウエルとは別に離間
して設けられた第２のウエルとを備え、 前記第３のダイオードと第４のダイオードは前記一対の
MOSFETに隣接して設けられ、前記第２のウエルを用いて
前記第３のダイオードあるいは第４のダイオードが形成
されてなることを特徴とする半導体装置。1. A protection circuit for protecting a pair of P-channel MOSFET, N-channel MOSFET, and a pair of MOSFETs from a static electricity applied to the input terminal, wherein a pair of P-channel MOSFETs and N-channel MOSFETs are supplied to respective gates with a signal input from an input terminal. In the semiconductor device including a circuit, the protection circuit includes: a first resistor having one end connected to the input terminal; a second resistor having one end connected to the other end of the first resistor; A first diode connected to a connection point of the first resistance and the second resistance, a cathode connected to the positive power supply, a cathode connected to a connection point of the first resistance and the second resistance, and an anode Is connected to a negative power supply, an anode is connected to the other end of the second resistor connected to the gate of each of the pair of P-channel MOSFET and N-channel MOSFET, and a cathode is connected to the positive electrode. A third diode connected to a power supply, a cathode connected to the other end of the second resistor connected to the gate of each of the pair of P-channel MOSFETs and N-channel MOSFET, and an anode connected to the negative power supply A fourth diode; a first well for forming the first diode or the second diode; and a first well for forming a P-channel MOSFET or an N-channel MOSFET of the pair of MOSFETs. A second well provided separately from the well, wherein the third diode and the fourth diode are arranged in a pair.
A semiconductor device provided adjacent to a MOSFET, wherein the third diode or the fourth diode is formed using the second well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290604A JP2780289B2 (en) | 1988-11-17 | 1988-11-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290604A JP2780289B2 (en) | 1988-11-17 | 1988-11-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02135774A JPH02135774A (en) | 1990-05-24 |
| JP2780289B2 true JP2780289B2 (en) | 1998-07-30 |
Family
ID=17758154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63290604A Expired - Fee Related JP2780289B2 (en) | 1988-11-17 | 1988-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780289B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293836A (en) * | 1996-04-25 | 1997-11-11 | Rohm Co Ltd | Semiconductor device |
| JP2003072076A (en) * | 2001-08-31 | 2003-03-12 | Canon Inc | Recording head and recorder using the same |
| BRPI1011202A2 (en) * | 2009-06-09 | 2016-03-15 | Sharp Kk | semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59111356A (en) * | 1982-12-17 | 1984-06-27 | Nec Corp | Semiconductor device |
| JPS60257576A (en) * | 1984-06-04 | 1985-12-19 | Mitsubishi Electric Corp | Protective circuit for input to mis type field-effect semiconductor device |
| JPS6356957A (en) * | 1986-08-28 | 1988-03-11 | Nec Corp | Protection circuit |
| JPS6380563A (en) * | 1986-09-24 | 1988-04-11 | Nec Corp | Input protective device |
| JPS6395667A (en) * | 1986-10-09 | 1988-04-26 | Nec Corp | Input protective device |
-
1988
- 1988-11-17 JP JP63290604A patent/JP2780289B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59111356A (en) * | 1982-12-17 | 1984-06-27 | Nec Corp | Semiconductor device |
| JPS60257576A (en) * | 1984-06-04 | 1985-12-19 | Mitsubishi Electric Corp | Protective circuit for input to mis type field-effect semiconductor device |
| JPS6356957A (en) * | 1986-08-28 | 1988-03-11 | Nec Corp | Protection circuit |
| JPS6380563A (en) * | 1986-09-24 | 1988-04-11 | Nec Corp | Input protective device |
| JPS6395667A (en) * | 1986-10-09 | 1988-04-26 | Nec Corp | Input protective device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02135774A (en) | 1990-05-24 |
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