JPH0766405A - Semiconductor protection device - Google Patents

Abstract

PURPOSE:To prevent the gate insulation film of a MOSFET from being broken down by surge. CONSTITUTION:It has a first means 104 for detecting the potential near a drain region 103 of a MOSFET 110 in a substrate region 100 wherein the region 103 is connected to the input or output terminal 14 of a semiconductor device to be protected, and second means 115 for feedback of the variation of the detected potential to a gate electrode 106 of the FET 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection device for preventing a semiconductor device from being destroyed by an electrostatic surge (hereinafter simply referred to as surge).

[0002]

2. Description of the Related Art As a conventional semiconductor protection device, there is one shown in FIGS. 13 and 14, for example. FIG. 13 shows a CMOS that constitutes the output protection device. On the main surface of the N-type substrate 1, a P-type well 2, P ⁺ -type regions 10, 11 and N
^{A +} type region 12 is formed. Two P ⁺ type regions 10
A gate electrode 13 is formed on the main surface of the N-type substrate 1 between the gate electrodes 11 and 11 with a gate oxide film 8 interposed therebetween. P-type well 2
N ⁺ type regions 6 and 7 and a P ⁺ type region 5 are formed on the main surface of. A gate electrode 9 is formed on the main surface of the P-type well 2 between the two N ⁺ type regions 6 and 7 with a gate oxide film 8 interposed therebetween. A protective film 4 is formed on the main surfaces of the N-type substrate 1 and the P-type well 2 with a field oxide film 3 interposed therebetween.

FIG. 14 shows an equivalent circuit of the preceding CMOS portion which is the above-mentioned output protection device and protected semiconductor device. A Pch MOSFET 20 is formed using the P ⁺ type region 11 as a source region and the P ⁺ type region 10 as a drain region, and the gate electrode 13 on the gate oxide film 8 and the N ⁺ type region 12 as a substrate contact. Further, a PNP type Tr 22 having the P ⁺ type region 10 as a collector, the N type substrate 1 as a base, and the P ⁺ type region 11 as an emitter is formed.
A diode 24 having the ⁺ type region 10 as an anode and the N type substrate 1 as a cathode is formed. On the other hand, P-type well 2
In the inside, the N ⁺ type region 7 is used as a drain region, the N ⁺ type region 6 is used as a source region, and the gate electrode 9 on the gate oxide film 8 and the P ⁺ type region 5 are further used as well contacts to form Nc.
The hMOSFET 21 is formed. Further, an NPN type Tr 23 having the N ⁺ type region 7 as a collector, the P type well 2 as a base, and the N ⁺ type region 6 as an emitter is formed, and the diode 25 having the N ⁺ type region 7 as a cathode and the P type well 2 as an anode 25 is formed. Are formed. Both MOSFETs 20, 21
The gate electrode of the CMO which is the protected semiconductor device in the previous stage.
It is connected to the drain of S. Nch MOSFET2
The source region 1, the emitter of the NPN type Tr 23 and the anode of the diode 25 are connected to the Vss (low potential) terminal. Source region of Pch MOSFET 20, PN
The emitter of the P-type Tr 22 and the cathode of the diode 24 are connected to the Vdd (high potential) terminal. Also Nch
Drain region of MOSFET 21 and Pch MOSFET
20 drain region, collector of NPN type Tr23 and P
The collector of the NP type Tr 22, the cathode of the diode 25 and the anode of the diode 24 are connected to the output terminal 14. The resistor 60 is a CMOS gate protection resistor that constitutes an output protection device.

CMOS of protected semiconductor device (internal circuit)
The part is almost the same as the above, and first, PchMO
Between the source and drain of SFET50, PNP type Tr5
2 and the diode 54 are connected in parallel. NchM
NPN type Tr is provided between the source and drain of the OSFET 51.
53 and the diode 55 are connected in parallel. Also V
Nch MOSFET 51 is provided between the dd terminal and the Vss terminal.
Is connected to an NPN type vertical Tr 56 having a source region as an emitter, a P type well as a base, and an N type substrate as a collector, and a diode 57 including a junction between the P type well and the N type substrate.

Next, the operation of the above semiconductor protection device will be described.

(A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; the diode 25 breaks down and the NPN Tr 23 turns on. Further, the diode 24 is forward-biased and the following three current paths occur. (i) The diodes 54 and 55 break down. (ii) NPN due to breakdown of diodes 54 and 55
The mold Tr53 turns on. (iii) The diode 57 breaks down and the NPN type Tr 56 turns on.
Therefore, the surge current flows from the output terminal 14 to the Vss terminal.

(B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal; the diode 25 is forward biased. Further, the diodes 54 and 55 and the diode 57 are forward biased, the diode 24 breaks down, and the PNP type Tr 22 is turned on. Therefore, the surge current flows from the Vss terminal to the output terminal 14.

(C) When the polarity of the surge is positive at the output terminal 14 with respect to the Vdd terminal; the diode 24 is forward biased. In addition, the diode 25 breaks down and the NPN type Tr
23 turns on and diodes 54 and 55 and diode 57 are forward biased. Therefore, the surge current flows from the output terminal 14 to the Vdd terminal.

(D) When the polarity of the surge is negative at the output terminal with respect to the Vdd terminal; the diode 24 breaks down and the PNP type Tr 22 turns on. Further, the diode 25 is forward-biased, and the following three types of current paths occur. (i) The diodes 54 and 55 break down. (ii) PNP due to breakdown of diodes 54 and 55
The type Tr 52 and the NPN type Tr 53 are turned on. (ii
i) The diode 57 breaks down and NPN type Tr5
6 turns on. Therefore, the surge current flows from the Vdd terminal to the output terminal 14.

[0010]

However, the conventional semiconductor protection device has the following problems. (A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; the potential of the drain of the NchMOSFET 21 becomes high. On the other hand, Nch MOSFET2
Since the gate potential of 1 is clamped by the breakdown potential of the diode 55, it is sufficiently lower than the surge voltage. Therefore NchM
The potential difference between the drain and gate of the OSFET 21 increases, and the gate oxide film is destroyed. (B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal; N
The drain potential of the chMOSFET 21 becomes low. On the other hand, the gate potential of the Nch MOSFET 21 has only a voltage drop of about the forward bias voltage of the diode 55 from the Vss terminal potential. Therefore, the potential difference between the drain and gate of the Nch MOSFET 21 becomes large, and the gate oxide film is destroyed. (C) When the polarity of the surge is positive at the output terminal 14 with respect to the Vdd terminal; the drain potential of the PchMOSFET 20 becomes high. On the other hand, PchMOSFET2
The gate potential of 0 rises only about the forward bias voltage of the diode 54. Therefore, the potential difference between the drain and gate of the Pch MOSFET 20 becomes large, and the gate oxide film is destroyed. (D) When the polarity of the surge is negative at the output terminal 14 with respect to the Vdd terminal; PchMOSFET 20
Drain voltage is low. On the other hand, Pch MOSFET
The gate potential of 20 is from the potential of the Vdd terminal to the diode 5
It is clamped at a voltage of about the value obtained by subtracting the breakdown voltage of 4.
Therefore, the potential difference between the drain and gate of the Pch MOSFET 20 becomes large, and the gate oxide film is destroyed.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a semiconductor protection device capable of preventing the gate insulating film of the MOSFET from being destroyed by a surge.

[0012]

In order to solve the above-mentioned problems, the present invention firstly proposes a MOS having a drain region connected to either an input terminal or an output terminal of a protected semiconductor device.
In a semiconductor protection device having a FET, the MOSF
First means for detecting the potential of the portion in the vicinity of the drain region in the substrate region where ET is formed, and the variation of the potential detected by the first means is fed back to the gate electrode of the MOSFET to obtain the gate. The gist is to have a second means for relaxing an electric field between the electrode and the drain region.

Secondly, in the first structure, the first means is a high-concentration region which is formed in the vicinity of the drain region and has the same conductivity type as the substrate region, and the second means is the high-concentration region. The gist is that it is a capacitor that connects a region and the gate electrode.

Thirdly, in the first structure, the first means is a high-concentration region which is formed in the vicinity of the drain region and has the same conductivity type as the substrate region, and the second means is the high-concentration region. The gist is that the diode is connected in the forward direction from the region to the gate electrode.

Fourth, the drain region is connected to either the input terminal or the output terminal of the protected semiconductor device.
In a semiconductor protection device having an OSFET, the first
Means for detecting the potential of the portion in the vicinity of the drain region in the first substrate region in which the second MOSFET is formed, and the fluctuation of the potential detected by the first means is applied to the gate of the first MOSFET. A second means for feeding back to the electrode to relax an electric field between the gate electrode and the drain area; and a variation in the potential detected by the first means to the source area of the first MOSFET to be fed back to the source area. It is a gist to have a third means for relaxing an electric field between the gate electrode and the source region.

Fifth, in the above-mentioned fourth structure, the first means is a first high-concentration region which is formed in the vicinity of the drain region and has the same conductivity type as the first substrate region, and the second region. Means is either a first capacitor connecting the first high-concentration region and the gate electrode or a first diode forwardly connected from the first high-concentration region to the gate electrode. The third means includes a second capacitor connecting the first high-concentration region and the source region, or a second diode connected in a forward direction from the first high-concentration region to the source region. And a low-concentration region of reverse conductivity type to the first substrate region is formed on the main surface of the first substrate region, the source region is provided at one end of the low-concentration region, and the other end is provided at the other end. A second high concentration region of the same conductivity type as the source region is provided. A third high-concentration region of the same conductivity type as the first substrate region is provided between the source region and the second high-concentration region, and the second high-concentration region and the third high-concentration region are connected to each other. The gist is that the first substrate region is connected to either a high-potential terminal that gives a high potential or a low-potential terminal that gives a low potential.

Sixthly, in the fourth structure, the first means is a high-concentration region formed in the vicinity of the drain region of the first MOSFET and of the same conductivity type as the first substrate region. The second means is either a capacitor that connects the high-concentration region and the gate electrode of the first MOSFET, or a diode that is connected in the forward direction from the high-concentration region to the gate electrode of the first MOSFET. The third means includes a second M having the same polarity as the first MOSFET in the second substrate region of the same conductivity type as the first substrate region.
OSFET is formed, the high concentration region is connected to the gate electrode of the second MOSFET through an inverter, and the drain region of the second MOSFET is connected to the first MOS.
The second MOSFET connected to the source region of the FET
And connecting the source region and the second substrate region to either a high potential terminal that gives a high potential or a low potential terminal that gives a low potential to the first substrate region. To do.

[0018]

In the above structure, firstly, when a surge is applied to the drain region of the MOSFET, the fluctuation of the potential in the vicinity of the drain region in the substrate region is fed back to the gate electrode, and the potential difference between the gate and the drain is reduced. Therefore, the breakdown of the gate insulating film is prevented.

Secondly, the feedback means for the potential fluctuation can be better achieved by specifically using a capacitor as the second means for feedback. At the same time, the ease of forming the feedback means on the semiconductor substrate can be obtained.

Thirdly, the second means for feedback is specifically a diode, and the feedback action of the potential fluctuation is performed by the forward direction or the breakdown characteristic of the diode according to the polarity of the surge. By setting the breakdown voltage to be lower than the breakdown voltage of the gate insulating film, the breakdown of the gate insulating film can be prevented. Further, similar to the above, the ease of forming the feedback means on the semiconductor substrate can be obtained.

Fourthly, in addition to the second means for feeding back the fluctuation of the potential in the vicinity of the drain region to the gate electrode, the third means for feeding back the fluctuation of the potential to the source region is provided. -The potential difference between the sources is also reduced, and the breakdown of the gate insulating film is prevented more reliably.

Fifth, specifically, the third means is
Similar to the second means, by using a capacitor or a diode, the feedback action of potential fluctuation is appropriately achieved. When a surge is applied to the drain region, the potentials of the first substrate region and the reverse conductivity type low concentration region fluctuate through the source region, and the potential between the low concentration region and the first substrate region and the low concentration region is opposite. Each junction between the conductive type third high-concentration regions is reverse-biased, and the neutral region inside the low-concentration region is narrowed. As a result, the emitter resistance of the parasitic bipolar transistor formed in the source region, drain region, etc. of the MOSFET increases, the surge current decreases, and the destruction of the MOSFET is prevented more reliably.

Sixth, when a surge of a certain polarity is applied to the drain region of the first MOSFET, the second MOS
The FET is turned off and the source region of the first MOSFET becomes floating. As a result, the first MOSFE
The parasitic bipolar transistor formed in the source region, drain region, etc. of T is turned off, latch-up is prevented from occurring, and destruction of the first MOSFET is prevented more reliably.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are views showing a first embodiment of the present invention. FIG. 1 is a diagram showing only the NchMOSFET portion of the CMOS constituting the output protection device, and FIG. 2 shows an equivalent circuit of an embodiment including this NchMOSFET. Note that, in FIG. 2, the CMOS portion which is the protected semiconductor device (internal circuit) in the preceding stage is the same as in FIG.
Since the configuration is the same as the above, each element is denoted by the same reference numeral as the above, and duplicate description is omitted.

First, the structure of the output protection device will be described with reference to FIGS. The P-type well 100 is formed on the main surface of the N-type substrate 1.
Are formed. A P ⁺ type region 101 and two N ⁺ type regions 102 and 103 are formed on the main surface of the P type well 100. In addition, the P-type well 10 near the N ⁺ -type region 103
A P ⁺ type region 104 is formed on the 0 main surface. A gate electrode 106 is formed on the main surface of the P-type well 100 between the two N ⁺ -type regions 102 and 103 via a gate oxide film 105.
Are formed. On the other hand, an electrode 108 is formed on the main surface of the P ⁺ type region 104 via a dielectric 107.

The P ⁺ type region 101 and the N ⁺ type region 102 are V
The N ⁺ type region 103 is connected to the ss terminal and the N ⁺ type region 103 is connected to the output terminal 14
And the drain region of the Pch MOSFET 20. The gate electrode 106 is connected to the drain of the CMOS in the previous stage and the gate electrode of the Pch MOSFET 20, and the electrode 108 is connected to the gate electrode 106.

The N ⁺ type region 102 is used as a source region and the N ⁺ type region 103 is used as a drain region.
Nch MOSFET 1 by the gate electrode 106 on 05
10 are formed. The P-type well 100 is
Substrate region for hMOSFET 110, and P ⁺
The mold region 104 forms a first means for detecting the potential in the vicinity of the drain region 103 in this substrate region. N ⁺ type region 102 is an emitter, P type well 100 is a base, and N ⁺ type region 103 is a collector N
A diode 1 in which a PN type Tr 113 is formed and whose N ⁺ type region 103 is a cathode and whose P type well 100 is an anode
11 is formed. P ⁺ type region 104, dielectric 10
7 and the electrode 108 form a capacitor 115,
With this capacitor 115, the P ⁺ -type region 104, which is the first means, causes the gate electrode 10 of the Nch MOSFET 110 to move.
Connected to 6. N ⁺ type region 103 and P ⁺ type region 1
The resistor 112 is formed inside the P-type well 100 between 01 and 01, and the resistor 114 is formed inside the P-type well 100 between the N ⁺ type region 103 and the P ⁺ type region 104.

Next, the operation of the output protection device configured as described above will be described.

(A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; the diode 111 breaks down and the NPN type Tr 113 turns on. Further, the diode 24 is forward biased and the diode 57 breaks down, so that the NPN type Tr 56 is turned on. Therefore, the surge current flows from the output terminal 14 to the Vss terminal. Here, the protective effect of the gate oxide film 105 according to this embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing a portion related to charging / discharging of the gate-drain capacitor 120 of the Nch MOSFET 110 in the equivalent circuit of FIG. 121 is a diode 55 and NPN type Tr53
Is an impedance element. The potential on the output terminal 14 side of the capacitor 120 rises due to the application of the surge.
Since the value of the resistor 114 is small, the potential of the capacitor 115 on the diode 111 side rapidly rises to surge voltage-breakdown voltage of diode 111 (1). The potential on the other end side of the capacitor 120 also rises to a value determined by the parallel connection of the capacitors 120 and 115. From the above, the capacitor 12
0, that is, the potential difference between the gate and drain of the Nch MOSFET 110 becomes smaller than that in the conventional example. After that, the charging of the capacitors 115 and 120 starts via the resistor 60 and the impedance element 121. Here, it is known that in short-time high-voltage stress such as electrostatic surge, the oxide film is destroyed when the charge in the oxide film reaches a certain amount (for example, Philips Journal of Research Vol.
40 No.3 1985 P.144). Therefore, the presence of the capacitor 115 suppresses the potential decrease on the resistor 60 side of the capacitor 120. That is, the potential difference in the gate oxide film 105 is reduced and the charge injection into the capacitor 120 is suppressed. As a result, the Nch MOSFET 11 due to the surge
Zero destruction is less likely to occur.

(B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal; the diode 111 is forward biased, the diodes 54, 55 and 57 are forward biased, and the diode 24 breaks down. Therefore, the surge current flows from the Vss terminal to the output terminal 14. Here, the protective effect of the surge oxide film 105 will be described with reference to FIG. Output terminal 14 of capacitor 120 when surge is applied
Side potential drops. Further, since the diode 111 is forward-biased, the potential of the capacitor 115 on the diode 111 side also rapidly decreases to (surge voltage) − (forward bias voltage of diode 111≈surge voltage) (2). The potential at the other end of the capacitor 120 also drops to a value determined by the parallel connection of the capacitors 120 and 115. Therefore, the potential difference in the capacitor 120 becomes smaller than that in the conventional example. After that, resistance 6
Capacitor 11 via 0 and impedance element 121
Charging of 5 and 120 begins. Since there is the capacitor 115 as in the case of (A), the capacitor 120
The increase in potential difference and charge injection are suppressed. As a result, the breakdown of the Nch MOSFET 110 due to the surge is less likely to occur. In this embodiment, the Nch MOSFET 110 is
However, by using the same structure for the Pch MOSFET 20, the output terminal 14 and Vd
Regarding the surge applied between the d terminals, PchMOSFE
The gate oxide film of T20 can be protected. Further, since the capacitor 115 is not directly connected to the output terminal 14, the surge does not damage the capacitor 115. Since the capacitor 115 is formed on the main surface of the P ⁺ -type region 104, the area of the protection circuit according to the present embodiment is increased only by the area of the P ⁺ -type region 104, and the integration degree of the protected semiconductor device is greatly impaired. There is no such thing.

FIGS. 4 to 6 show a second embodiment of the present invention. FIG. 4 shows N of the CMOS constituting the output protection device.
Only the chMOSFET portion is shown, and FIG. 5 shows an equivalent circuit thereof. Explaining the configuration, in the present embodiment, unlike the first embodiment, the dielectric and electrode are not provided, and the P ⁺ type semiconductor region 201 is sandwiched on the field oxide film 3 so as to sandwich the P ⁺ type semiconductor region. 200 and N ⁺ type semiconductor region 2
02 is formed. The P ⁺ type semiconductor region 200 is P ⁺
The N ⁺ type semiconductor region 202 is connected to the mold region 104, and the N ⁺ type semiconductor region 202 is connected to the gate electrode 106. The other structure is similar to that of the first embodiment. In the present embodiment, instead of the capacitor 115 in FIG. 2, the P ⁺ semiconductor region 200, the P-type semiconductor region 201 and the N ⁺ -type semiconductor region 2 are used.
A diode 203 composed of 02 is a resistor 114 and NchM.
It is connected to the gate electrode 106 of the OSFET 110.

Next, the operation of the output protection device configured as described above will be described.

(A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; the surge current flows from the output terminal 14 to the Vss terminal in the same manner as in the first embodiment (A). Here, the protective effect of the gate oxide film 105 according to this embodiment will be described with reference to FIG. FIG. 6 shows a portion related to charging / discharging of the gate-drain capacitor 120 of the Nch MOSFET 110 in the equivalent circuit of the present embodiment. The potential on the output terminal 14 side of the capacitor 120 rises due to the application of the surge. Since the value of the resistor 114 is small, the anode potential of the diode 203 also rapidly rises to surge voltage-breakdown voltage of the diode 111 (3). Therefore, the cathode potential of the diode 203, that is, the potential on the resistor 60 side of the capacitor 120 is
The anode potential of the diode 203-the forward bias voltage of the diode 203 ≈ the anode potential of the diode 203 (4). Therefore, the potential difference applied to the capacitor 120 immediately after the application of the surge is the surge voltage-the potential on the side of the resistor 60 of the capacitor 120 = surge voltage- (4) formula ≈ surge voltage- (3) formula = breakdown voltage of the diode 111 (5) And is sufficiently lower than the dielectric breakdown voltage of the capacitor 120. After that, the resistor 60 and the impedance element 12
A current flows through one portion toward the Vss terminal. However, due to the presence of the diode 203, the potential of the capacitor 120 on the side of the resistor 60 is still clamped to the value of the equation (4), that is, the anode potential of the diode 203-the forward bias voltage of the diode 203. Therefore, the capacitor 12
The potential difference of 0 remains the value of the equation (5), that is, the breakdown voltage of the diode 111, and the high voltage is not applied to the capacitor 120. As a result, NchM due to surge
The destruction of the OSFET 110 is prevented.

(B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal; the surge current flows from the Vss terminal to the output terminal 14 as in the first embodiment (B). Here, the protective effect of the gate oxide film 105 will be described with reference to FIG. The potential on the output terminal 14 side of the capacitor 120 decreases due to the application of the surge. Since the diode 111 is forward-biased, the anode potential of the diode 203 rapidly drops to surge voltage-forward bias voltage of diode 111≈surge voltage (<0) (6). If the potential difference in the diode 203 becomes larger than its breakdown voltage, the diode 203 will breakdown. Therefore, the cathode potential of the diode 203, that is, the potential on the side of the resistor 60 of the capacitor 120, can be calculated by using equation (6) using the anode potential of the diode 203. + Breakdown voltage of diode 203 = surge voltage + breakdown voltage of diode 203 (<0) (7) Therefore, the potential difference of the capacitor 120 immediately after the application of the surge becomes (surge voltage + breakdown voltage of the diode 203) −surge voltage = breakdown voltage of the diode 203 (8) using the equation (7). After that, a part of the surge current flows from the Vss terminal to the diode 203 via the impedance element 121 and the resistor 60. However, due to the breakdown of the diode 203, the potential difference of the capacitor 120 remains clamped to the breakdown voltage of the diode 203 (9). As a result, if the breakdown voltage of the diode 203 is made lower than the dielectric breakdown voltage of the capacitor 120, the Nch MOSFET 110 due to the surge is generated.
Will be less likely to be destroyed. Further, the diode 203 is not directly connected to the output terminal 14, and the diode 20
Since the magnitude of the surge current flowing through 3 is limited by the impedance element 121 and the resistor 60, the diode 203 is not destroyed by the surge. Although only the NchMOSFET 110 has been described in the present embodiment, the PchMOSFET having the same structure can protect the gate oxide film of the PchMOSFET against a surge applied between the output terminal 14 and the Vdd terminal. In addition, the diodes 111 and 20
3 is a Zener diode structure, and the diode 111,
If the breakdown voltage of 203 is lowered, the MOSF will be more effective.
The gate oxide film of ET can be protected.

7 and 8 show a third embodiment of the present invention. FIG. 7 shows N out of CMOS constituting the output protection device.
Only the chMOSFET portion is shown, and FIG. 8 shows an equivalent circuit thereof. Explaining the structure, in the present embodiment, the N ⁺ type region 300 is formed in the portion where the P ⁺ type region 104 is formed in the second embodiment, and the gate electrode 1 is formed.
It is connected to 06. A diode 301 is formed by the P-type well 100 and the N ⁺ -type region 300, and this diode 301 is connected between the resistor 114 and the gate electrode 106 of the Nch MOSFET 110. The protective action of the Nch MOSFET 110 when a surge is applied is similar to that in the second embodiment. In this embodiment,
Since it is not necessary to form a plurality of semiconductor regions on the field oxide film 3, there is an advantage that the process is simplified. If the diode 301 has a Zener diode structure, the gate oxide film can be protected more effectively. In addition,
If the Pch MOSFET has a similar structure, it is possible to protect against a surge applied between the output terminal 14 and the Vdd terminal.

9 and 10 show a fourth embodiment of the present invention. FIG. 9 shows only the Nch MOSFET portion of the CMOS constituting the output protection device, and FIG. 10 shows its equivalent circuit. To explain the configuration, an N-type region 403 is formed on the main surface of the P-type well 100, and
The N ⁺ type region 102 which is the source region of the NchMOSFET 110 is formed at one end of the type region 403, and the N ⁺ type region 400 is formed at the other end. And both N ⁺
A P ⁺ type region 401 is formed on the main surface of the N type region 403 between the mold regions 102 and 400. A second electrode 405 is formed on the main surface of P ⁺ type region 104 with dielectric 107 interposed. The N ⁺ type region 400 and the P ⁺ type region 401 are connected to the Vss terminal, and the second electrode 405
Are connected to the N ⁺ type region 102. The N ⁺ type region 102 is not connected to the Vss terminal. The capacitor 407 formed by the second electrode 405, the dielectric 107 and the P ⁺ type region 104 is a resistor 114 and an NchMOS.
It is connected between the FET 110 and the source region 102. The capacitor 407 forms a third means for feeding back the fluctuation of the potential in the vicinity of the drain region 103 of the N-channel MOSFET 110 in the P-type well 100 to the source region 102 thereof. N-type region 40
The resistor 408 formed inside 3 is the Nch MOSFET 1
10 source regions 102 and Vss terminals. Other configurations are similar to those of the first embodiment.

Next, the operation of the output protection device configured as described above will be described.

(A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; In this case, the following actions and effects are obtained in addition to the actions and effects of the first embodiment. That is, firstly, the capacitor 407 allows NchMOSFE
The source potential of T110 rises. Therefore, not only the potential difference between the gate electrode 106 and the drain region 103 and between the active regions but also the potential difference between the gate electrode 106 and the source region 102 is reduced.
The breakdown of the gate oxide film 105 of 10 becomes more difficult to occur. Secondly, since the potential of the N ⁺ type region (source region) 102 rises, the potential of the N type region 403 also rises.
Therefore, the junction formed by the N-type region 403 and the P ⁺ -type region 401 and the junction formed by the N-type region 403 and the P-type well 100 are in the reverse bias state, and the depletion layer spreads inside the N-type region 403. As a result, the neutral region inside the N-type region 403 becomes narrower, and the value of the resistor 408 increases. Therefore NPN
Since the emitter resistance of Tr113 increases, NPNTr
The surge current flowing through 113 decreases and Nc due to the surge
The destruction of the hMOSFET 110 becomes more difficult to occur.

(B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal; In this case, in addition to the function and effect of the first embodiment, there is the capacitor 407,
The source potential of the Nch MOSFET 110 decreases. Therefore, not only between the gate electrode 106 and the drain region 103, between the active regions, but also between the gate electrode 106 and the source region 10.
Since the potential difference between 2 and N also decreases, Nch due to surge
The breakdown of the gate oxide film 105 of the MOSFET 110 becomes more difficult to occur.

If the PchMOSFET has a similar structure, the PchMOSFET can be protected against a surge applied between the output terminal 14 and the Vdd terminal. Further, in this embodiment, the resistor 114 and the Nch MOSFET
The capacitor 110 is connected to the source region 102 of the capacitor 110, but the same protection effect is obtained by connecting a diode as in the second and third embodiments.

11 and 12 show a fifth embodiment of the present invention. FIG. 11 shows only the Nch MOSFET portion of the CMOS that constitutes the output protection device.
2 shows the equivalent circuit. Explaining the configuration, N
A second P-type well 500 is formed adjacent to the first P-type well 100 on the main surface of the mold substrate 1. A P ⁺ type region 502 and two N ⁺ type regions are formed on the main surface of the second P type well 500.
Mold regions 505 and 506 are formed. A gate electrode 511 is formed on the main surface of the second P-type well 500 between the two N ⁺ -type regions 505 and 506 via a gate oxide film 105.
Are formed. P ⁺ type region 502 and N ⁺ type region 50
5 is connected to the Vss terminal. The N ⁺ type region 506 is connected to the N ⁺ type region 102. Further, the P ⁺ type region 104 in the first P type well 100 is connected to the gate electrode 511 via an inverter (a cross sectional structure is not shown) 513. The N ⁺ type region 102 is not connected to the Vss terminal. The N ⁺ type region 505 is used as a source region and the N ⁺ type region 506 is used as a drain region, and these and the gate electrode 511 on the gate oxide film 105 are used to form a second N region.
A chMOSFET 521 is formed. Also, the N ⁺ type region 505 is the emitter, the P type well 500 is the base,
NPN type Tr 525 having a ⁺ type region 506 as a collector
And a diode 523 having the N ⁺ type region 506 as a cathode and the P type well 500 as an anode is formed. The drain of the second Nch MOSFET 521 is the first Nc.
It is connected to the source of the hMOSFET 110. The other structure is the same as that of the first embodiment.

Next, the protective action of the gate oxide film when a surge is applied will be described.

(A) When the polarity of the surge is positive at the output terminal 14 with respect to the Vss terminal; In addition to the functions and effects of the first embodiment, the following functions and effects are obtained. First, second
Since the Nch MOSFET 521 is off, the potentials of the N ⁺ type regions 102 and 506 are not fixed. When the potential of the gate electrode 106 of the first Nch MOSFET 110 is increased by the capacitor 115, the potential of the N ⁺ type region 102 is also increased. Therefore, not only between the gate electrode 106 and the drain region 103, between the active regions, but also between the source region 102.
The potential difference between and also decreases. Second, the N ⁺ type region 102
Potential rises and the junction of the N ⁺ type region 102 and the first P type well 100 is reverse biased, so that the NPN type Tr 113 does not turn on. Therefore, NPN type Tr
Current concentration on 113 does not occur. As a result, the gate oxide film 1 of the first Nch MOSFET 110 due to the surge is generated.
The destruction of 05 becomes more difficult to occur.

(B) When the polarity of the surge is negative at the output terminal 14 with respect to the Vss terminal: In this case, the same action and effect as those of the first embodiment are obtained.

Here, in the present embodiment, in the normal circuit operation, the potential of the first P-type well 100 is the Vss potential, so that the output of the inverter 513 becomes the Vdd potential and the second Nch MOSFET 521 is turned on. To do. Therefore, the circuit operation is not impaired. Further, in this embodiment, when a positive overvoltage surge is applied to the output terminal 14 during the normal circuit operation, there is a protective action as described below.
That is, the holes generated by the breakdown of the diode 111 flow through the resistor 112, and the potential of the first P-type well 100 rises. This allows the inverter 5
The output of 13 turns to the Vss potential, and the second NchMOSF
ET521 is turned off. As a result of the N ⁺ -type region 102 floating, the NP inside the first P-type well 100
The turn-on of the N lateral Tr 113 and the NPN vertical Tr (not shown), that is, the so-called snapback phenomenon does not occur. In addition, snapback does not trigger and latch-up does not occur. This protective action occurs even without the capacitor 115. As in the second or third embodiment, a diode is used instead of the capacitor 115 and the P ⁺ type region 104 and the first Nch MOSFET are used.
Even if the gate electrode 106 of 110 is connected, the same protective action as described above occurs. Further, if the Pch MOSFET has a similar structure, a similar protection action is produced against a surge applied between the output terminal 14 and the Vdd terminal.

Although the output protection device has been described in the first to fifth embodiments, it can be used as an input protection device if the gate of the MOSFET is connected to the source through the resistor and the drain is connected to the input terminal. . Further, when a P-type semiconductor substrate is used, in each embodiment, if the Vdd terminal and the Vss terminal are exchanged and the N-type and P-type of the diffusion layer are exchanged, the same protection effect against surge is obtained.

[0048]

As described above, according to the present invention,
First, in a semiconductor protection device having a MOSFET whose drain region is connected to either an input terminal or an output terminal of a protected semiconductor device, a potential of a portion near the drain region in a substrate region where the MOSFET is formed. And a second means for feeding back the fluctuation of the potential detected by the first means to the gate electrode of the MOSFET to relax the electric field between the gate electrode and the drain region. Since it is equipped with MOSF
When a surge is applied to the drain region of ET, the potential fluctuation in the vicinity of the drain region in the substrate region is fed back to the gate electrode, and the potential difference between the gate and drain is reduced to prevent the breakdown of the gate insulating film of the MOSFET. be able to.

Secondly, the first means is a high-concentration region which is formed in the vicinity of the drain region and has the same conductivity type as the substrate region, and the second means includes the high-concentration region and the gate electrode. Since the capacitor is connected, the feedback action of the potential fluctuation in the vicinity of the drain region can be better achieved, and at the same time, the ease of forming the feedback means on the semiconductor substrate can be obtained.

Thirdly, the first means is a high-concentration region formed in the vicinity of the drain region and having the same conductivity type as the substrate region, and the second means is arranged from the high-concentration region to the gate electrode. Since the diode is connected in the direction, the feedback action of the potential fluctuation is performed by the forward direction or the breakdown characteristic of the diode according to the polarity of the surge, and the breakdown voltage is set lower than the breakdown voltage of the gate insulating film. It is possible to prevent the gate insulating film of the MOSFET from being destroyed. Further, similar to the above, the ease of forming the feedback means on the semiconductor substrate can be obtained.

Fourth, the drain region is connected to either the input terminal or the output terminal of the protected semiconductor device.
In a semiconductor protection device having an OSFET, the first
Means for detecting the potential of the portion in the vicinity of the drain region in the first substrate region in which the second MOSFET is formed, and the fluctuation of the potential detected by the first means is applied to the gate of the first MOSFET. A second means for feeding back to the electrode to relax an electric field between the gate electrode and the drain area; and a variation in the potential detected by the first means to the source area of the first MOSFET to be fed back to the source area. Since the third means for relaxing the electric field between the gate electrode and the source region is provided, when the surge is applied to the drain region of the MOSFET, the potential difference between the gate and the drain becomes smaller and the potential difference between the gate and the source becomes smaller. It is possible to prevent the breakdown of the gate insulating film of the MOSFET more reliably.

Fifth, the first means is formed in the vicinity of the drain region and is of the same conductivity type as the first substrate region.
The second capacitor is connected to the gate electrode in the forward direction from the first capacitor or the first high concentration region connecting the first high concentration region and the gate electrode. And a third capacitor connected to the first high concentration region and the source region in order from the first high concentration region to the source region. Which is one of the second diodes connected in a direction, and further has a low-concentration region of a reverse conductivity type to the first substrate region formed on the main surface of the first substrate region, and one end of the low-concentration region is formed. And a second high-concentration region of the same conductivity type as the source region at the other end and a second high-concentration region of the same conductivity type as the source region between the source region and the second high-concentration region. A third high-concentration region of the second high-concentration region and the third high-concentration region of The potential region is connected to either a high-potential terminal that gives a high potential to the first substrate region or a low-potential terminal that gives a low potential. Appropriate feedback can be given to the source area. When a surge is applied to the drain region, the potentials of the first substrate region and the reverse conductivity type low concentration region fluctuate through the source region, and the potential between the low concentration region and the first substrate region and the low concentration region is opposite. Each junction between the conductive type third high-concentration regions is reverse-biased, and the neutral region inside the low-concentration region is narrowed. As a result, the emitter resistance of the parasitic bipolar transistor formed in the source region, the drain region, etc. of the MOSFET increases, and the surge current decreases, so that the MOSFE can be more reliably processed.
The destruction of T can be prevented.

Sixth, the first means is the first MO.
A high-concentration region that is formed in the vicinity of the drain region of the SFET and is of the same conductivity type as the first substrate region; and the second means connects the high-concentration region and the gate electrode of the first MOSFET, or One of the diodes connected in the forward direction from the high-concentration region to the gate electrode of the first MOSFET, wherein the third means is disposed on the second substrate region of the same conductivity type as the first substrate region. The first MO
A second MOSFET having the same polarity as that of the SFET is formed, and the high concentration region is connected to the second MOSFET through an inverter.
The drain region of the second MOSFET is connected to the source region of the first MOSFET, and the source region of the second MOSFET and the second substrate region are connected to the first region of the first MOSFET. Since the substrate region is configured to be connected to either a high-potential terminal that gives a high potential or a low-potential terminal that gives a low potential, when a surge of a certain polarity is applied to the drain region of the first MOSFET, the second MOSF
ET is turned off, and the source region of the first MOSFET becomes floating. As a result, the first MOSFET
The parasitic bipolar transistor formed in the source region, the drain region, etc. is turned off, latch-up is prevented from occurring, and the first MOSFET can be more reliably prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a first embodiment of a semiconductor protection device according to the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of the first embodiment.

FIG. 3 is a circuit diagram showing a portion related to charging and discharging of a gate-drain capacitor of an Nch MOSFET in a second equivalent circuit.

FIG. 4 is a vertical sectional view showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an equivalent circuit of FIG.

FIG. 6 is a circuit diagram showing a portion related to charging / discharging of a gate-drain capacitor of an Nch MOSFET in the second embodiment.

FIG. 7 is a vertical sectional view showing a third embodiment of the present invention.

8 is a circuit diagram showing an equivalent circuit of FIG.

FIG. 9 is a vertical cross-sectional view showing a fourth embodiment of the present invention.

10 is a circuit diagram showing an equivalent circuit of FIG. 9. FIG.

FIG. 11 is a vertical sectional view showing a fifth embodiment of the present invention.

12 is a circuit diagram showing an equivalent circuit of FIG.

FIG. 13 is a vertical cross-sectional view of a conventional semiconductor protection device.

14 is a circuit diagram showing an equivalent circuit of FIG.

[Explanation of symbols]

14 output terminals 20 Pch MOSFETs 50, 51 Pch, Nc constituting a protected semiconductor device
h MOSFET 100 P-type well 102, 505 serving as a first substrate region N ⁺ type region 103, 506 serving as a source region N ⁺ type region 104 serving as a drain region P ⁺ type region (first means) 105 Gate oxidation Film (gate insulating film) 106, 511 Gate electrode 110 NchMOSFET 115 Capacitor (second means) 203 Diode (second means) 400 N ⁺ type region (second high-concentration region of the same conductivity type as the source region) 401 P ⁺ type region (the same conductivity type as the first substrate region)
403 N-type region (first substrate region and reverse conductivity type low-concentration region) 407 Second capacitor (third means) 500 P-well 513 to be the second substrate region 513 Inverter 521 2 Nch MOSFET

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/088 8934-4M H01L 27/08 102 F

Claims (6)

[Claims] 1. A semiconductor protection device having a MOSFET whose drain region is connected to either an input terminal or an output terminal of a protected semiconductor device, wherein a portion of the substrate region in which the MOSFET is formed is located in the vicinity of the drain region. First means for detecting an electric potential, and second means for feeding back the fluctuation of the electric potential detected by the first means to the gate electrode of the MOSFET to relax the electric field between the gate electrode and the drain region. A semiconductor protection device comprising: 2. The first means is a high-concentration region formed in the vicinity of the drain region and having the same conductivity type as the substrate region, and the second means connects the high-concentration region and the gate electrode. The semiconductor protection device according to claim 1, wherein the semiconductor protection device is a capacitor. 3. The first means is a high-concentration region formed in the vicinity of the drain region and having the same conductivity type as the substrate region, and the second means is in the forward direction from the high-concentration region to the gate electrode. The semiconductor protection device according to claim 1, wherein the semiconductor protection device is a connected diode. 4. A first MOSF whose drain region is connected to either an input terminal or an output terminal of a protected semiconductor device.
In the semiconductor protection device having ET, the first MO
First means for detecting the potential of the portion in the vicinity of the drain region in the first substrate region in which the SFET is formed, and the variation of the potential detected by the first means is applied to the gate electrode of the first MOSFET. Second means for relieving the electric field between the gate electrode and the drain region by feeding back to the source region of the first MOSFET by feeding back the potential fluctuation detected by the first means. A semiconductor protection device comprising: an electrode and a third means for relaxing an electric field between the source region and the source region. 5. The first means is a first high-concentration region formed near the drain region and having the same conductivity type as the first substrate region, and the second means is the first high-concentration region. A first capacitor connecting a region and the gate electrode or a first diode connected in a forward direction from the first high concentration region to the gate electrode, wherein the third means is the third device. One of a second capacitor connecting the high concentration region and the source region or a second diode connected in a forward direction from the first high concentration region to the source region; On the main surface of the substrate area of
Of the substrate region and a low-concentration region of reverse conductivity type are formed, the source region is provided at one end of the low-concentration region, and a second high-concentration region of the same conductivity type as the source region is provided at the other end. A third high concentration region of the same conductivity type as the first substrate region is provided between the second high concentration region and the second high concentration region and the third high concentration region. 5. The semiconductor protection device according to claim 4, wherein the substrate protection region is connected to either a high potential terminal that applies a high potential or a low potential terminal that applies a low potential. 6. The first means is the first MOSFE.
A high concentration region formed in the vicinity of the drain region of T and having the same conductivity type as the first substrate region, and the second means connects the high concentration region and the gate electrode of the first MOSFET, or From the high concentration region to the first M
One of the diodes connected in the forward direction to the gate electrode of the OSFET, wherein the third means includes the first MOSFET in the second substrate region of the same conductivity type as the first substrate region.
A second MOSFET having the same polarity as T is formed, the high concentration region is connected to the gate electrode of the second MOSFET through an inverter, and the drain region of the second MOSFET is the source of the first MOSFET. And connecting the source region of the second MOSFET and the second substrate region to either a high potential terminal that gives a high potential or a low potential terminal that gives a low potential to the first substrate region. The semiconductor protection device according to claim 4, wherein the semiconductor protection device is configured as follows.