JP3472911B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
Particularly, it relates to a structure for protecting a circuit from a surge such as static electricity.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of element dimensions of semiconductor devices, the thickness of impurity regions such as a source region, a drain region, and a gate electrode has been reduced. The parasitic resistance of the gate electrode is increasing. Such an increase in parasitic resistance causes a decrease in the operating speed of the circuit. A technique called a salicide process has been proposed as a technique for reducing the parasitic resistance of the source region, the drain region, and the gate electrode. Regarding this salicide process, conventional techniques disclosed in, for example, JP-A-5-75045 and JP-A-5-259115 are known.

In this salicide process, a film of a metal such as titanium, cobalt, tungsten, molybdenum, or tantalum is entirely sputtered on a semiconductor substrate on which a source region, a drain region, and a gate electrode have already been formed, and heat treatment is performed. It As a result, the silicon of the source region, the drain region and the gate electrode is alloyed with the deposited metal to form a metal silicide layer. afterwards,
The metal left unalloyed is removed. As a result, the low-resistance metal silicide layer is formed in self-alignment with the source region, the drain region, and the gate electrode.
Thus, using salicide process, the source region,
By forming a low resistance metal silicide layer on the surface of the drain region and the gate electrode, the source region, the drain region,
The parasitic resistance of the gate electrode can be remarkably reduced.
As a result, the operating speed of the circuit can be significantly improved.

A transistor formed by using the salicide process, that is, a transistor having a salicide structure has a problem that its ESD performance is lower than that of a transistor having no salicide structure. As a technique for improving the ESD performance of a salicide structure transistor, for example, a conventional technique disclosed in Japanese Patent Laid-Open No. 5-3173 is known. In this conventional technique, the source region and the drain region of the transistor of the output buffer have a silicide structure, while the gate electrode has a polycide structure to improve the ESD performance.

However, this conventional technique has a problem that the manufacturing process is complicated because both the silicide process and the polycide process are required. Further, in this conventional technique, only electrostatic breakdown due to current concentration near the boundary between the drain region and the gate electrode is considered, and electrostatic breakdown at a place other than the boundary between the drain region and the gate electrode is considered. Didn't.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of improving the ESD performance by a simple manufacturing process.

[0007]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention is formed in a first region of a first conductivity type and has a substantially rectangular second conductivity type to which a power supply potential is applied. A first impurity region and a second conductive type second having a substantially rectangular shape and formed adjacent to the first impurity region with a given interval.
The first metal silicide layer includes an impurity region, a substantially rectangular first metal silicide layer formed on the surface of the second impurity region, and a contact connecting the first metal silicide layer and the wiring layer. Between the one side of the first impurity region side and the one side of the second impurity region on the first impurity region side of L1, the other side of the first metal silicide layer, and the second impurity region When the distance from the other side is L2, L2 ≧ L1.

According to the present invention, since L2 ≧ L1,
Most of the current due to surges such as static electricity can be discharged to the power supply potential via the bipolar formed by the second impurity region, the first region and the first impurity region. As a result, a large current can be prevented from flowing to the diode formed on the other side of the second impurity region, and the ESD performance can be improved.

Further, according to the present invention, the first metal silicide layer and the second impurity region are formed in a substantially rectangular shape,
The other side of the first metal silicide layer and the second impurity region is a short side of the first metal silicide layer and the second impurity region formed in a substantially rectangular shape. When the second impurity region is formed in a substantially rectangular shape, the current passage area on the short side of the second impurity region is small. Therefore, when a large current flows through the diode formed on the short side, electrostatic breakdown easily occurs. According to the present invention, a large current can be prevented from flowing to the diode on the short side of the substantially rectangular second impurity region, so that the ESD performance can be further improved.

Further, according to the present invention, a substantially rectangular shaped third impurity region of the second conductivity type formed in the second region of the first conductivity type and a substantially square shape formed on the surface of the third impurity region. A second metal silicide layer, a contact connecting the second metal silicide layer and the wiring layer, and a distance between one side of the second metal silicide layer and one side of the third impurity region is L3. In that case, L3 ≧ L1. By doing so, most of the current due to surge such as static electricity can be discharged through the bipolar formed by the second impurity region, the first region, and the first impurity region, and the third impurity region and the second region can be discharged. It is possible to prevent a large current from flowing through the diode composed of. This makes it possible to prevent the elements connected to the wiring layer in parallel to the second impurity region from being electrostatically destroyed by a surge such as static electricity.

According to the present invention, a substantially rectangular second conductivity type first impurity region which is formed in the first conductivity type first region and to which a power supply potential is applied and a first impurity region adjacent to the first impurity region are provided. A substantially rectangular second conductivity type second impurity region formed apart from each other, a substantially square first metal silicide layer formed on the surface of the second impurity region, and the first metal silicide. A first conductive type fourth impurity region which is formed so as to at least partially overlap the first region and is supplied with the power supply potential; and a contact connecting the layer and the wiring layer. The distance between one side of the first impurity region side of the layer and one side of the contact formed on the one side of the fourth impurity region is L4, the other side of the first metal silicide layer, and the fourth side. Formed on the other side of the impurity region When the L5 the distance between the side of contact being characterized in that it is a L5 ≧ L4.

Consider a case where a large forward current flows through a diode formed of the second impurity region and the first region due to a surge such as static electricity. In such a case, according to the present invention, since L5 ≧ L4, most of the current due to a surge such as static electricity is generated in the diode formed on one side (first impurity region side) of the second impurity region. It becomes possible to discharge through. As a result, a large current can be prevented from flowing to the diode formed on the other side of the second impurity region, and the ESD performance can be improved.

When a third metal silicide layer is formed on the surface of the fourth impurity region, the L4 faces one side of the first metal silicide layer on the first impurity region side and the one side. Is the distance between the side of the third metal silicide layer and L5 is the distance between the other side of the first metal silicide layer and the side of the third metal silicide layer facing the other side. Is desirable.

Further, according to the present invention, the substantially square-shaped third impurity region of the second conductivity type formed in the second region of the first conductivity type and the substantially rectangular shape formed on the surface of the third impurity region. A first conductivity type, which is formed so that at least a part of the second metal silicide layer, a contact connecting the second metal silicide layer and the wiring layer overlap the second region, and is supplied with the power supply potential. L6 ≧ L4, including a fifth impurity region, where L6 is a distance between one side of the second metal silicide layer and one side of the contact formed in the fifth impurity region. And By doing so, most of the current due to a surge such as static electricity can flow to the diode formed on one side of the second impurity region, and the diode formed of the third impurity region and the second region. It is possible to prevent a large current from flowing through. This makes it possible to further improve the ESD performance.

When a third metal silicide layer is formed on the surface of the fourth impurity region and a fourth metal silicide layer is formed on the surface of the fifth impurity region, the L
4 is a distance between one side of the first metal silicide layer on the first impurity region side and a side of the third metal silicide layer facing the one side, and L 6 is the second metal silicide. It is desirable that the distance is one side of the layer and the side of the fourth metal silicide layer facing the one side.

In the present invention, it is desirable that the first and second impurity regions are a source region and a drain region of an output buffer connected to a pad, respectively. Further, the first and second impurity regions may be an emitter region and a collector region of a lateral bipolar type protection circuit, respectively.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The preferred embodiments of the present invention will be described below. In the following description, the first conductivity type is p-type and the second conductivity type is n-type. An example of application to a MOS transistor will be mainly described. However, the present invention is also applicable when the first conductivity type is n-type and the second conductivity type is p-type. In addition to the MOS type transistor, it can be applied to various transistors such as a MIS type transistor. In addition to transistors,
It can also be applied to lateral bipolar.

1. Configuration of this Embodiment FIG. 1A shows an example of a plan view of this embodiment. Further, FIG. 1B shows a conceptual cross-sectional view taken along line A1-A2 in FIG.

In FIGS. 1A and 1B, a p-type well 12 (first region) is formed in an n-type semiconductor substrate 10. The p-type well 12 is a p-type well tap region 1 formed using a manufacturing process such as diffusion and ion implantation.
4 (fourth impurity region), contacts 16, 18 and the like, and is connected to ground potential GND (lower power supply potential). The well tap region 14 may be formed so that at least a part thereof overlaps the p-type well 12.

The n-type source regions 20 and 21 (first impurity regions) are formed in the p-type well 12 using a manufacturing process such as diffusion and ion implantation. This source region 20, 2
1 is connected to GND via contacts 34, 35 and the like.

The drain region 22 (second impurity region) is
It is formed next to the source regions 20 and 21 with a given distance. That is, the drain region 22 includes the gate electrodes 24 and 2.
It is formed adjacent to the source regions 20 and 21 with 5 interposed therebetween. Then, on the surface of the drain region 22, titanium, cobalt,
A first metal silicide layer 30 that is an alloy of silicon with a metal such as tungsten, molybdenum, or tantalum is formed. As shown in FIG. 1B, the first metal silicide layer 30 is connected to the wiring layer 40 via the contact 32 and the like, and the wiring layer 40 is connected to the pad 42. Here, the reason why the first metal silicide layer 30 is interposed between the drain region 22 and the wiring layer 40 is to enable ohmic contact between the drain region 22 and the wiring layer 40. That is, the first metal silicide layer 30 is the contact 3
It functions as a 2 barrier metal.

Source regions 20, 21 and drain region 22
An output buffer is formed by the transistor including the gate electrodes 24 and 25. The output buffer functions as a protection circuit for the output buffer itself and the internal circuit connected to the output buffer.

The feature of this embodiment is that in FIG. 1A, L2 ≧
The point is L1. Here, L1 corresponds to the distance between the side 50 of the first metal silicide layer 30 on the source region 20 side and the side 52 of the drain region 22 on the source region 20 side. L2 is a side 54 of the first metal silicide layer 30.
And the side 56 of the drain region 22.

By setting L2 ≧ L1 as described above, most of the charges injected by the surge 44 are caused to pass through the path E in FIG.
It is possible to discharge at 1 and prevent a large current from flowing through the path E2. That is, most of the injected charges are transferred to the diodes D1 and D.
It is possible to flow by using a bipolar BP constituted by 2. As a result, the drain region 22 and the device isolation film 3
It is possible to prevent a large current from flowing through the diode D3 formed near the boundary of 8. As a result, electrostatic breakdown at the portion indicated by E3 in FIG. 1B can be prevented.

In FIGS. 1A and 1B, the distance L2 between the rectangular drain region 22 and the sides 54 and 56 which are the short sides (sides in the gate electrode length direction) of the first metal silicide layer 30. Is L2 ≧ L1. However, FIG.
As shown in (A), when there is no source region on the left side (or the right side) of the drain region 22, the distance L2 ′ between the long sides (sides in the gate electrode width direction) 51, 53. It is desirable that L2 ′ ≧ L1.

In this embodiment, as shown in FIG. 2B, the emitter regions 220, 221 (first impurity regions),
Collector region 222 (second impurity region), base region 2
It is also applicable to a lateral bipolar type protection circuit composed of 24 and 225. That is, in this case, the relationship between the distance L1 between the side 250 of the first metal silicide layer 230 and the side 252 of the collector region 222 and the distance L2 between the sides 254 and 256 is L2 ≧ L1.

2. Effects of this Embodiment By setting L2 ≧ L1 as in this embodiment, the following effects can be obtained.

(1) The injected charges due to the surge can be discharged to GND by using the bipolar BP.

That is, when the surge 44 is applied to the drain region 22, the diode parasitic on the drain region 22 avalanche breaks. At this time, the drain voltage becomes Vbd, as indicated by B1 in FIG. After that, when the bipolar BP is turned on, the drain voltage decreases from Vbd to Vsp, as indicated by B2 in FIG. Such a phenomenon in which the drain voltage drops is called snapback. At the time of snapback, the input impedance of the drain region 22 becomes very low. Therefore, the charges injected into the drain region 22 by the surge 44 can be easily discharged to GND. Further, even if the surge 44 having a magnitude of 200 V is applied, the voltage of the drain region 22 can be reduced to about Vsp = 8V.

However, in FIG. 1A of Japanese Patent Laid-Open No. 5-3173, L2 <L1. Therefore, in this conventional technique, before the bipolar BP is turned on, the diode D3 near the boundary between the drain region 22 and the element isolation film 28 undergoes avalanche break, and a large current flows through this diode D3. Therefore, the portion E3 may be electrostatically destroyed before the drain voltage and the input impedance of the drain region 22 are reduced by the snapback.

On the other hand, in this embodiment, L2 ≧ L1
Therefore, the bipolar BP can be easily turned on. As a result, the drain voltage and the input impedance of the drain region 22 can be reduced, and the load on the element can be reduced. Further, it is possible to prevent a large current from flowing through the diode D3, and it is possible to prevent electrostatic breakdown at the portion E3.

(2) The passing area of current in the discharge path can be increased.

As shown in FIG. 3B, the width W of the transistor forming the output buffer is generally large, and the width WD of the drain region 22 is smaller than W. In a general output buffer, W is, for example, about 200 to 300 μm, and WD is, for example, about 10 μm. Therefore, FIG.
As shown in F1, F2, and F3 of (B), the source region 2
The current passing area on the 0, 21 side is larger than that on the element isolation film side.

According to this embodiment, since L2 ≧ L1, it becomes possible to flow a current to the source regions 20 and 21 having a large current passage area. As a result, current concentration can be prevented and ESD performance can be improved.

Now, referring to FIG. 1 of Japanese Patent Laid-Open No. 5-3173
In (A), L2 = 0. Thus L2 = 0
By so setting, as shown in FIG. 4A, the effective width Weff of the transistor can be made equal to W, and the speed of the transistor can be increased. This is because the first metal silicide layer 30 has a remarkably smaller parasitic resistance than the drain region 22.

As described above, in the past, it was general to set L2 = 0 (<L1) by giving priority to the speedup of the transistor.

Contrary to such a situation that hinders the construction of the present embodiment, the present embodiment is contrary to L2 ≧ L.
There is a big feature in that it is 1. That is, when L2 ≧ L1, Weff becomes smaller than W as shown in FIG. The present embodiment sacrifices such a decrease in transistor capability to some extent,
Priority is given to the improvement of the ESD performance, and L2 ≧ L1.

For example, in the case of a manufacturing process of 0.35 μm, L1 is preferably 0.5 to 0.8 times as long as L2. By doing so, a sufficient ESD breakdown voltage can be obtained without significantly lowering the transistor capability.

3. Protection of Other Elements Connected to Pad Above, the ESD countermeasure of the output buffer has been mainly described.

However, in the input / output buffer 60 having the output buffer 62 and the input buffer 64 as shown in FIG. 5, for example, the surge 44 from the pad 42 is caused by the wiring 4
It is also applied to the diodes D4 and D5 via 0. These diodes D4 and D5 are parasitically formed in front of a protection resistance (diffusion resistance) RP for protecting the gate electrode of the input buffer 64. And FIG.
As in the case where the drain region 22 of (A) is provided with the ESD countermeasure, it is necessary to provide the diode with the ESD countermeasure.

FIG. 6 shows an example of a plan view of the diode D5 provided on the GND side. Further, FIG. 7 shows a conceptual cross-sectional view taken along the line A3-A4 in FIG.

Here, the cathode region 70 of the diode D5
The (third impurity region) is formed in the p-type well 68 (second region) by using a manufacturing process such as diffusion and ion implantation. The p-type well 68 may be the same as the p-type well 12 (first region) in which the output buffer 62 is formed.

A second metal silicide layer 72, which is an alloy of silicon with a metal such as titanium, cobalt, tungsten, molybdenum, or tantalum, is formed on the surface of the cathode region 70. The second metal silicide layer 72 is connected to the wiring layer 40 via the contact 74. Here, the reason why the second metal silicide layer 72 is interposed between the cathode region 70 and the wiring layer 40 is that the cathode region 70 and the wiring layer 4 are arranged.
This is to enable ohmic contact with 0.

In this embodiment, in order to protect the diode D5, L3 ≧ L1 as shown in FIG. Here, L3 is a side 82 or 83 of the second metal silicide layer 72.
And the sides 84 and 85 of the cathode region 70.

By setting L3 ≧ L1 in this way, most of the injected charges due to the surge 44 can be discharged to the source regions 20 and 21 side of the output buffer 62, and a large current can be prevented from flowing in the path E4 of FIG. That is, most of the injected charges can be made to flow using the bipolar BP shown in FIG. This can prevent a large current from flowing through the diode D5 in FIG. As a result, it becomes possible to prevent electrostatic breakdown at the portion indicated by E5 in FIG.

In FIG. 6, the diode D of the input buffer is
5, the relationship of L3 ≧ L1 is established. However, the present invention is not limited to this, and it is desirable to establish the relationship of L3 ≧ L1 in various elements electrically connected in parallel to the output buffer 62 (or the lateral bipolar protection circuit). As such an element,
For example, a pull-up transistor or an analog output buffer can be considered.

4. ESD without avalanche break of diode In FIGS. 1A and 1B, the n-type drain region 22 and p
The ESD with avalanche break of the diode formed by the well 12 has been described. In this case, as shown in FIG. 8A, a positive surge is applied to the drain region 22 of the output buffer (terminal OUT) with reference to GND.

On the other hand, in FIG. 8B, a negative surge is applied to the drain region 22 of the output buffer with reference to GND. The application of such a negative surge results in ESD without avalanche break of the diode. That is, a current flows in the diode in the forward direction.

In the case of a p-type transistor, VD
Application of negative surge based on D is ESD with avalanche break, and application of positive surge based on VDD is ES without avalanche break.
It becomes D.

The electrostatic breakdown due to ESD without avalanche break as shown in FIG. 8B has not been considered so far. However,
It has been found that with the miniaturization of the element size, an output buffer that has not been electrostatically destroyed in the ESD with the avalanche break may be electrostatically destroyed in the ESD without the avalanche break.

In order to prevent such a situation, in this embodiment, L5 is set to L4 or more as shown in FIG. 9 (A). Here, L4 corresponds to the distance between the side 50 of the first metal silicide layer 30 on the source region 20 side and the side 17 of the contact 16 formed on the side 50 side of the well tap region 14. Further, L5 is the side 54 of the first metal silicide layer 30 and the side 54 in the well tap region 14.
It corresponds to the distance between the side 19 of the contact 18 formed on the side.

By setting L5 ≧ L4 as described above, most of the forward discharge current due to the negative surge 90 is generated as shown in FIG.
(B) The path E6 can be discharged, and a large current can be prevented from flowing to the path E7. That is, a forward discharge current due to the negative surge 90 can be supplied using the diode D1. This can prevent a large forward current from flowing through the diode D3 formed near the boundary between the drain region 22 and the element isolation film 38. As a result, E3 in FIG.
It is possible to prevent electrostatic breakdown at the portion indicated by.

The reason why the ESD performance can be improved by discharging in the route E6 is as follows. That is, as already described with reference to FIG. 3B, the width W of the transistor forming the output buffer is generally large and the width WD of the drain region 22 is large.
Is small. Therefore, the current passing area is larger on the source regions 20 and 21 side than on the element isolation film 38 side. Further, according to the present embodiment, L5 ≧ L4, so that most of the current can be made to flow to the source regions 20, 21 side having a large current passage area. As a result, current concentration can be prevented and ESD performance can be improved.

Until now, in order to minimize the layout area of the output buffer, the distance LT shown in FIG. 9A was generally set to the minimum distance allowed by the design rule. When the distance LT is set to the minimum distance, L
5 is smaller than L4 (see FIG. 1 (A)).

Contrary to such a situation that hinders the construction of the present embodiment, the present embodiment has L5 ≧ L.
There is a big feature in that it was set to 4. That is, when L5 ≧ L4, the portion indicated by F4 in FIG. 9A becomes a wasted space, and the layout area of the output buffer becomes large. In the present embodiment, such an increase in layout area is sacrificed to some extent, and L5 ≧ L4 is given priority in improving the ESD performance.

In order to prevent the current from being discharged through the path E6 in FIG. 9B and the large current from flowing through the path E7,
It is important to set the parasitic resistance R2 in FIG. 9B to R1 or more. Here, R1 is the first metal silicide layer 30,
It corresponds to the parasitic resistance between the well tap region 14 and the contact 16. R2 is the first metal silicide layer 30.
Corresponds to the parasitic resistance between the contact 18 and the well tap region 14. If R2 ≧ R1 holds, L5 can be made slightly smaller than L4.

5. Protecting Other Elements Connected to the Pad In the input / output buffer 60 as shown in FIG. 5, when a negative surge based on GND is applied to the pad 42, a forward current flows through the diode D5. Flowing. Therefore, it is necessary to take an ESD countermeasure for this diode D5 as well as an ESD countermeasure for the drain region 22.

FIG. 10 shows an example of a plan view of the diode D5 provided on the GND side. Further, FIG. 11 shows a conceptual cross-sectional view taken along the line A7-A8 in FIG.

In the present embodiment, in order to protect the diode D5, L6 is set to L4 or more as shown in FIG. Here, L6 is a side 82 of the second metal silicide layer 72.
Or 83 and contacts 76, 7 of the well tap region 80
It corresponds to the distance between the sides 77 and 79 of 8.

By setting L6 ≧ L4 as described above, most of the forward discharge current due to the negative surge 90 can be discharged through the source regions 20 and 21 of the output buffer 62, and a large current flows through the path E8 in FIG. Can be prevented from flowing.
That is, most of the discharge current is the diode D of FIG.
1 can be used to flow on path E6. This can prevent a large forward current from flowing through the diode D5 of FIG. As a result, it becomes possible to prevent electrostatic breakdown at the portion indicated by E5 in FIG.

Not only the diode (diffusion resistance) of the input buffer as shown in FIG. 10, but also various elements electrically connected in parallel to the output buffer 62 (or the lateral bipolar type protection circuit) can be used as L6. It is desirable to establish a relationship of ≧ L4.

Further, in order to prevent the large current from flowing through the path E8 in FIG. 11 while discharging the current through the path E6 in FIG. 9B, the parasitic resistance R3 in FIG. It is important to set the parasitic resistance R1 to R1 or more. Here, R3 corresponds to the parasitic resistance between the second metal silicide layer 72 of FIG. 10 and the contacts 76 and 78 of the well tap region 80. If R3 ≧ R1 is satisfied, L6 can be made slightly smaller than L4.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, the present invention can be applied to various elements other than the output buffer and the input / output buffer. Further, it can be applied not only to n-type transistors but also to p-type transistors.

The layout of the drain region, the source region, the gate electrode, the well tap region, etc. is not limited to that described in the present embodiment, and various modifications can be made.

The first to third impurity regions (drain region, source region, cathode region) and the first and second metal silicide layers may have a substantially rectangular shape. For example, chamfered edges are provided at the corners. Good.

In the above embodiment, the metal silicide layer is not formed on the surface of the well tap region (fourth impurity region, fifth impurity region) or the source region, but it may be formed. Good. 12, 13, 14 and 15 are conceptual cross-sectional views when a metal silicide layer is formed on the surfaces of the well tap region and the source region. These FIG. 12, FIG. 13, FIG. 14 and FIG.
This corresponds to (B), FIG. 7, FIG. 9 (B), and FIG. 11.

For example, in FIG. 12, the well tap region 14
The third metal silicide layer 13 is formed on the surface of the (fourth impurity region).
0 is formed. Further, the metal silicide layer 132 is formed on the surface of the source region 20.

Further, in FIG. 13, the well tap region 80
The fourth metal silicide layer 17 is formed on the surface of the (fifth impurity region).
2 is formed.

Similar to FIG. 12, also in FIG. 14, the third metal silicide layer 130 is formed on the surface of the well tap region 14 (fourth impurity region), and the metal silicide layer 132 is formed on the surface of the source region 20. And in this case, L4 is
The distance is one side of the first metal silicide layer 30 and the side of the third metal silicide layer 130 facing the one side. L5 is the distance between the other side of the first metal silicide layer 30 and the side of the third metal silicide layer 130 facing the other side.

In FIG. 15, as in FIG. 13, the fourth metal silicide layer 172 is formed on the surface of the well tap region 80 (fifth impurity region). And in this case, L6
Is the distance between one side of the second metal silicide layer 72 and the side of the fourth metal silicide layer 172 facing the one side.

[0072]

[Brief description of drawings]

1A is an example of a plan view of the present embodiment, and FIG. 1B is a conceptual cross-sectional view taken along the line A1-A2 of FIG.

2A and 2B are views for explaining an application example of the present embodiment to an output buffer having no source region on the left side or the right side of the drain region and a lateral bipolar protection circuit. FIG.

FIG. 3 (A) is a diagram for explaining snapback, and FIG. 3 (B) is a diagram for explaining the magnitude of a current passage area.

FIGS. 4A and 4B are diagrams for explaining a relationship between a width W of a transistor and an effective width Weff.

FIG. 5 is a diagram showing an example of a configuration of an input / output buffer.

FIG. 6 is an example of a plan view of a diode parasitically formed on the GND side.

FIG. 7 is a conceptual sectional view taken along line A3-A4 in FIG.

8A and 8B are diagrams for explaining application of a positive surge based on GND and application of a negative surge based on GND, respectively.

9 (A) is an example of a plan view of the present embodiment that establishes a relationship of L5 ≧ L4, and FIG. 9 (B) is FIG.
It is a cross-section conceptual diagram in the A5-A6 line of (A).

FIG. 10 is an example of a plan view of a diode parasitically formed on the GND side.

11 is a conceptual sectional view taken along line A7-A8 in FIG.

FIG. 12 is a conceptual cross-sectional view when a metal silicide layer is provided on the surfaces of the well tap region and the source region in FIG. 1B.

FIG. 13 is a conceptual cross-sectional view when a metal silicide layer is provided on the surface of the well tap region in FIG. 7.

FIG. 14 is a conceptual cross-sectional view in the case where a metal silicide layer is provided on the surfaces of the well tap region and the source region in FIG. 9B.

FIG. 15 is a conceptual cross-sectional view when a metal silicide layer is provided on the surface of the well tap region in FIG. 11.

[Explanation of symbols]

10 Semiconductor substrate 12 p-type well (first region) 14 Well tap region (4th impurity region) 16, 18 contacts 20, 21 Source region (first impurity region) 22 Drain region (second impurity region) 24, 25 Gate electrode 30 First metal silicide layer 32, 34, 35 contacts 38 Element isolation film 40 wiring layers 42 pads 44 surge (positive polarity) 50, 52, 54, 56 sides 68 p-type well (second region) 70 cathode region (third impurity region) 72 Second metal silicide layer 74, 76, 78 contacts 80 well tap region (fifth impurity region) 82, 83, 84, 85 sides 90 surge (negative polarity) 130 Third metal silicide layer 172 Fourth metal silicide layer

Claims (8)

(57) [Claims] 1. A substantially square-shaped first impurity region of a second conductivity type, which is formed in a first region of the first conductivity type and to which a power supply potential is applied, and adjacent to the first impurity region at a given interval. A substantially rectangular second conductivity type second impurity region formed separately, and a substantially rectangular first impurity region formed on the surface of the second impurity region.
A metal silicide layer, a contact connecting the first metal silicide layer and a wiring layer, one side of the first metal silicide layer on the first impurity region side, and the first impurity of the second impurity region. the distance between the side of the region side L1, and the other sides of the first metal silicide layer, the distance between the other sides of the second impurity region when the L2, Ri L2 ≧ L1 der, A substantially rectangular second conductivity formed in the second region of the first conductivity type
-Type third impurity region and a second substantially rectangular shape formed on the surface of the third impurity region.
A metal silicide layer, and a coil connecting the second metal silicide layer and the wiring layer.
And one side of the second metal silicide layer and the third impurity region.
When the distance between one side of the area and L3 is L3, L3 ≧ L1
A semiconductor device characterized in that 2. The first metal silicide layer and the second impurity region are formed in a substantially rectangular shape according to claim 1, and the other side of the first metal silicide layer and the second impurity region is A semiconductor device, characterized in that it is a short side of the first metal silicide layer and the second impurity region formed in a substantially rectangular shape. 3. A substantially square-shaped second impurity region of the first conductivity type, which is formed in the first region of the first conductivity type and to which a power supply potential is applied, and adjacent to the first impurity region by a given distance. A substantially rectangular second conductivity type second impurity region formed separately, and a substantially rectangular first impurity region formed on the surface of the second impurity region.
A fourth impurity of the first conductivity type, which is formed so that at least a part thereof overlaps with the metal silicide layer, the contact connecting the first metal silicide layer and the wiring layer, and the power source potential is applied. L4, the distance between one side of the first metal silicide layer on the first impurity region side and one side of the contact formed on the one side of the fourth impurity region is L4, The distance between the other side of the silicide layer and one side of the contact formed on the other side of the fourth impurity region is L
The semiconductor device is characterized in that L5 ≧ L4 when it is set to 5. 4. The third metal silicide layer according to claim 3, wherein a third metal silicide layer is formed on a surface of the fourth impurity region, and the L4 is one side of the first metal silicide layer on the first impurity region side and the one side. Between the side of the third metal silicide layer and the side of the third metal silicide layer that faces the other side of the first metal silicide layer. A semiconductor device having a distance. 5. The substantially square-shaped second impurity type third impurity region formed in the first conductivity type second region, and the substantially square shape formed in the surface of the third impurity region according to claim 3. Second shape
A metal silicide layer, a contact that connects the second metal silicide layer and the wiring layer, and a first conductivity type fifth electrode that is formed so as to at least partially overlap the second region and to which the power supply potential is applied. L6 ≧ L4, including an impurity region, where L6 is a distance between one side of the second metal silicide layer and one side of the contact formed in the fifth impurity region. Semiconductor device. 6. The third metal silicide layer according to claim 5, wherein a third metal silicide layer is formed on a surface of the fourth impurity region, the fourth metal silicide layer is formed on a surface of the fifth impurity region, and L4 is A distance between one side of the first metal silicide layer on the first impurity region side and a side of the third metal silicide layer facing the one side, wherein L6 is one side of the second metal silicide layer, A semiconductor device characterized in that the distance is from the side of the fourth metal silicide layer facing the one side. 7. The semiconductor device according to claim 1, wherein the first and second impurity regions are a source region and a drain region of an output buffer connected to a pad, respectively. 8. The semiconductor device according to claim 1, wherein the first and second impurity regions are an emitter region and a collector region of a lateral bipolar protection circuit, respectively.