JP4995364B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to a semiconductor integrated circuit device, a semiconductor device, and a method for manufacturing the semiconductor integrated circuit device.
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect type semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device, and more particularly to a driver IC for driving a liquid crystal, a thermal paper resistance, etc., and a power source control IC for a portable device.
[0003]
The present invention also relates to a semiconductor integrated circuit device incorporating a metal wiring having a large current amount per unit width. In particular, it is suitable for a semiconductor integrated circuit device having an output terminal with a narrow pitch.
[0004]
[Prior art]
In the conventional semiconductor integrated circuit device, the gate electrode 11 side end in the channel length direction of the drain region 10 of the transistor constituting the input / output circuit, the end of the contact region 12 electrically connecting the drain region 10 and the metal electrode 14 are provided. The second minimum distance 22 and the third minimum distance 23 between the end opposite to the gate electrode 11 in the channel length direction and the end of the contact region 12 that electrically connects the drain region 10 and the metal electrode 14, The first minimum distance 21 between the end of the drain region 10 of the transistor constituting the input / output circuit in the channel width direction and the end of the contact region 12 that electrically connects the drain region 10 and the metal is provided relatively small. .
[0005]
An example of an input / output circuit transistor of a conventional semiconductor integrated circuit device is shown in FIG. FIG. 2 is a plan view of an insulated gate field effect transistor.
[0006]
The transistor shown in FIG. 2 is provided with a contact region 12 in each of a drain region 10 and a source region 13 that are electrically separated by a gate electrode 11 electrically connected to a metal electrode 16. Each is electrically connected to each of the metal electrodes 14 and 15 to obtain desired electrical characteristics.
[0007]
Since this transistor is directly connected to the input / output terminal, noise from the outside is directly applied to the transistor, and thus the transistor has excellent characteristics of noise resistance from outside. As the method, it has been well known that the second minimum interval is increased, the channel width is increased, or the channel width is decreased.
[0008]
Further, the conventional semiconductor integrated circuit device uses a thick aluminum silicon when using a metal wiring with a large amount of current per unit width, or uses an aluminum copper silicon or copper having a high electromigration resistance, or A method such as using laminated metal wiring has been used.
[0009]
An example of a conventional semiconductor integrated circuit device is shown in FIG. FIG. 7C is a cross-sectional view of an insulated gate field effect type semiconductor integrated circuit device using a thick metal wiring.
[0010]
In a semiconductor integrated circuit device composed of a plurality of field effect transistors, a metal wiring 46 patterned on an interlayer insulating film 40 covering a circuit element provided in the vicinity of the surface of a semiconductor substrate has a thickness of about 1 μm to 3 μm. The protective film 42 is provided by coating the interlayer insulating film 40 and the metal wiring 46.
[0011]
An example of a conventional method for manufacturing a semiconductor integrated circuit device is shown in FIGS. As shown in FIG. 7A, a circuit element is formed near the surface of the semiconductor substrate 31 to form an interlayer insulating film 40 that covers the circuit element, and an opening 43 for electrical connection is formed in the interlayer insulating film 40. In the first step, as shown in FIG. 7B, a wiring layer 44 is formed on the interlayer insulating film 40 with a thick film thickness, and an etching mask material 45 is patterned on the wiring layer 44 to form a wiring layer. Etch 44 is used to remove the wiring layer 44 in an unnecessary region and form the metal wiring 46, and as shown in FIG. 7C, the etching mask material 45 is removed and the metal wiring 46 is removed. A method of manufacturing a semiconductor integrated circuit device has been provided in which a protective film 42 is formed on the upper and interlayer insulating films 40 and an opening is formed in the external terminal connection portion.
[0012]
Further, as shown in FIG. 9, the conventional semiconductor integrated circuit device has a source region 56 and a low concentration drain that are electrically separated by a gate electrode 67 and a gate insulating film 62 in the vicinity of the surface of the first conductivity type semiconductor substrate 61. A region 55 is provided, a high concentration drain region 53 is provided in a region surrounded by the low concentration drain region 55, a well region 54 is provided inside the low concentration drain region 55, and a thick oxide film 52 is formed above the low concentration drain region. A drain metal electrode 58 electrically connected to the high-concentration drain region 53 via the interlayer insulating film 59 is provided above the thick oxide film 52, and a protective film 60 having a pad opening 61 on the drain metal electrode 58. Is provided, and the space between the pad opening 61 and the gate electrode 57 is sufficiently widened so that impact stress during mounting by wire bonding is directly applied to the element. Strange design has been made. Further, the gap between the drain metal electrode 58 to be wire-bonded and the metal electrode 63 electrically isolated from the pad opening 61 is sufficiently widened, and impact stress during mounting by wire bonding causes the protective film 60 on the metal electrode 63 to be affected. It was designed not to be directly applied to.
[0013]
[Problems to be solved by the invention]
However, the conventional semiconductor integrated circuit device has the following problems.
That is, in the case of the insulated gate field effect semiconductor device shown in FIG. 2, in order to obtain desired noise resistance (including electrostatic resistance), it is necessary to design the channel width to be large. It was difficult to reduce the size.
[0014]
Further, when there are many input / output terminals, an increase in chip size as a semiconductor integrated circuit device has significantly increased manufacturing costs.
[0015]
Further, the conventional semiconductor integrated circuit device has the following problems.
That is, in the case of the insulated gate field effect semiconductor integrated circuit device using the thick metal wiring shown in FIG. 7, when the metal wiring is selectively removed by etching, the etching mask material and the metal wiring to be etched Therefore, when the metal wiring is formed thick, the thickness of the etching mask material is at least 1.5 times the selection ratio from the metal wiring film thickness in consideration of the in-plane distribution of the film thickness of the etching mask material. It is necessary to set to 0 times. For this reason, it is difficult to form a fine processing width of the metal wiring.
[0016]
Also, in the case of a method such as using aluminum copper silicon or copper having high electromigration resistance for metal wiring or using laminated metal wiring, the electromigration resistance is significantly improved, the processing accuracy is improved, and the manufacturing cost is reduced. It was difficult.
[0017]
Further, the conventional semiconductor integrated circuit device has the following problems.
That is, in the case of the conventional insulated gate field effect semiconductor device shown in FIG. 9, the design is such that the impact stress during mounting by wire bonding is not directly applied to the protective film on the metal electrodes having different elements and potentials. For this reason, it has been difficult to reduce the chip size of the semiconductor integrated circuit device.
[0018]
Further, it has been impossible to lay out elements such as an output driver and a protective circuit between adjacent driver output terminals at a narrow pitch.
[0019]
Further, when there are many input / output terminals, an increase in chip size as a semiconductor integrated circuit device has significantly increased manufacturing costs.
[0020]
[Means for Solving the Problems]
Therefore, the present invention uses the following means in order to solve the above problems.
[0021]
In a semiconductor integrated circuit composed of a plurality of MOS field effect transistors,
The first minimum distance between the channel width direction end of the drain region of the MOS transistor constituting the input / output circuit and the contact region end electrically connecting the drain and the metal is defined as the MOS transistor constituting the input / output circuit. The drain region is provided larger than the second minimum distance between the gate electrode side end in the channel length direction and the contact region end electrically connecting the drain and the metal.
[0022]
In addition, the first minimum interval is set to be 1 μm or more larger than the second minimum interval.
[0023]
Further, the MOS transistor is composed of an off-type transistor that is always in an off state and an input-type transistor that receives an input signal.
[0024]
Further, the MOS transistor is composed of an off-type transistor that is always in an off state and an output-type transistor that outputs an output signal.
[0025]
Further, the total channel width of the MOS transistors electrically connected to the same input / output terminal is 140 μm or less.
[0026]
Further, the first minimum distance between the channel width direction end of the drain region of the MOS transistor and the end of the contact region that electrically connects the drain and the metal is the channel of the drain region of the MOS transistor constituting the input / output circuit. It was set larger than the third minimum distance between the end portion on the opposite side to the gate electrode in the long direction and the contact region end portion for electrically connecting the drain and the metal. In addition, the first minimum interval is set to be 1 μm or more larger than the third minimum interval.
[0027]
Further, the MOS transistor is composed of an off-type transistor that is always in an off state and an input-type transistor that receives an input signal.
[0028]
Further, the MOS transistor is composed of an off-type transistor that is always in an off state and an output-type transistor that outputs an output signal.
[0029]
Further, the total channel width of the MOS transistors electrically connected to the same input / output terminal is 140 μm or less.
[0030]
Therefore, the present invention uses the following means in order to solve the above problems.
[0031]
In a semiconductor integrated circuit composed of a plurality of field effect transistors,
A second wiring that is in contact with an upper portion and a side wall portion of the first wiring and is electrically connected via a contact surface between the first wiring and the upper portion of the first wiring or both the upper portion and the side wall portion is provided.
[0032]
The second wiring is provided with a processing width of 0.1 μm or more, and the first wiring is provided with a processing width of 3 μm or more.
[0033]
The second wiring was provided with a thickness of 300 nm or more, and the first wiring was provided with a thickness of 1 μm or more.
[0034]
In the method for manufacturing a semiconductor integrated circuit device of the present invention,
Forming a circuit element near the surface of the semiconductor substrate, forming an insulating film for coating the circuit element, and forming an opening for electrical connection in the insulating film;
Forming a first wiring layer on the insulating film, patterning an etching mask material on the first wiring layer, etching the first wiring layer to remove the first wiring layer in an unnecessary region; A second step of forming a first wiring;
The etching mask material is removed, a second wiring layer is formed on the first wiring and the insulating film, the etching mask material is patterned on the second wiring layer, and the second wiring layer is etched. A method of manufacturing a semiconductor integrated circuit device having a third step of removing the second wiring layer in an unnecessary region and forming a second wiring is used.
[0035]
In the second step of the method of manufacturing a semiconductor integrated circuit device,
The first wiring layer is formed with a laminated structure of a refractory metal layer such as titanium or titanium nitride and a conductive material layer mainly composed of aluminum, and an etching mask material is patterned on the first wiring layer. The conductive material layer mainly composed of aluminum is removed by etching the conductive material layer mainly composed of aluminum, and the high melting point of the conductive material layer mainly composed of aluminum in the first wiring and the first wiring layer is removed. As a process of forming the metal layer portion,
In the third step, the etching mask material is removed, and a second wiring layer is formed on the conductive material layer portion mainly composed of aluminum of the first wiring and the refractory metal layer portion of the first wiring layer. The etching mask material is patterned, and the second wiring layer is etched to remove the second wiring layer in the unnecessary region and the refractory metal layer portion of the first wiring layer in the unnecessary region, It was set as the process of forming.
[0036]
In the step of forming an opening for electrical connection in the insulating film in the first step of the method for manufacturing a semiconductor integrated circuit device
A method of manufacturing a semiconductor integrated circuit device having a step of filling a conductive material such as tungsten, aluminum, or copper in the opening is used.
[0037]
Therefore, the present invention uses the following means in order to solve the above problems.
[0038]
A source region and a low concentration drain region electrically isolated by a gate electrode and a gate insulating film are provided near the surface of the first conductivity type semiconductor substrate, and a high concentration drain region is provided in a region surrounded by the low concentration drain region. A well region is provided inside the concentration drain region, a thick oxide film is provided above the low concentration drain region, and the high concentration drain region is electrically connected to the thick oxide film, the high concentration drain region, and the gate electrode via an interlayer insulating film. In the semiconductor integrated circuit device in which the drain metal electrode connected to each other and the protective film having the pad opening on the drain metal electrode are provided, the distance between the pad opening and the gate electrode is set to 10 μm or less.
[0039]
Further, the distance between the pad opening and the metal wiring was set to 12 μm or more.
[0040]
Further, a low concentration drain region and a well region are provided below the pad opening.
[0041]
The drain metal electrode was provided with a film thickness of 1.5 μm to 3 μm.
[0042]
Moreover, the drain metal electrode was provided with the metal containing copper.
[0043]
Further, the gap between the pad opening and the gate electrode was set to 1 μm or more.
[0044]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0045]
The semiconductor integrated circuit device of the present invention shown in FIG. 1 is a transistor used in an input / output circuit of a semiconductor integrated circuit composed of a plurality of field effect transistors. And the first minimum distance 21 between the end of the contact region 12 for electrically connecting the metal and the metal.
[0046]
Hereinafter, a semiconductor integrated circuit device of the present invention will be described in detail with reference to the drawings.
[0047]
FIG. 1 is a plan view of a transistor constituting an input / output circuit of a semiconductor integrated circuit device of the present invention.
[0048]
In the transistor shown in FIG. 1, a contact region 12 is provided in each of a drain region 10 and a source region 13 that are electrically separated by a gate electrode 11, and the drain region 10 and the source region 13 are electrically connected to metal electrodes 14 and 15, respectively. To obtain desired electrical characteristics. Since this transistor is directly connected to the input / output terminal, noise from the outside is directly applied to the transistor, and thus the transistor has excellent characteristics of noise resistance from outside.
[0049]
In the present invention, the first minimum distance 21 between the end of the drain region 10 in the channel width direction and the end of the contact region 12 that electrically connects the drain region 10 to the metal is defined as the gate electrode in the channel length direction of the drain region 10. 11 side end, drain region 10 and metal electrode 14 are electrically connected to the end of contact region 12 second minimum distance 22 and channel length direction opposite to gate electrode 11, drain region 10 and metal Because it is provided larger than the third minimum distance 23 with the end of the contact region 12 that electrically connects the electrode 14,
The locality of the overcurrent generated when electrostatic noise is applied to the drain region 10 can be reduced, and the breakdown of the transistor due to local heat generation can be suppressed.
[0050]
Conventionally, as the technique, it is well known that the second minimum interval 22 is increased or the channel width is increased. In the conventional technique, in order to obtain a practically preferable electrostatic resistance, for example, The second minimum distance 22 between the end of the drain region 10 in the channel length direction on the side of the gate electrode 11 and the end of the contact region 12 of the drain region 10, the end opposite to the gate electrode 11, and the end of the contact region 12 of the drain region 10 Even when the third minimum distance 23 between the transistors is set to about 7 μm or more, it is necessary to configure the total channel width of the transistors electrically connected to the same input / output terminal to be 200 μm or more.
[0051]
However, when the first minimum interval 21 between the channel width direction end of the drain region 10 and the end of the contact region 12 of the drain region 10 is set larger than the second minimum interval 22 and the third minimum interval 23, Even if the second minimum interval 22 and the third minimum interval 23 are about 7 μm, it is possible to configure the total channel width of transistors electrically connected to the same input / output terminal to be 140 μm or less. Further, although it depends on a difference in mounting conditions, a device, and a process configuration, it can be configured to be about 120 μm or less or about 100 μm or less. Further, if the first minimum interval 21 is made approximately 1 μm larger than the second minimum interval 22 and the third minimum interval 23, the effect is further increased. Further, when the phenomenon that determines the static drain withstand voltage of the transistor is the junction breakdown between the drain and the semiconductor substrate region 1, the relationship between the first minimum interval 21 and the third minimum interval 23 affects the electrostatic resistance. To make it larger. In addition, when the phenomenon that determines the static drain withstand voltage of the transistor is the surface breakdown caused by the gate electrode, the relationship between the first minimum interval 21 and the second minimum interval 22 has a greater influence on the electrostatic resistance. To do.
[0052]
Up to this point, an embodiment effective when the power supply voltage is about 3 V or less, about 5 V or less, or about 7 V or less has been described. However, the present invention can achieve the same effect when the power supply voltage is about 7 V or more and about 40 V or less. It is done. A similar effect can be obtained when the voltage is about 40 V or more.
[0053]
However, in the case of a transistor having an LDD structure having a side spacer on the side wall of the gate electrode 11 used when the power supply voltage or the applied electric field is large, the second minimum interval 22 and the third minimum interval rather than the first minimum interval 21 are used. In some cases, the electrostatic resistance becomes higher when the interval 23 is set larger.
[0054]
In addition, when the static drain breakdown voltages on the four sides of the outer periphery of the drain region 10 are approximately the same, the effect of the present invention is further increased.
[0055]
Furthermore, when electrostatic noise is applied, it is known that the parasitic bipolar transistor composed of the drain region 10, the semiconductor substrate region 1, and the source region 13 causes the noise charge to escape to the ground potential. The effect of the present invention is significant by increasing the distance between the end of the drain region 10 and the contact region 12 in the vicinity of the parasitic bipolar transistor having a small current capacity leading to breakdown. Such an effect becomes remarkable when the power supply voltage is between 20V and 40V.
[0056]
That is, the essence of the present invention is that overcurrent is prevented from flowing locally in a region having high resistance when electrostatic noise is applied.
[0057]
The effect of the conductivity type of the transistor of the present invention is large when it is an N-channel type, but a certain degree of effect is also obtained when it is a P-channel type.
[0058]
FIG. 3 shows another embodiment of the present invention. This will be described in detail with reference to the drawings.
[0059]
When configuring a semiconductor integrated circuit device, an input / output element and an electrostatic protection element are connected to the external connection terminal. These elements have some resistance against external noise and static electricity. In order to provide such resistance, the current capacity of the current path for noise and static electricity is increased, or a path for discharging noise and static electricity to the power supply terminal (VDDorVSS) by an electrostatic protection element such as a diode or a bipolar transistor is provided. The present invention has an effect of increasing current capacity against surge and static electricity of an input / output element (particularly a MOS transistor) and an electrostatic protection element (particularly a gate-off type MOS transistor).
[0060]
The noise and static electricity resistance of a MOS transistor (hereinafter referred to as MOS Tr.) Is generally determined by the current capacity of a parasitic diode and a parasitic bipolar transistor (hereinafter referred to as parasitic bipolar Tr.). Parasitic diodes and parasitic bipolar Tr. The current capacity is determined by the current path volume and current path uniformity of the semiconductor region exposed directly to the external input. The semiconductor element shown in FIG. 3 has particularly improved current path uniformity against noise and static electricity.
[0061]
FIG. 3 shows an MOSTr. 2 which constitutes an input / output element or an electrostatic protection element of the semiconductor integrated circuit device of the present invention and has two gate electrodes 11. FIG.
[0062]
The input / output element or electrostatic protection element of the semiconductor integrated circuit device of the present invention is provided with a drain region 10 electrically isolated by a channel region 18 and an element isolation region 17 under the gate electrode 11 in the vicinity of the surface of the semiconductor substrate 1. Two source regions 13 electrically isolated by the region 18 and the element isolation region 17 are provided, and the drain region 10, the source region 13, and the gate electrode 11 are respectively connected via the contact region 12 for electrical wiring. A metal electrode 14 is provided. Although not shown here, a metal electrode is provided via a contact region for electrical wiring in the element isolation region 17. Although not shown here, the gate electrode 11 and the element are provided. The isolation region 17 is electrically connected via the metal electrode 14, and although not shown here, the source region 13 and the drain region 10. Lower semiconductor region and the channel region 18 is constructed by connecting an element isolation region 17 to electrically have the same conductivity type and the element isolation region 17.
[0063]
In the layout configuration as shown in FIG. 3, the electrical isolation between the drain region 10 and the element isolation region 17 is performed by the junction diode at the end of the drain region 10 in the channel width direction and the gate at the end of the drain region 10 in the channel length direction. The electrode 11 is carried by a junction diode having a field effect.
[0064]
In general, input / output elements and electrostatic protection elements of a semiconductor integrated circuit device have a channel width of about 200 μm to 400 μm in order to ensure current capacity. Therefore, a junction diode (hereinafter referred to as channel width direction) is formed. The current path of noise and static electricity (referred to as a diode) is significantly smaller than the current path of a junction diode (hereinafter referred to as a channel length direction diode) having a field effect of the gate electrode 11 at the end of the channel length direction. End up. This configuration degrades the current path uniformity against noise and static electricity. If the isolation voltage of the channel width direction diode is lower than the isolation voltage of the channel length direction diode, the current path uniformity will be further deteriorated. This significantly deteriorates the input / output tolerance of the semiconductor integrated circuit device.
[0065]
Therefore, a configuration in which the isolation breakdown voltage of the channel width direction diode is higher than the isolation breakdown voltage of the channel length direction diode is conceivable. Although this method improves the current path uniformity against noise and static electricity under specific conditions in the relationship between the current-voltage characteristics of the channel length direction diode and the current-voltage characteristics of the channel width direction diode, Lowering the impurity concentration results in a decrease in the current capacity at the end of the drain region 10 in the channel width direction, and adversely affects the current-voltage characteristics of the channel width direction diode.
[0066]
A schematic diagram of this relationship is shown in FIG. Even if the current capacity of the channel length direction diode is large, if the current capacity of the channel width direction diode is small, a current is generated in the channel width direction diode before the applied electrostatic current amount flows out by the channel length direction diode, and the current capacity is reduced. An outline of the phenomenon that causes destruction when the current exceeds the value is shown.
[0067]
That is, it is not possible to improve the resistance to noise or static electricity by simply increasing the isolation voltage of the diode in the channel width direction. Optimal design is necessary based on the correlation between the channel length direction diode characteristics and the channel width direction diode characteristics.
[0068]
All voltages applied to the input / output element or electrostatic protection element based on the expected amount of noise and static electricity in the actual mounting environment and usage environment of the semiconductor integrated circuit device and the resistance and capacitance values of the current path Alternatively, it is necessary to compare the channel length direction diode characteristics and the channel width direction diode characteristics under current conditions, and to make the channel width direction diode not to be destroyed under all conditions. In the case of a MOS type semiconductor integrated circuit device (in particular, the minimum processing width is 0.6 to 3.0 μm, the channel length direction diode isolation withstand voltage is 6 to 40 V, and the channel width direction diode isolation withstand voltage is 3 to 10 V from the channel length direction diode isolation withstand voltage. If the total width of the channel length direction diodes of the input / output element or the electrostatic protection element is 200 um to 400 um, the optimum condition is obtained.
[0069]
Such a method is not preferable because it greatly increases the area of the input / output element or the electrostatic protection element and becomes a major problem in device design, which adversely affects the cost of developing and manufacturing the semiconductor integrated circuit device.
[0070]
FIG. 3 is a plan view of the input / output element and the electrostatic protection element of the semiconductor integrated circuit device of the present invention shown in FIG. 3, the second minimum distance 22 being the shortest distance between the channel length direction diode and the contact region 12 of the drain region 10. A first minimum distance 21 that is the shortest distance between the channel width direction diode and the contact region 12 of the drain region 10 is indicated. In the present invention, a method has been found in which most of the charge due to noise or static electricity is caused to flow out of the channel length direction diode by the difference in length between the first minimum interval 21 and the second minimum interval 22.
[0071]
As described above, the drain region 10 directly connected to the external input terminal has noise and static current paths having different characteristics, that is, a channel width direction diode and a channel length direction diode. It is difficult to have path uniformity. However, in the present invention, if the first minimum interval 21 is configured to be more than twice as large as the second minimum interval 22, most of the current path of noise and static electricity is limited to the channel length direction diode, so that the current of the channel width direction diode There is no need to increase the capacity. That is, if the current capacity of the channel length direction diode is set larger than the expected noise or static electricity amount, noise and static electricity resistance can be obtained. In this case, the effect that the width of the sum of the channel length direction diodes conventionally required from 200 μm to 400 μm is about 100 μm or less is sufficient. In addition, the total width of the channel length direction diodes can be configured to be 140 μm or less simply by configuring the first minimum interval 21 to be greater than the second minimum interval 22 by about 1 μm or more.
[0072]
Here, the total width of the diodes in the channel length direction is the MOSTr. Is the sum of the channel widths.
[0073]
In the case of a semiconductor device having a structure in which the drain region 10 is surrounded by the gate electrode 11 as shown in FIG. 5, the drain region 10 and the element isolation region 17 are electrically separated from each other by the gate electrode in the channel length direction end. 11 is maintained by a junction diode having an electric field effect, and the uniformity of the current path of noise and static electricity is obtained. However, since the volume of the current path in the channel width direction remains small, the fourth minimum interval 24 needs to be configured larger than the second minimum interval 22.
[0074]
Although not shown here, in the case of a semiconductor device having channel regions in all four directions surrounding the drain region, the current capacity of the corner portion becomes small. Therefore, the distance between the contact region of the corner portion and the corner is the channel length. It is necessary to design larger than the shortest distance between the direction diode and the contact region of the drain region.
[0075]
The semiconductor integrated circuit device of the present invention shown in FIG. 6E is a semiconductor integrated circuit composed of a plurality of field effect transistors, and a CMOS type or bipolar type circuit element is formed near the surface of the semiconductor substrate 31. It is in contact with the upper portion and side wall portion of the first metal wiring 50 provided on the interlayer insulating film 40 that covers the element, and electrically through the first metal wiring 50 and the upper portion or the contact surface of the side wall portion. The connected second metal wiring 52 is provided, the second metal wiring 52 is provided with a processing width of 0.1 μm or more, and the first metal wiring 50 is provided with a processing width of 2 μm or more. Further, the second metal wiring 52 is provided with a film thickness of 0.6 μm or more, and the first metal wiring 50 is provided with a film thickness of 0.8 μm or more.
[0076]
Here, the second metal wiring 52 can be provided with a processing width of 0.5 μm or more and about 10 μm or less, but may be provided with a processing width of about 0.8 μm or more and about 10 μm or less.
[0077]
Further, this technique can be realized even if the first metal wiring 50 is provided with a processing width of about 3 μm or more and about 500 μm or less, but it may be provided with a processing width of about 5 μm or more and about 50 μm or less.
[0078]
Further, the second metal wiring 52 can be provided with a film thickness of 300 nm or more and about 1 μm or less, but this technique can be realized, but it may be provided with a film thickness of about 500 nm or more and 800 nm or less.
[0079]
In addition, this technique can be realized even if the first metal wiring 50 is provided with a film thickness of 500 nm or more and about 5 μm or less, but it may be provided with a film thickness of 1 μm or more and about 3 μm or less.
[0080]
The difference in film thickness between the first metal wiring 50 and the second metal wiring 52 is that the etching selectivity between the etching mask material 53 and the second metal wiring 52 on the first metal wiring 50 region and the film thickness ratio are It is determined by the processing accuracy of the second metal wiring 52.
[0081]
Further, since the first metal wiring layer 50 is covered with the second metal wiring layer 52, the film thickness of the first metal wiring layer 50 due to the etching of the second metal wiring 52 does not occur.
[0082]
In the method for manufacturing the semiconductor integrated circuit device of the present invention shown in FIGS.
Forming a CMOS type or bipolar type circuit element in the vicinity of the semiconductor substrate surface, forming an interlayer insulating film 40 for coating the circuit element, and forming an opening 43 for electrical connection in the insulating film;
A first metal layer is formed on the interlayer insulating film 40, a first etching mask material 51 is patterned on the first metal layer, and an unnecessary region of the first metal layer is removed by etching. A second step of forming the metal wiring 50,
The first etching mask material 51 is removed, a second metal layer is formed on the first metal wiring 50 and the interlayer insulating film 40, and the second etching mask material 53 is patterned on the second metal layer. A third step of removing the unnecessary second metal layer by etching the second metal layer and forming the second metal wiring layer 52;
A fourth step of forming a passivation film 54 after removing the second etching mask material 53;
A method for manufacturing a semiconductor integrated circuit device having the above is used.
[0083]
In the second step of the method of manufacturing a semiconductor integrated circuit device,
The first metal layer is formed with a laminated structure of a high-melting point metal layer such as titanium or titanium nitride and a low-resistance conductive material layer mainly composed of aluminum, and a first etching mask material 51 is formed on the first metal layer. A step of patterning, removing unnecessary regions by etching, and forming a low-resistance conductive material layer portion mainly composed of aluminum of the first metal wiring layer 50 and a refractory metal layer portion of the first metal wiring layer 50 age,
In the third step, the first etching mask material 51 is removed, and the second metal layer is formed on the first metal wiring layer 50 as a low resistance mainly composed of a refractory metal layer such as titanium or titanium nitride and aluminum. It is also possible to form the second metal wiring layer 52 by forming a laminated structure with a conductive material layer, patterning the second etching mask material 53, removing unnecessary regions of the second metal layer by etching. good.
[0084]
In the step of forming the opening 43 for electrical connection in the interlayer insulating film 40 in the first step of the method for manufacturing the semiconductor integrated circuit device
In some cases, a method of manufacturing a semiconductor integrated circuit device having a step of embedding a conductive material such as tungsten, aluminum, or copper in the opening 43 may be used.
[0085]
In the method for manufacturing the semiconductor integrated circuit device of the present invention shown in FIGS. 6A to 6E, the film thicknesses of the first metal wiring layer 50 and the second metal wiring layer 52 are, for example, 2.0 μm. The first metal wiring layer 50 can be formed thick as 0.8 um. Therefore, when forming a semiconductor integrated circuit device, the region where the first metal wiring layer 50 exists can be configured with a large allowable current amount. In other words, if the first metal wiring layer 50 is formed on a wiring that requires a large amount of current, the wiring layer can be configured with a small area, so that the chip size of the semiconductor integrated circuit device can be reduced.
[0086]
Further, when the first metal wiring layer 50 is formed by etching in the second step, the selectivity and the film thickness ratio between the first metal wiring layer 50 and the first etching mask material 51 become a problem. The etching amount of the first metal layer is set so as to be over-etched by about 20 to 50%, thereby preventing etching residue due to manufacturing variations. Since the metal as the material to be etched is formed thick, the total etching time is significantly increased, but the first etching mask material 51 needs to remain sufficiently at the end of etching. That is, either a mask material having a sufficiently high selection ratio of the first etching mask material 51 to the material to be etched is used, or an etching method in which the selection ratio is sufficiently large is used. As an etching method with a sufficiently high selectivity, wet etching with a mixture of an acidic solution such as phosphoric acid, or dry etching using an atmosphere in which the bias on the semiconductor substrate side is lowered or an additive gas is mixed is preferable. .
[0087]
Generally, such an etching method has a very large variation in processing accuracy, and a fine wiring of 1 μm or less cannot be used. Therefore, a plurality of metal wiring layers are formed according to applications. In this case, three photo processes are required to form a contact connecting a plurality of metal wiring layers and metal wiring layers.
[0088]
However, in the present invention, the thick wiring can be formed by the first metal wiring layer 50 and the fine wiring can be formed by the second metal wiring layer 52, and a contact for connecting the generally used metal wiring layers is required. Therefore, the semiconductor integrated circuit device can be easily formed by two photo processes.
[0089]
The semiconductor device of the present invention shown in FIG. 8 is a schematic sectional view of a part of an external output pad and an output driver of a semiconductor integrated circuit device composed of a plurality of external output pads, an output driver, and a control circuit.
[0090]
A source region 66 and a low concentration drain region 65 electrically isolated by a gate electrode 67 and a gate insulating film 72 are provided near the surface of the first conductivity type semiconductor substrate 61, and a high concentration is provided in a region surrounded by the low concentration drain region 65. A drain region 63 is provided, a well region 64 is provided inside the low concentration drain region 65, a thick oxide film 62 is provided above the low concentration drain region 65, and the thick oxide film 62, the high concentration drain region 63, and the gate electrode 72 A semiconductor integrated circuit device in which a drain metal electrode 68 electrically connected to the high concentration drain region 63 via an interlayer insulating film 69 is provided above, and a protective film 70 having a pad opening 71 is provided on the drain metal electrode 68. , The distance between the pad opening 71 and the gate electrode 67 was 10 μm or less.
[0091]
At the time of mounting by wire bonding, the wire may be struck on a part of the protective film 70 out of the pad opening 71. In this case, impact stress due to bonding may be applied to the protective film 70, the gate electrode 67, the gate insulating film 72, the low-concentration drain region 65, and the like, and the electrical characteristics of the transistor may vary. Therefore, conventionally, the distance between the pad opening 71 and the gate electrode 67, the gate insulating film 72, the low-concentration drain region 65, and the like has been set to about 13 μm, which is larger than the alignment accuracy of wire bonding. Therefore, in the case of a semiconductor integrated circuit device having a large number of external output pads with a narrow pitch, elements such as an output driver and a protection circuit cannot be laid out in the vicinity of the external output pads, particularly between adjacent pads.
[0092]
In the present invention, since the drain metal electrode 68 to be wire-bonded is extended above the output transistor laid out in the vicinity of the pad opening, even if an impact stress due to bonding is applied above the output transistor, the drain metal electrode 68. However, it absorbs shock stress and does not impair the electrical characteristics of the transistor. Therefore, the distance between the pad opening 71 and the gate electrode 67 can be made 10 μm or less. Although it can be set to about 5 μm or less or about 1 μm or less, it is preferably set to about 6 μm or less for practical use as a countermeasure against external electrostatic noise.
[0093]
Further, since the bonding center having the greatest impact stress due to wire bonding is set at the pad opening, a low-concentration drain region 65 having the same potential as the drain metal electrode 68 is formed below the thick oxide film 62 immediately below the pad opening. A well region 64 is provided to prevent a leak current due to a defect due to impact stress caused by bonding.
[0094]
Further, since the impact stress due to wire bonding increases as it approaches the bonding center, it is recommended that the interval between the pad opening 71 and the gate electrode 67 be about 1 μm to 3 μm or more in practical use.
[0095]
On the other hand, the metal electrode 73 that is electrically separated from the drain metal electrode 68 to be wire-bonded is only provided with a protective film 70 having a low resistance to impact stress due to bonding, so that the pad opening 71 and the metal electrode It is desirable to set the distance from 73 to about 12 μm or more, which is larger than the alignment accuracy of wire bonding.
[0096]
In order to further improve the resistance to impact stress due to bonding, the drain metal electrode 58 may be provided with a film thickness of 1.5 μm to 3 μm. Further, a laminated structure of metal films may be used. Further, the drain metal electrode 68 is provided with a metal containing copper. For example, there are aluminum silicon copper alloy and copper.
[0097]
FIG. 8 of the present invention shows the external connection pad area and the output driver. However, since this description enables the element to be installed in the vicinity of the external connection pad area, it is installed in the vicinity of the external connection pad area. There is no problem whether the element to be used is a protective element or a control element.
[0098]
FIG. 8 shows a part of the external connection pad region. It is preferable to have the same configuration on the four sides of the top, bottom, left and right with the pad opening 71 as the center. Moreover, it is possible to install only one side, to install on a concentric circle, to install in an octagonal shape, to install only two sides, to install only three sides.
[0099]
Further, the present invention is extremely effective when used in an IC for a thermal head driver having a 192-bit output driver.
[0100]
Each of the embodiments described so far can be used in combination with another embodiment.
[0101]
【Effect of the invention】
As described above, according to the present invention, in the semiconductor integrated circuit device, since the electrostatic resistance of the input / output circuit transistor can be increased, an input / output protection circuit having high reliability can be easily formed with a small channel width. . For this reason, there is an effect of reducing the manufacturing cost by reducing the chip size.
[0102]
In addition, as described above, in the present invention, in the semiconductor integrated circuit device, the metal wiring can be partially thickened by two photo processes and an etching process. Metal wiring with good width controllability can be easily formed. This has the effect of reducing the manufacturing cost and reducing the chip size.
[0103]
In addition, as described above, the present invention makes it possible to install an element in the vicinity of the external connection pad region in the semiconductor integrated circuit device, so that the chip size can be easily reduced. For this reason, the manufacturing cost can be reduced by reducing the chip size.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a semiconductor integrated circuit device of the present invention.
FIG. 2 is a schematic plan view of a conventional semiconductor integrated circuit device.
FIG. 3 is a schematic plan view of a semiconductor integrated circuit device of the present invention.
FIG. 4 is a voltage-current characteristic diagram of the semiconductor integrated circuit device of the present invention.
FIG. 5 is a schematic plan view of a semiconductor integrated circuit device of the present invention.
FIG. 6 is a schematic cross-sectional view in order of the manufacturing process of the semiconductor integrated circuit device of the present invention.
FIG. 7 is a schematic cross-sectional view in order of the manufacturing process of a conventional semiconductor integrated circuit device.
FIG. 8 is a schematic sectional view of a semiconductor integrated circuit device of the present invention.
FIG. 9 is a schematic cross-sectional view of a conventional semiconductor integrated circuit device.
[Explanation of symbols]
1 Semiconductor substrate area
10 Drain region
11 Gate electrode
12 Contact area
13 Source area
14 Metal electrode
17 Device isolation region
18 channel region
21 First minimum interval
22 Second minimum interval
23 Third minimum interval
24 4th minimum interval
31 Semiconductor substrate
40 Interlayer insulation film
42 Protective film
43 Openings for electrical connection
44 Wiring layer
45 Etching mask material
46 Metal wiring
50 First metal wiring layer
51 First etching mask material
52 Second metal wiring layer
53 Second etching mask material
61 Semiconductor substrate
62 Thick oxide film
63 High concentration drain region
64-well region
65 Low concentration drain region
66 Source region
67 Gate electrode
68 Drain metal electrode
69 Interlayer insulation film
70 Protective film
71 Pad opening
72 Gate oxide film
73 Metal wiring

Claims (6)

A first conductivity type semiconductor substrate;
A gate electrode disposed via a gate insulating film provided on the surface of the first conductive type semiconductor substrate;
A source region of a second conductivity type provided on the first conductivity type semiconductor substrate under the gate electrode and electrically separated by the first conductivity type semiconductor substrate, and a pad region disposed above the source region. A low-concentration drain region having a size that can be formed;
A high-concentration drain region of a second conductivity type provided in a region surrounded by the low-concentration drain region;
A second conductivity type well region provided only below the lightly doped drain region and the heavily doped drain;
A thick oxide film provided on the entire upper surface of the low-concentration drain region;
A drain metal electrode electrically connected to the high-concentration drain region, provided on the thick oxide film via an interlayer insulating film, and further extending to cover the gate electrode via the interlayer insulating film When,
A source electrode provided to be electrically separated from the drain metal electrode at a distance;
A pad provided on the drain metal electrode so that a part of the drain metal electrode located on the low-concentration drain region opposite to the gate electrode through the high-concentration drain is used as the pad region. A protective film having an opening,
The gate electrode continuously covers from the source region to the high-concentration drain region through the gate insulating film,
The pad area is an output terminal;
The gate electrode is controlled by a control circuit;
The semiconductor integrated circuit device, wherein the source electrode is disposed farther than the drain metal electrode when viewed from the pad opening. 2. The semiconductor integrated circuit device according to claim 1, wherein an interval between the pad opening and the source electrode is 12 [mu] m or more.   2. The semiconductor integrated circuit device according to claim 1, wherein the drain metal electrode is provided in a thickness of 1.5 to 3 [mu] m.   2. The semiconductor integrated circuit device according to claim 1, wherein the drain metal electrode is provided by a metal containing copper.   2. The semiconductor integrated circuit device according to claim 1, wherein an interval between the pad opening and the gate electrode is 1 [mu] m or more.   2. The semiconductor integrated circuit device according to claim 1, wherein an interval between the pad opening and the gate electrode is 10 [mu] m or less.

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