JP5429764B2 - Chip and chip manufacturing method - Google Patents

Description

BACKGROUND OF THE INVENTION
This application is a continuation-in-part of Patent Application No. 09/251, filed on Feb. 17, 1999, which is a continuation-in-part of Patent Application No. 09 / 216,791 filed on Dec. 21, 1998. , No. 183.

The present invention relates to a chip and a method for manufacturing the chip.

[Prior art]
Improvements in the performance of semiconductor devices are typically obtained by reducing the geometric dimensions of the integrated circuit, which results in a reduced cost per die, while at the same time some of the performance of the semiconductor device. The surface is improved. Metal connections that connect integrated circuits to other circuits or systems are relatively more important, but for further miniaturization of ICs (integrated circuits), the performance of the circuit Increase adverse effects. The parasitic capacitance and resistance of the metal interconnect increases, which significantly degrades chip performance. Most important in this regard is the voltage drop along the RC delay of the feed and ground bus (bus) or electrical signal path. Attempting to reduce resistance using wider metal lines increases the capacitance of these wires.

In order to solve this problem, one attempt has been made to develop a low resistance metal (eg, copper) for wires with a low dielectric material between the signal lines. The current practice is to form a metal interconnect network under the passivation or passivation layer, but this attempt limits the interconnect network to fine wire interconnects, and in this regard, parasitic capacitance And high line resistivity. The latter two parameters reduce the performance of the device due to their relatively large values, and the effect is even more severe for higher frequency applications and for long interconnect lines used, for example, for clock wiring lines. Also, the thin wire interconnect metal typically cannot carry large current values that require ground and feeder buses.

As noted above, the concern for the semiconductor field is to create interconnect line formation methods that remove typical limitations imposed on interconnect wires (eg, undesirable parasitic capacitance and high interconnect line resistance). Is to provide. The present invention provides such a method. In this regard, it can be pointed out that the currently used (conventional) thin wire interconnect system formed under the passivation layer is similar to a city street. The post-passivation interconnection scheme of the present invention can be regarded as a highway between cities.

Referring now to the drawings illustrating the prior art, FIG. 1 is a cross-sectional view of a silicon substrate having a surface with a conductive interconnect network formed thereon. The structure shown in cross section in FIG. 1 deals only with a conventional power supply and ground wiring network and is limited to this. Various features highlighted in FIG. 1 are as follows.

Reference numeral 40: A silicon substrate having a surface on which an interconnection network is formed Reference numeral 42: An exemplary number of semiconductor circuits formed in or on the surface of the substrate 40 Reference numeral 44: In or on the surface of the substrate 40 Two electrostatic discharge (ESD) circuits formed above, each ESD circuit being provided for each accessible pin (pin 52; described below) for external connections 46: interconnect line layer These interconnect lines are above the surface of the substrate 40 and below the passivation layer 48, representing a typical application of conventional thin wire interconnects; these thin wire interconnects in layer 46 are typically Has a high resistivity and a high parasitic capacitance 48: a passivation layer deposited on the surface of the layer 46 of the interconnect line 50: provided in the layer 46 A feed or ground bus that connects to the circuit 42 via a wire interconnect line; this feed or ground bus typically carries the stored current or for the device 42 Since it becomes a ground connection part, it is a wide metal. Reference numeral 52: a power supply or ground pin that penetrates the passivation layer 48 and is connected to the power supply or ground bus 50.

From the above, it can be summarized as follows: circuits are formed in or on the silicon substrate, interconnect lines are formed for these circuits for further interconnection to external circuits, For each I / O (input / output) pin, the circuit comprises an ESD circuit, and these circuits with the respective ESD circuit are connected to power supply or ground pins that penetrate the passivation layer. The passivation layer is the final layer that sits on top of the formed interconnect line structure, the interconnect line below the passivation layer is a thin wire interconnect, and all electrical connections of the thin wire interconnect Has disadvantages (eg, high resistivity and high parasitic capacitance).

The following explanation can be made in relation to the cross section shown in FIG. As is known in the art, ESD circuits are provided to protect semiconductor circuits against unexpected electrical charges. For this reason, each pin connected to the semiconductor circuit must have an ESD circuit.

FIG. 2 is a cross-sectional view of a conventional shape similar to that shown in FIG. However, the structure shown in cross section in FIG. 2 deals only with the clock and signal wiring network and is limited to this. FIG. 2 shows the following features (in addition to the features highlighted earlier in FIG. 1):

Reference numeral 45: Two ESD circuits provided in or on the surface of the substrate 40; an ESD circuit is always required for any external connection to input / output (I / O) pins. Reference numeral 45 ': each input ( Receiver) or output (driver) or circuit that can be a receiver or driver or I / O circuit for I / O. 54: clock bus bar 56: clock or signal pin extending through the passivation layer 48.

The same description as described above in connection with FIG. 1 applies to the cross-section shown in FIG. 2, but as a summary description that it is the final layer present on the structure on which the passivation layer is formed, the passivation The interconnect lines below the layers are fine wire interconnects and have all of the electrical disadvantages of thin wire interconnects (eg, high resistivity and high parasitic capacitance).

If pin 56 is a signal or clock pin, what applies further to the cross section shown in FIG. 2 is as follows: Pin 56 must be connected to ESD and driver / receiver or I / O circuit 45. For signal or clock pins 56 that must be connected, these pins must be connected not only to the ESD circuit, but also to the driver or receiver or I / O circuit highlighted as circuit 45 'in FIG. 2 (clock and signal). After the stimuli have passed through the ESD and driver / receiver or I / O circuitry, these stimuli are further routed using thin wire interconnect wires under conventional methods. A passivation layer is deposited on the dielectric layer forming the interconnect network.

Therefore, a concern for the semiconductor field is to provide a method of forming interconnect lines that eliminates the typical limitations placed on interconnect wires (eg, undesirable parasitic capacitance and high resistivity of interconnect lines). That is.

[Problems to be solved by the invention]
The main objective of the present invention is to provide an interconnect metal formation method that allows the use of thick and wide range of metals.

Another object of the present invention is to provide a method of forming an interconnect metal that uses a thick dielectric layer such as a polymer. Yet another object of the present invention is to provide a method that allows the formation of long interconnect lines that do not have high resistance or cause high parasitic capacitance.

Another object of the present invention is to form interconnect lines that can carry large values of current for the formation of feed and ground wiring networks. Yet another object of the present invention is to form an interconnect metal that can be formed using an inexpensive manufacturing method by forming an interconnect metal on the surface of the layer after the passivation layer has been deposited.

[Means for Solving the Problems]
In accordance with the purpose of the present invention, a novel method for forming interconnect lines is provided. A thin wire interconnect is provided as a first dielectric layer located on a semiconductor circuit formed in or on the surface of the substrate. A passivation layer is deposited on the dielectric layer and a thick second dielectric layer is formed on the surface of the passivation layer. A thick and wide interconnect line is formed in the thick second dielectric layer.

Embodiment
For reference purposes and for a clear understanding, reference is made to the related patent application 09 / 251,183 (hereinafter referred to as the reference application) in FIG.

With particular reference to FIG. 6, a cross-section of one embodiment of a reference application is shown. The surface of the silicon substrate 10 includes transistors and other devices (not shown in FIG. 6). The surface of the substrate 10 is covered with a dielectric layer 12, and therefore the dielectric layer 12 is deposited in the surface of the substrate and on devices provided on the substrate 10. Conductive interconnect lines 11 are provided within layer 12 and connect to semiconductor devices provided within the surface of substrate 10.

Layer 14 (showing two examples) typically represents all of the metal and dielectric layers formed on top of the dielectric layer 12, so that the layer 14 shown in FIG. 6 is a dielectric or insulator. , And conductive interconnect lines 13 that form a network of electrical connections formed throughout layer 14. Electrical contacts 16 are located on the surface of layer 14. These electrical contacts 16 may be, for example, bond pads that establish electrical interconnections to transistors and other devices provided in the surface of the substrate 10. These contacts 16 are interconnection points within the IC structure that need to be further connected to peripheral circuitry. A passivation layer 18 formed, for example, of silicon nitride is deposited on the surface of layer 14 to protect the underlying layer from moisture, contamination, and the like.

The main process of the above referenced application begins with the deposition of a thin layer 20 of polyimide that is deposited on the surface of layer 18. The electrical contact 16 must be accessible and for this reason the pattern of openings 22, 36, 38 is etched through the polyimide layer 20 and the passivation layer 18, and the pattern of openings 22, 36, 38 is an electrical contact. Matches 16 patterns. Contacts 16 electrically extend to the surface of layer 20 through openings 22/36/38 formed in layer 20 of polyimide.

The above referenced material used for the deposition of layer 20 is polyimide, but the material that can be used for this layer is not limited to polyimide and includes any known polymer (SiCl _x O _y ). Can do. The polyimide shown is a preferred material to use for the process of the present invention for the thick layer 20 of polymer. Examples of polymers that can be used are silicon-based, carbon-based, fluoride, chloride-based, oxygen-based, silicone elastomer, parylene or Teflon (registered trademark), polycarbonate (PC), polystyrene (PS), polyoxide (PO), Polypolyoxide (PPO) and benzocyclobutene (BCB).

Here, the electrical contact with the contact point 16 can be formed by filling the openings 22/36/38 with a conductive material. Here, the top surface 24 of these metal conductors contained within the openings 22/36/38 can be used for connection of the IC to the periphery and for further incorporation into the surrounding electrical circuit. This latter description is equivalent to the fact that semiconductor devices provided on the surface of the substrate 10 can be further connected to surrounding elements and circuits via conductive interconnects contained within the openings 22/36/38. is there. Interconnect pads 26, 28 are formed on top of the surface 24 of the metal interconnect contained within opening 22/36/38. These pads 26, 28 can be arbitrarily designed in width and thickness to meet specific circuit design requirements. For example, the pad can be used as a flip chip pad. Other pads can be used for power distribution and as ground or signal buses. The following connections can be formed, for example, in the pad shown in FIG. 6: pad 26 can act as a flip chip pad, pad 28 can act as a flip chip pad, or power supply Alternatively, it can be connected to an electrical ground point or an electrical signal bus. There is no connection between a pad of the dimensions shown in FIG. 6 and the proposed possible electrical connection that allows this pad to be used. The dimensions of the pads, as well as the standard rules and restrictions of electrical circuit design, determine the electrical connections that are useful for a given pad itself.

The following description relates to the size and number of contacts 16 (FIG. 6). Since these contacts 16 are located on top of a thin dielectric (layer 14, FIG. 6), the pad dimensions cannot be made excessively large. The reason is that large pad dimensions cause large capacitance. Furthermore, the large pad dimensions conflict with the wiring capabilities of that layer of metal. Therefore, it is preferable to keep the dimensions of the pad 16 relatively small. However, the dimensions of the pad 16 are also directly related to the aspect ratio of the vias (openings) 22/36/38. An aspect ratio of about 5 is acceptable when considering via etching and via filling. Based on these considerations, the size of the contact pad 16 can be on the order of 0.5 μm to 30 μm, and the exact size depends on the thickness of the layers 18, 20.

For larger aspect ratio vias, the vias are filled with via plugs before the metal layers 26, 28 are deposited. However, for vias having a smaller aspect ratio (eg, less than 2), a via plug is not required, in which case the metal of layers 26, 28 can directly establish contact with pad 16.

The reference application does not limit the number of contact pads that can be included in the design, and this number depends not only on package design requirements but also largely on the internal circuit design requirements of the package. Layer 18 in FIG. 6 can be a typical IC passivation layer.

The most frequently used passivation layers in the current state of the art are plasma enhanced CVD (PECVD) oxides and nitrides. In forming the passivation layer 18, a layer of about 0.5 μm PECVD oxide can be deposited first, and then a layer of about 0.7 μm nitride can be deposited. The passivation layer 18 is extremely important. The reason is that this layer protects the device wafer from moisture and external ionic contamination. The positioning of this layer between the submicron process (for integrated circuits) and the tens-micron process (for interconnected metallization structures) is crucial. The reason is that this allows for a cheaper process that can reduce the need for a strict clean room for the process of forming the interconnected metallization structure.

Layer 20 is a thick polymer (eg, polyimide) dielectric layer having a thickness greater than 2 μm (after curing). The range of polymer thickness can vary from 2 μm to 150 μm depending on electrical design requirements.

For the deposition of the layer 20, for example, polyimide HD2732 or 2734 manufactured by Hitachi DuPont can be used. Polyimide can be spin-on coated and cured. After spin-on coating, the polyimide is cured for 1 hour at a temperature of 400 ° C. in a vacuum or nitrogen environment. For thicker polyimides, multiple polyimide films can be coated and cured.

Another material that can be used to form layer 20 is polymer benzocyclobutene (BCB). This polymer is currently manufactured commercially, for example by the Dow Chemical Company, and has recently been licensed to be used in place of typical polyimide applications.

The dimensions of the openings 22, 36, 38 have been described above. The size of the opening cooperates with the thickness of the dielectric to determine the aspect ratio of the opening. The aspect ratio facilitates the via etch process and metal fill capability. This allows the diameter of the opening 22/36/38 to be in the range of about 0.5 μm to 30 μm and the height for the opening 22/36/38 to be in the range of about 2 μm to 150 μm. The aspect ratio of the openings 22/36/38 is designed so that via filling with metal can be achieved. The via can be filled with CVD metal such as CVD tungsten or CVD copper, electro-less nickel, corrugated metal filling process, electroplated copper, and the like. As already mentioned, via filling is not necessary as an extra processing step for low aspect ratio vias. Direct contact between the metal layers 26, 28 and the contact pads 16 can be achieved.

The reference application can be further expanded by applying a plurality of polymer layers (such as polyimide) and can therefore be adapted to a wider variety of applications. The function of the structure described in connection with FIG. 6 can be further expanded by depositing a second polyimide layer on top of the previously deposited layer 20 and overlying the pads 26,28. it can. Selective etching and metal deposition or metal electroplating can further form additional contacts on the surface of the second polyimide layer that can be interconnected with pads 26,28. Additional polyimide layers and contact pads formed thereon can be tailored to specific applications, and the given extension of multiple polyimide layers greatly improves the flexibility and usefulness of reference continuation applications Let

FIG. 6 shows the advantages of the basic design of the reference continuation application. This advantage allows a submicron or fine line passing immediately adjacent to the metal layer 14 and the contact 16 to extend upward 30 through the metal interconnect, which extension is horizontal to the metal interconnect 28. Continues in direction 32 and travels down through metal interconnect 38 to downward 34. The mechanism and structure of the passivation layer 18 and insulating layer 20 remain as emphasized above. An advantage of this basic design of the present invention is that it “lifts” or “fans out” the thin wire interconnects, and has significantly larger dimensions from the micro and sub-micro levels, Therefore, moving to a metal interconnect level that has smaller resistance and capacitance and can be manufactured easily and inexpensively. This aspect of the reference application does not include any aspect of pad rewiring and therefore has inherent simplification characteristics. This therefore adds to the importance of the reference application to allow access to micro and sub-micro interconnects at wide and thick metal levels. The interconnects 22, 36, 38 travel upward through the passivation layer and the polymer or polyimide dielectric layer, and continue for a distance over a wide, thick metal level, through the passivation layer and the polymer or polyimide dielectric layer. The fine line level metal is interconnected by continuing to descend from the wide and thick metal level down to the fine line metal level by proceeding downward again. The extension achieved in this manner need not be limited to any particular type of fine metal interconnect point 16 extension, such as a signal on a wide and thick metal line 26, 28 or power supply or ground. The laws of physics and electronics, if any, give limits on the type of interconnection that can be established in this way, and the limiting factors are common electrical limiting factors such as resistance, propagation delay, RC constant, etc. The reference application is important because the reference continuation application provides greater freedom in applying these laws, so that a wider range of integrated circuit applications and uses, and Provides application of these circuits to a wide and thick metal environment.

This completes the description of the configuration shown in FIG. 6 for reference purposes. Subsequently, the cross section shown in FIGS. 7a and 7b will be described. FIG. 7a shows, for reasons of clarity, a simplified cross section of the substrate and the layer formed on the surface of this substrate by the process of the present invention, with the highlighted part shown as follows: Is specified in:
Reference numeral 10: Silicon substrate Reference numeral 12: Dielectric layer deposited on the surface of the substrate Reference numeral 14: Interconnect layer including interconnection lines, vias and contacts Reference numeral 16: Contact point on the surface of the interconnection layer Reference numeral 18: Contact point Passivation layer with openings accessible to 16 Reference numeral 20: Thick polymer layer Reference numeral 21: Thick layer 20 of conductive plug polymer provided through the polyimide layer 20 covers the surface of the passivation layer 18 in liquid form Or it can be laminated on the surface of the passivation layer 18 by application of a dry film. The vias necessary to form the conductive plug 21 can be defined by a common photolithography process or can be formed using laser (drilling) techniques.

From the above description, the series of layers shown in cross-section in FIG. 7a allows additional electrical elements such as inductors and capacitors to be formed on the surface of the polyimide layer 20 and is electrically connected to the conductive plug 21. It is clear that it was formed to contact. In the cross section shown in FIG. 7 a, the dielectric layer 12 can be part of the layer 14. This is because layer 14 is an intra-level dielectric (ILD) layer that can easily incorporate layer 12.

With respect to the cross section shown in FIG. 7b, the same layers as specified in FIG. 7a are also provided in this cross section. Also shown is an upper layer 17 of the silicon substrate 10 that contains active semiconductor devices. A cross section of inductor 19 formed on the surface of passivation layer 18 is also shown. It must be emphasized that the ohmic resistivity of the metal used for the inductor 19 must be as small as possible. For this reason, it is preferable to use, for example, a thick layer of gold for the formation of the inductor 19, and a thick layer of gold for a 2.4 GHz application that greatly improves the Q value of the inductor 19. It has been shown to increase the Q value of the inductor 19 from about 5 to about 20.

Referring now specifically to FIG. 3a, this drawing refers only to power and ground pins and does not deal with signal or clock pins. FIG. 3a shows a cross-sectional view of a silicon substrate 40 having an interconnect network according to the present invention formed thereon, the wide and thick wire interconnect network being formed in a thick dielectric layer overlying a passivation layer. The Feed and / or ground pins are provided through the surface of the thick dielectric layer for external connection. The following are the various features shown in Figure 3a:
Reference numeral 40: a silicon substrate having a surface with interconnect lines formed thereon according to the present invention Reference numeral 42: a semiconductor circuit formed in or on the surface of the substrate 40 Reference numeral 44: provided for passivating the circuit 42 ESD circuit 58: Connection pad to semiconductor device 42 formed in or on the surface of substrate 40 Reference 60: Fine wire interconnect formed to be located on connection pad 58 to semiconductor device 42 Reference numeral 61: One of the vias provided in the layer 60; a larger number of such vias are shown in FIG. 3a, but have been omitted for reasons of clarity. 62: Passivation layer deposited so as to be overlying the layer 60 of the fine wire interconnects 63: One of the vias through the passivation layer 62; Such vias are shown in FIG. 3a, but the reference numerals have been omitted for reasons of clarity. Reference numeral 64: dielectric layer with interconnects formed therein as post-passivation numeral 65 : Feed or ground bus starting from within layer 64 and passing through layers 62, 60 and connected to ESD circuit 66: Combination of feed or ground bus (for multiple connection pads in layer 58) A via formed to lie over the passivation layer 62; a larger number of such vias are shown in FIG. 3a, but have been omitted for reasons of clarity. From the cross-section shown in FIG. 3a, most importantly, interconnects to semiconductor devices formed in or on the surface of the substrate. The ability to extend by not only forming these interconnects within the thin wire interconnects in layer 60, but also by forming a wide and thick interconnect network overlying the passivation layer. It is clear that This is because these lines (within or on the surface of the substrate) can be used, with the interconnect network formed overlying the passivation layer being able to contain rugged or thicker and wider interconnect lines. It provides an immediate and significant advantage in that it is further removed from the surface of the substrate (so as to reduce parasitic effects due to interconnect lines on the semiconductor device formed above). Thick and wide metal interconnects can be used for power and ground wiring, this wiring occurs above the passivation layer and is partially replaced, and for this purpose the fine wire below the passivation layer Extends conventional methods with interconnected networks. Some concerns may be listed here in connection with conventional methods and the present invention.
Conventional technology:
Providing an ESD circuit for each pin used for external input / output interconnections;
After the ESD stimulus has passed through the ESD circuit, it provides a fine wire interconnect network for further distribution of power and ground stimuli; and a fine wire feed and ground wiring network is formed below the passivation layer.

In this regard and in connection with the above description, it should be kept in mind that the power and ground pins do not require driver and / or receiver circuitry.
The present invention: there is no need to form an ESD circuit for each pin used for external input / output interconnection; this takes into account the more robust wiring that drives the ESD circuit and spans the interconnection line Reduces power loss due to unexpected power surges and delivers more power to the ESD circuit;
Allows power and ground interconnections to be directly connected to the internal circuitry of the semiconductor device; this involves no ESD circuit or a smaller ESD circuit than standard ESD circuits (as previously described).

The method used to form the interconnect network shown in cross-section in FIG. 3a deals only with the use of power and ground connections and does not apply to clock and signal interconnect lines. FIG. 3a can be summarized as follows: a silicon substrate comprises a surface in which a semiconductor device and at least one electrostatic discharge (ESD) circuit are formed, and a first dielectric layer is on the substrate A thin wire interconnect network is formed in the first dielectric layer and contacts the active and ESD circuits. A passivation layer is deposited on the surface of the first dielectric layer and a metal plug (or a direct interconnect between the overlying metal layers as pointed out above for low aspect ratio vias) Is formed in the passivation layer to match the contacts formed in the surface of the first dielectric layer. A second dielectric layer is deposited on the surface of the passivation layer, and a wide and thick line interconnect network is formed in the second dielectric layer and contacts the ESD circuit. An electrical contact consisting of a feed or ground contact is provided in the surface of the second dielectric layer.

FIG. 3b provides further insight into the formation of the feed and ground interconnect lines of the present invention, these interconnect lines being shown as interconnect line 66 and interconnect line 66 '. Interconnect line 66 is formed above passivation layer 62 and acts as a generic feed and ground interconnect line. Interconnect line 66 'is formed below passivation layer 62 and serves as a local feed and ground interconnect line.

Referring now to FIG. 4a, FIG. 4a handles signal and clock line interconnections. In FIG. 4a, a cross section of a silicon substrate 40 is shown, and an interconnection network according to the present invention is formed on the substrate. Access pins to the ESD circuit or driver circuit or receiver circuit or I / O circuit are provided through the surface of the dielectric layer for external connection. While ESD circuits are necessary for all circuits that establish I / O connections, independent of the type of circuit that establishes I / O connections, I / O connections can also be receiver circuits or driver circuits or I / O connections. It can be provided for the O circuit.

The features shown in FIG. 4a and not previously highlighted are as follows: The present invention provides an interconnect network with wide and thick interconnect lines for delivering clock and signal stimuli; Is located on the passivation layer and forms a thick and wide interconnect line for clock and signal stimulation;
Reference 70: External connection (pin) provided for ESD circuit 45 and for driver / receiver / I / O circuit 45 '; pin 70 is an external access for clock and signal stimulation to circuits 45, 45' I will provide a;
72: Clock or signal bus formed in interconnect layer 64 using thick and wide wires for interconnect lines; clock and signal interconnect line wiring provides external contacts for I / O interconnect Note that it is entirely contained within layer 64 without.

The method used to form the interconnect network shown in cross section in FIG. 4a can be summarized as follows. A silicon substrate is provided, and an active circuit including an ESD, a receiver, a driver, and an I / O circuit is formed on the surface of the substrate. A first dielectric layer of inorganic material is deposited on the substrate and a thin wire interconnect network is formed in the dielectric layer to contact the active circuit. A passivation layer is deposited on the first thin dielectric layer and a pattern of metal plugs is formed in the passivation layer (or, for low aspect ratio openings, through the openings in the intervening dielectric layer). Direct contact is established between the upper metal layers) and the metal interconnects align with electrical contacts in the surface of the first dielectric layer. One or more thicker dielectric layers are typically deposited on the surface of the passivation layer of organic material, and a wider and thicker line interconnect network containing one ESD, receiver, driver or I / O circuit. It is formed in a thick dielectric layer and is in electrical contact with a metal plug or metal pad in or under the passivation layer.

FIG. 4b provides further insight into the formation of the signal and clock interconnect lines of the present invention, these interconnect lines being shown as interconnect line 71 and interconnect line 71 '. Interconnect line 71 is formed above passivation layer 62 and acts as a generic signal and clock interconnect line. Interconnect line 71 'is formed below passivation layer 62 and acts as a local signal and clock interconnect line.

FIG. 5a shows a cross section of a silicon substrate 40 on which an interconnect network according to the present invention is formed, the interconnect network being formed in a thick dielectric layer overlying the passivation layer, It is located inside. No ESD, receiver, driver or I / O circuit access pin for external connection is provided through the surface of the dielectric layer. Shown in FIG. 5a, but not emphasized earlier is a clock or signal interconnect line 74, which is a thick and wide line of material located on the passivation layer without external I / O connections. Provides an interconnection scheme. Because of the thick and wide lines of interconnect networks formed overlying the passivation layer, clock and signal distribution can occur entirely within the interconnect layer 64, which is the clock and signal wiring line. In contrast to prior art methods, where each thick and wide interconnect line (when used) must have at least one I / O connection point for off-chip connection.

The method used to form the wide and thick line interconnect shown in cross section in FIG. 5a can be summarized as follows and is similar to that described above in connection with FIG. 4a. A silicon substrate is provided and active devices are provided in the surface of the substrate. A first thin dielectric layer is deposited on the surface of the substrate and a fine wire interconnect network with fine wire interconnect lines is formed in the first dielectric layer to contact electrical contacts in the surface of the substrate. . A passivation layer is deposited on the surface of the first dielectric layer, and a pattern of conductive interconnects is formed in the passivation layer to align with electrical contacts in the surface of the first dielectric layer. One or more second dielectric layers are deposited on the surface of the passivation layer and are in electrical contact with the conductive interconnects in the passivation layer.

FIG. 5b provides further insight into the formation of the signal and clock interconnect lines of the present invention, these interconnect lines being shown as interconnect lines 74 and interconnect lines 74 '. Interconnect line 74 is formed above passivation layer 62 and acts as a generic signal and clock interconnect line. Interconnect line 74 'is formed below passivation layer 62 and serves as a local signal and clock interconnect line.

If FIG. 3-5 shows a thin wire interconnect network 60 located below the passivation layer 62, the present invention is also possible, completely eliminating the thin wire interconnect network 60 and using only thick and wide wires. It should be further emphasized that it can be further expanded to form an interconnect network 64. For this application of the invention, the first dielectric layer 60 is not applied and the passivation layer 62 is deposited directly on the surface of the semiconductor device 58 formed in or on the surface of the substrate 40.

It is more valuable to briefly explain the above-mentioned distinction between fine wire interconnect lines and wide and thick interconnect lines. The following points apply to this: While conventional thin wire interconnect lines are formed underneath the passivation layer, the wide and thick interconnect lines of the present invention are formed over the passivation layer; the thin wire interconnect lines are typically inorganic dielectric layers. The thick and wide interconnect lines formed within are typically formed in a dielectric layer made of a polymer. The reason is that because the dielectric layer can result in tears and cracks, inorganic materials cannot be deposited as a thick dielectric layer; thin wire interconnect metals are typically sputtered or electroplated by resistive etching. Formed using a corrugated pattern process using oxidative etching at, followed by CMP. Neither of these two methods can form a thick metal because it is expensive or because of oxidative cracks; thick and wide interconnect lines first sputter a thin metal base layer and coat a thick layer of photoresist. It can be formed by patterning, applying a thick layer of metal by electroplating, removing the patterned photoresist and performing a metal-based etch (of a sputtered thin metal base). This method allows the formation of very thick metal patterns, in which a metal thickness in excess of 1 μm is achieved with the thickness of the dielectric layer having thick metal interconnect lines formed in it can exceed 2 μm. it can.

Although the invention has been described and illustrated with reference to specific exemplary embodiments, it is not intended that the invention be limited to these exemplary embodiments. Those skilled in the art will recognize that various changes and modifications can be made without departing from the spirit of the invention. Accordingly, all such variations and modifications as included within the spirit of the invention and their equivalents are included in the invention.
[Brief description of the drawings]
[Figure 1]
A silicon substrate on which a conventional thin wire interconnect network is formed, on which a passivation layer is deposited, and for providing an external connection, feed and / or ground pins are provided through the passivation layer. It is a cross-sectional view of such a silicon substrate. The structure shown in cross section in FIG. 1 deals only with a conventional power supply and ground wiring network and is limited to this.
[Figure 2]
A silicon substrate on which a conventional thin wire interconnect network is formed, a passivation layer is deposited thereon, and clocks and / or signal pins are provided through the passivation layer for connection to the outside. It is a cross-sectional view of such a silicon substrate. The structure shown in cross section in FIG. 2 handles only conventional clock and signal wiring networks and is limited to this.
[Fig. 3]
FIG. 3a is a cross-sectional view of a silicon substrate having an interconnect network according to the present invention formed thereon. A power feed and / or ground pin is provided through the surface of the dielectric layer for connection to the outside. The structure shown in cross section in FIGS. 3a and 3b deals only with the feed and ground wiring network of the present invention and is limited to this. FIG. 3b shows the difference between the feed and ground wiring lines below the passivation layer and the feed and ground wiring lines above the passivation layer.
[Fig. 4]
FIG. 4a is a cross-sectional view of a silicon substrate having an interconnect network according to the present invention formed thereon. ESD and / or driver and / or receiver circuit access pins are provided through the surface of the dielectric layer for external connection. The structure shown in cross section in FIGS. 4a and 4b deals only with the clock and signal wiring network of the present invention and is limited to this. FIG. 4b is a diagram showing the difference between the clock and signal wiring lines below the passivation layer and the clock and signal wiring lines above the passivation layer.
[Figure 5]
FIG. 5a is a cross-sectional view of a silicon substrate having an interconnect network according to the present invention formed thereon. There is no I / O connection pin penetrating the surface of the dielectric layer for connection to the outside. The structure shown in cross section in FIGS. 5a and 5b deals only with the clock and signal wiring network of the present invention and is limited to this. FIG. 5b illustrates the difference between the clock and signal wiring lines below the passivation layer and the clock and signal wiring lines above the passivation layer.
[Fig. 6]
It is a cross-sectional view of the interconnection system according to the invention of the partially continued application referred to above.
[Fig. 7]
FIG. 7a is a cross-sectional view of a simplified version of the substrate and the layers formed on the surface of the substrate by the process of the continuation-in-part application referenced above. FIG. 7b is a cross-sectional view of FIG. 7a with an inductor added over the passivation layer.
[Explanation of symbols]
10, 40 Silicon substrate 12 Dielectric layer 14 Interconnect layer 16 Electrical contacts 18, 62 Passivation layer 20 Thick layer 21 Conductive plugs 22, 36, 38 Openings (vias)
26, 28 Pad 42 Semiconductor device 44, 45 ESD circuit 60 Thin wire interconnection layer (network)
61, 63, 67 Via 64 Dielectric layer 65 Power supply or ground bus 68 Power supply or ground pin 72 Clock or signal bus

Claims (8)

A silicon substrate;
An ESD circuit in or on the silicon substrate;
A first internal circuit in or on the silicon substrate;
A driver, receiver or I / O circuit in or on the surface of the silicon substrate, the driver, receiver or I / O circuit having a first terminal and a second terminal ;
A dielectric layer on said silicon substrate;
A first interconnect structure on the silicon substrate and in the dielectric layer, the first interconnect structure connected to a first terminal of the driver, receiver or I / O circuit ;
Said silicon substrate and a second interconnect structure of the dielectric layer, the second interconnect structure that will be connected to said first internal circuit;
A passivation layer on said dielectric layer, comprising a nitride layer;
A first via in the passivation layer, the first via connected to the first interconnect structure;
A second via in the passivation layer and connected to the second interconnect structure;
A polymer layer above the surface of the passivation layer;
A third interconnect structure on the passivation layer and in the polymer layer, wherein the third interconnect structure is connected to the first and second vias, and the first terminal is sequentially the first interconnect structure, wherein the first via, the third interconnect structure, wherein the second via and the through the second interconnect structure first internal circuit A third interconnect structure connected to the;
The ESD circuit and the driver, and an external connection portion connected to the second terminal of the receiver or the I / O circuit;
Including
The chip is formed in the polymer layer, wherein the third interconnect structure is thicker and wider than the first and second interconnect structures and thicker than the dielectric layer.
A silicon substrate;
A first internal circuit in or on the silicon substrate ;
And ESD circuitry in or on the silicon substrate;
A dielectric layer on the silicon substrate;
A first interconnect structure on the silicon substrate and in the dielectric layer, the first interconnect structure connected to the ESD circuit;
Said silicon substrate and a second interconnect structure of the dielectric layer, the second interconnect structure that will be connected to said first internal circuit;
A passivation layer on said dielectric layer, comprising a nitride layer;
A first via in the passivation layer, the first via connected to the first interconnect structure;
A second via in the passivation layer and connected to the second interconnect structure;
A polymer layer above the surface of the passivation layer;
A third interconnect structure on the passivation layer and in the polymer layer, the third interconnect structure connected to the first and second vias;
The ESD circuit sequentially through the first interconnect structure, the first via, the third interconnect structure, the second via, and the second interconnect structure. Connected to the first internal circuit,
The chip is formed in the polymer layer, wherein the third interconnect structure is thicker and wider than the first and second interconnect structures and thicker than the dielectric layer.
3. The chip of claim 2 , comprising: a second internal circuit in or on the silicon substrate; and a fourth interconnect structure on the silicon substrate and in the dielectric layer, A fourth interconnect structure connected to the second internal circuit and a third via in the passivation layer and connected to the third and fourth interconnect structures; further comprising a via, said first internal circuit sequentially, the second interconnect structure, wherein the second via, the third interconnect structure, the third via and the fourth The ESD circuit is connected to the second internal circuit via an interconnect structure, and the ESD circuit sequentially includes the first interconnect structure, the first via, the third interconnect structure, and the second interconnect circuit. 3 via and through the fourth interconnect structure connected to the second internal circuit Is, chip.
3. The chip of claim 2 , wherein the third interconnect structure includes a power bus on the passivation layer, the power bus is connected to the first and second vias, and the ESD circuit is A chip connected to the first internal circuit via the power bus.
3. The chip of claim 2 , wherein the third interconnect structure includes a ground bus on the passivation layer, the ground bus is connected to the first and second vias, and the ESD circuit is A chip connected to the first internal circuit via the ground bus.
A silicon substrate;
An ESD circuit in or on the silicon substrate;
A first internal circuit in or on the silicon substrate;
A second internal circuit in or on the silicon substrate;
A dielectric layer on the silicon substrate;
A first interconnect structure on the silicon substrate and in the dielectric layer, the first interconnect structure being connected to the first internal circuit;
Said silicon substrate and a second interconnect structure of the dielectric layer, the second interconnect structure that will be connected to the second internal circuit;
A passivation layer on said dielectric layer, comprising a nitride layer;
A first via in the passivation layer, the first via connected to the first interconnect structure;
A second via in the passivation layer and connected to the second interconnect structure;
A clock bus on the passivation layer and in the polymer layer, the clock bus connected to the first and second vias;
The first internal circuit sequentially through the first interconnect structure, the first via, the clock bus, the second via, and the second interconnect structure, It is connected to the second internal circuit,
The chip is formed in the polymer layer that is thicker and wider than the first and second interconnect structures and thicker than the dielectric layer.
7. The chip of claim 6 , wherein the polymer layer has a thickness greater than 2 micrometers.
7. The chip of claim 6 , wherein the clock bus has a thickness greater than 1 micrometer.

Images