JP2002270686A - Interconnecting structure body and forming method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new method to forming an interconnection line. SOLUTION: A thin line interconnection part (60) is provided in the surface of a substrate (10), or in a first dielectrics layer (12), located above a semiconductor circuit (42) formed over it. A passivation layer (18) sticks to the dielectrics layer, while a second thick dielectrics layer (20) is formed on the surface of the passivation layer. A thick and wide interconnection line is formed in the second thick dielectrics layer. The first dielectrics layer may be so omitted, to form a wide and thick interconnection network on the surface of the passivation layer which sticks to the surface of substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] This application is related to the present applicant.
1999, which is a continuation-in-part of patent application Ser. No. 09 / 216,791 filed on Dec. 21, 998.
No. 09 / 251,183, filed Feb. 17, 2014. This application is also related to Patent Application No. filed on the date.

[0002] The present invention relates to the manufacture of integrated circuit devices,
In particular, it relates to a method of post-passivation or post-passivation to create conductive interconnects.

[0003]

BACKGROUND OF THE INVENTION Improvements in the performance of semiconductor devices are typically obtained by reducing the geometries of integrated circuits, resulting in lower cost per die and, at the same time, lower semiconductor device performance. Several aspects of performance are improved. While the metal connections that connect integrated circuits to other circuits or components of the system have become relatively more important, the further miniaturization of ICs (integrated circuits) has led to a reduction in circuit performance. Increase adverse effects. The parasitic capacitance and resistance of the metal interconnect increases, which significantly degrades chip performance. Most important in this regard is the power and ground bus (bus) and the RC of the electrical signal path.
This is the voltage drop along the delay. Attempting to reduce the resistance using wider metal lines increases the capacitance of these wires.

To solve this problem, one attempt has been made to develop a low resistance metal (eg, copper) for the wire while using a low dielectric material between the signal lines. Current practice is to form a metal interconnect network beneath the passivation or passivation layer, but this approach has limited the interconnect network to fine wire interconnects,
In this connection, it gives rise to parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively large values, degrade the performance of the device, and the effect is even more severe for higher frequency applications and for long interconnect lines used, for example, in clock wiring lines. Also, fine-wire interconnect metal cannot typically carry large current values that require a ground bus and a power bus.

[0005] As mentioned above, the concern in the semiconductor field is that of interconnect lines that eliminate the typical limitations imposed on interconnect wires (eg, undesirable parasitic capacitance and high interconnect line resistance). It is to provide a forming method. The present invention provides such a method. In this regard, it can be pointed out that currently used (conventional) fine line interconnect systems formed under the passivation layer are similar to urban streets.
The post-passivation interconnect scheme of the present invention can be considered as a highway between cities.

Referring now to the drawings illustrating the prior art, FIG. 1 is a cross-sectional view of a silicon substrate having a surface having a conductive interconnect network formed thereon. The structure shown in cross-section in FIG. 1 handles only conventional power and ground wiring networks and is limited thereto. Various features highlighted in FIG. 1 are as follows.

Reference numeral 40: a silicon substrate having a surface with an interconnect network formed thereon 42: an exemplary number of semiconductor circuits formed in or on the surface of the substrate 40 Reference numeral 44: the surface of the substrate 40 There are two electrostatic discharge (ESD) circuits formed in or on each, each ESD circuit being provided for each accessible pin (pin 52; see below) for external connections. Line layers; these interconnect lines are above the surface of the substrate 40 and the passivation layer 48
And represents the typical application of conventional wire interconnects; these wire interconnects in layer 46 typically have high resistivity and high parasitic capacitance. A passivation layer deposited on the surface of layer 46 of FIG. 50: a power or ground bus that connects to circuit 42 via a fine wire interconnect line provided in layer 46; this power or ground bus is typically 52, which is a wide metal because this feed or ground bus carries the stored current or provides a ground connection for the device 42. 52: penetrates the passivation layer 48 and connects to the feed or ground bus 50. Power or ground pin.

From the above, the following can be summarized:
Circuits are formed in or on the silicon substrate and for further interconnection to external circuits, interconnect lines are formed for these circuits and for each I / O (input / output) pin,
The circuits comprise ESD circuits, and these circuits with respective ESD circuits are connected to power or ground pins which penetrate the passivation layer. The passivation layer is the final layer overlying the formed interconnect line structure, and the interconnect lines below the passivation layer are the fine interconnects and all the electrical connections of the fine interconnects. Disadvantages (eg high resistivity and high parasitic capacitance)
Having.

The following description can be given with reference to the cross section shown in FIG. As is known in the art, ESD circuits are provided to protect semiconductor circuits against unexpected electrical charges. For this reason, each pin connected to the semiconductor circuit must have an ESD circuit.

FIG. 2 is a cross-sectional view of a conventional shape similar to the cross-section shown in FIG. However, the structure shown in cross section in FIG. 2 handles only clock and signal wiring networks and is limited to this. FIG. 2 shows the following features (in addition to the features highlighted earlier in FIG. 1):

Reference numeral 45: two ESD circuits provided in or on the surface of the substrate 40; the ESD circuit is always required for any external connection to input / output (I / O) pins. A circuit that can be an input (receiver) or output (driver) or a receiver or driver for I / O or an I / O circuit. Reference numeral 54: Clock bus Reference numeral 56: Clock extending through the passivation layer 48 or Signal pin.

The same description as described above in connection with FIG. 1 applies to the cross-section shown in FIG. 2, except that the passivation layer is the final layer present on the structure. As such, the interconnect lines below the passivation layer are thin interconnects and have all of the electrical shortcomings of the thin interconnects (eg, high resistivity and high parasitic capacitance).

If pin 56 is a signal or clock pin, the following further applies to the cross section shown in FIG. 2: Pin 56 is connected to the ESD and driver / receiver or I / O circuit 45. For signal or clock pins 56 that must be connected, these pins are
Not only the circuit but also the driver or receiver or I / O circuit, highlighted in FIG. 2 as circuit 45 ', must be connected to the stimulus (clock and signal) passing through the ESD and driver / receiver or I / O circuit After that, these stimuli
Under conventional methods, it is further routed using fine interconnect wires. A passivation layer is deposited on the dielectric layer that formed the interconnect network.

Therefore, interests in the semiconductor field are:
It is an object of the present invention to provide a method of forming interconnect lines that eliminates the typical limitations placed on interconnect wires (eg, undesirable parasitic capacitance and high interconnect line resistivity).

[0015]

SUMMARY OF THE INVENTION The main object of the present invention is to:
It is an object of the present invention to provide a method for forming an interconnect metal which allows the use of thicker and wider metals.

Another object of the present invention is to provide a method for forming an interconnect metal using a thick dielectric layer such as a polymer. It is yet another object of the present invention to provide a method that allows the formation of long interconnect lines that do not have high resistance or create high parasitic capacitance.

It is another object of the present invention to form an interconnect line that can carry large values of current for the purpose of forming power and ground wiring networks. It is yet another object of the present invention to form an interconnect metal that can be formed using inexpensive manufacturing methods by forming an interconnect metal on the surface of the layer after the passivation layer has been deposited.

[0018]

According to the object of the present invention,
A new method for forming an interconnect line is provided. A fine wire interconnect is provided as a first dielectric layer located within a surface of the substrate or over a semiconductor circuit formed thereon. A passivation layer is deposited on the dielectric layer and a thick second dielectric layer is formed on the surface of the passivation layer. Thick and wide interconnect lines are formed in the thick second dielectric layer.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS For reference purposes and for a clear understanding, reference is made to the related patent application Ser. No. 09 / 251,183 (hereinafter referred to as the reference application) in FIG.

Referring specifically to FIG. 6, a cross section of one embodiment of the referenced application is shown. The surface of silicon substrate 10 includes transistors and other devices (not shown in FIG. 6). The surface of the substrate 10 is covered with a dielectric layer 12,
Therefore, the dielectric layer 12 is deposited within the surface of the substrate and on devices provided on the substrate 10. Conductive interconnect lines 11 are provided within layer 12 and connect to semiconductor devices provided within the surface of substrate 10.

Layer 14 (two examples) typically represent all of the metal and dielectric layers formed on top of dielectric layer 12, and therefore, layer 14 shown in FIG. Alternatively, it may include multiple layers, such as insulators, and conductive interconnect lines 13 that form a network of electrical connections formed throughout layer 14. Electrical contacts 16 are located on the surface of layer 14. These electrical contacts 16
For example, it may be a bonding pad provided in the surface of the substrate 10 to establish electrical interconnection to transistors and other devices. These contacts 16 are interconnection points in the IC structure that need to be further connected to peripheral circuits. A passivation layer 18, formed for example of silicon nitride, is deposited on the surface of layer 14 to protect the underlying layer from moisture, contamination, and the like.

The main steps of the above referenced application begin with the deposition of a thin layer 20 of polyimide which is deposited on the surface of layer 18. The electrical contacts 16 must be accessible and for this reason the pattern of openings 22, 36, 38 is etched through the polyimide layer 20 and the passivation layer 18, and the pattern of the openings 22, 36, 38 It matches 16 patterns. Polyimide layer 20
Contact 1 through an opening 22/36/38 formed therein.
6 extends electrically to the surface of layer 20.

Although the above-referenced material used for the deposition of layer 20 is polyimide, the material that can be used for this layer is not limited to polyimide, but may be any known polymer (SiCl _x O _y ). Can be included. The polyimide shown is the preferred material to use for the process of the present invention for the thick layer 20 of polymer. Examples of polymers that can be used include silicon-based, carbon-based, fluoride,
Chloride type, oxygen type, silicone elastomer, parylene or Teflon (registered trademark), polycarbonate (P
C), polystyrene (PS), polyoxide (P
O), polypropylene (PPO) and benzocyclobutene (BCB).

Here, the electrical contact with the contact points 16 can be formed by filling the openings 22/36/38 with a conductive material. Here, the top surface 24 of these metal conductors contained within the openings 22/36/38 can be used for connection of the IC to the surroundings and for further incorporation into surrounding electrical circuits. This latter statement is the same as that the semiconductor device provided on the surface of the substrate 10 can be further connected to surrounding elements and circuits via conductive interconnects contained in the openings 22/36/38. is there. Interconnect pads 26, 28 are formed on top of metal interconnect surface 24 contained within openings 22/36/38. These pads 26, 28 can be arbitrarily designed in width and thickness to meet specific circuit design requirements. For example, the pads can be used as flip chip pads. Other pads can be used for power distribution and as a ground or signal bus. The following connections can be made, for example, to the pads shown in FIG. 6: pad 26 can act as a flip chip pad and pad 28 can act as a flip chip pad,
Alternatively, it can be connected to a power supply or an electrical ground or an electrical signal bus. There is no connection between the pad of the dimensions shown in FIG. 6 and the proposed possible electrical connections that allow this pad to be used. Pad dimensions, as well as standard rules and limitations of electrical circuit design, determine the electrical connections that serve a given pad itself.

The following description relates to the dimensions and number of contacts 16 (FIG. 6). These contacts 16 are made of a thin dielectric (layer 14,
Since it is located at the top of FIG. 6), the dimensions of the pad cannot be excessively increased. The reason is that large pad dimensions give rise to large capacitance. In addition, large pad dimensions conflict with the wiring capabilities of that layer of metal. Therefore, it is preferable to keep the dimensions of the pads 16 relatively small. However, the dimensions of the pad 16 are also directly related to the aspect ratio of the vias (openings) 22/36/38.
Considering via etching and via filling, about 5
An aspect ratio of is acceptable. Based on these considerations, the size of the contact pad 16 is 0.5 μm to 30 μm
And the exact dimensions will depend on the thickness of the layers 18,20.

For larger aspect ratio vias, the vias are filled with via plugs before the metal layers 26, 28 are deposited. However, for vias having a smaller aspect ratio (eg, less than 2), no via plug is required, in which case the metal of layers 26, 28 can directly establish contact with pad 16.

The reference application does not limit the number of contact pads that can be included in the design, and this number depends not only on the package design requirements, but also largely on the package internal circuit design requirements. Layer 18 in FIG. 6 can be a typical IC passivation layer.

The most frequently used passivation layer in the current state of the art is plasma enhanced CVD (PE
CVD) oxides and nitrides. Passivation layer 1
8, a layer of PECVD oxide of about 0.5 μm can be first deposited, then about 0.7 μm
Can be deposited. The passivation layer 18 is very important. The reason is that this layer protects the device wafer from moisture and external ionic contamination. Submicron processes (for integrated circuits) and tens microns (for metallization structures for interconnects)
The positioning of this layer with the s-micron) process is extremely important. This is because it allows for a less expensive process that can reduce stringent clean room requirements for the process of forming metallization structures for interconnects.

Layer 20 is a thick polymer (eg, polyimide) dielectric layer having a thickness (after curing) of greater than 2 μm. The range of polymer thickness can vary from 2 μm to 150 μm depending on electrical design requirements.

For the deposition of the layer 20, for example, polyimide HD2732 or 2734 from Hitachi DuPont can be used. Polyimide can be spin-on coated and cured. After spin-on coating, the polyimide is cured for one hour at a temperature of 400 ° C. in a vacuum or nitrogen environment. For thicker polyimide, multiple layers of polyimide film can be coated and cured.

Another material that can be used to form layer 20 is polymeric benzocyclobutene (BCB).
This polymer is currently manufactured commercially, for example by Dow Chemical Company, and has recently obtained a license that can be used in place of typical polyimide applications.

The dimensions of the openings 22, 36, 38 have been described above. The dimensions of the opening, in cooperation with the thickness of the dielectric,
Determine the aspect ratio of the opening. The aspect ratio facilitates the via etching process and metal filling capability. This will increase the diameter of the openings 22/36/38 from about 0.5 μm to 30 μm
m and the height for openings 22/36/38 can be in the range of about 2 μm to 150 μm. The aspect ratio of the openings 22/36/38 is designed such that filling of the via with metal can be achieved. Vias can be made of CVD metal such as CVD tungsten or CVD copper,
ctro-less) can be filled with nickel, corrugated metal filling process, electroplated copper etc. As mentioned,
For low aspect ratio vias, via filling is not required as an extra processing step. A direct contact between the metal layers 26, 28 and the contact pads 16 can be achieved.

The reference application can be further extended by applying multiple (such as polyimide) polymer layers, and is therefore more adaptable to a variety of applications. The function of the structure described in connection with FIG. 6 is to deposit a second polyimide layer on top of the previously deposited layer 20 and to provide pads 26, 28
It can be further expanded by placing it on Selective etching and metal deposition or metal electroplating can further form additional contacts on the surface of the second polyimide layer that can be interconnected with pads 26,28. Additional polyimide layers and contact pads formed thereon can be tailor-made for a particular application, and the given extension of multiple polyimide layers greatly enhances the flexibility and utility of the reference part continuation application Let it.

FIG. 6 illustrates the advantages of the basic design of the referenced continuation-in-part application. This advantage allows submicron or fine lines passing immediately adjacent the metal layer 14 and the contacts 16 to extend upwardly 30 through the metal interconnect, the extension being in the horizontal plane of the metal interconnect 28. In the direction 32 and down through the metal interconnect 38 in a downward direction 34. The mechanism and structure of the passivation layer 18 and the insulating layer 20 remain as highlighted above. An advantage of this basic design of the present invention is that it "lifts" or "fans out" the fine wire interconnects, and that these interconnects, from the micro and sub-micro levels, have significantly larger dimensions, Therefore, moving to a metal interconnect level that has less resistance and capacitance and can be manufactured easily and inexpensively. This aspect of the referenced application does not include any aspects of pad redistribution and therefore has inherent simplification properties. This therefore adds further to the importance of the reference application in that it allows access to micro and sub-micro interconnects at wide and thick metal levels. Interconnects 22, 3
6, 38 proceed upward through the passivation layer and the polymer or polyimide dielectric layer, continue for a distance over a wide and thick metal level, and again downward through the passivation layer and the polymer or polyimide dielectric layer. Interconnects the fine line level metal by continuing down from the wide and thick metal level to the fine line metal level. The extension achieved in this manner need not be limited to the extension of any particular type of fine metal interconnect point 16, such as signal or feed or ground on wide and thick metal lines 26,28. The laws of physics and electronics impose restrictions on the types of interconnects that can be established in this way, if any, with limiting factors such as resistance, propagation delay,
It is a common electrical limiting factor such as the RC constant. The reference application is important because the reference continuation-in-part application provides greater freedom in applying these laws, so that a wider range of integrated circuit applications and uses, and The application of these circuits to a wide and thick metal environment is provided.

This completes the description of the configuration shown in FIG. 6 for reference purposes. Next, the cross section shown in FIGS. 7A and 7B will be described. FIG. 7a shows, for reasons of clarity, a simplified cross section of the substrate and of the layers formed on the surface of this substrate by the process of the invention, the highlighted parts of which are as follows: Reference numeral 10: Silicon substrate Reference numeral 12: Dielectric layer deposited on the surface of the substrate Reference numeral 14: Interconnect layer including interconnect lines, vias and contacts Reference numeral 16: Interconnect layer 14 Contacts on the surface 18: passivation layer with openings accessible to contacts 16 20: thick layer of polymer 21: conductive plug provided through layer 20 of polyimide Thick layer 20 of polymer is the surface of passivation layer 18 It can be coated in liquid form on top or can be laminated on the surface of the passivation layer 18 by applying a dry film. The vias required to form conductive plug 21 can be defined by conventional photolithographic processes, or can be formed using laser (drilling) techniques.

From the foregoing description, it can be seen that the series of layers shown in cross-section in FIG. 7a allows additional electrical components, such as inductors and capacitors, to be formed on the surface of the polyimide layer 20 and the conductive plug 21 Obviously, they were formed to make electrical contact. In the cross section shown in FIG. 7 a, the dielectric layer 12 can be part of the layer 14. The reason is,
This is because layer 14 is an intra-level dielectric (ILD) layer into which layer 12 can be easily incorporated.

For the cross section shown in FIG. 7b, the same layers as specified in FIG. 7a are also provided in this cross section. Also shown is an upper layer 17 of the silicon substrate 10 containing the active semiconductor devices. In addition, passivation layer 1
Also shown is a cross section of inductor 19 formed on the surface of 8. It must be emphasized that the ohmic resistivity of the metal used for the inductor 19 must be as low as possible. For this reason, it is preferable to use, for example, a thick layer of gold for the formation of the inductor 19, and for a 2.4 GHz application that greatly improves the Q value of the inductor 19, a thick layer of gold is used. The Q value of the inductor 19 is about 5 to about 20
To increase.

Referring now specifically to FIG. 3a, this figure refers only to power and ground pins and does not address signal or clock pins. FIG. 3a shows a cross-sectional view of a silicon substrate 40 having an interconnect network formed thereon according to the present invention, wherein the wide and thick wire interconnect network is formed in a thick dielectric layer overlying the passivation layer. You. Power and / or ground pins are provided through the surface of the thick dielectric layer for external connections. The following are various features shown in FIG. 3a: reference numeral 40: a silicon substrate having a surface on which interconnect lines are formed according to the invention reference numeral 42: a semiconductor formed in or on the surface of the substrate 40 Circuit 44: ESD circuit provided to passivate the circuit 42. 58: Connection pad to the semiconductor device 42 formed in or on the surface of the base 40. 60: Connection pad 58 to the semiconductor device 42. The layer of the fine wire interconnect formed so as to be located on top of the reference numeral 61: one of the vias provided in the layer 60; a greater number of such vias are shown in FIG. The reference number has been omitted for reasons of clarity. Reference numeral 62: passivation layer deposited overlying the layer 60 of the fine wire interconnect. Reference numeral 63: passivation layer 6. One of the vias passing through two
One more such vias are shown in FIG. 3a, but their numbers have been omitted for clarity in the figure. Reference numeral 64: interconnects formed therein as a post-passivation process. Dielectric layer 65: Power or ground bus starting from within layer 64 and connected to ESD circuits through layers 62, 60 66: (for multiple connection pads in layer 58)
Combination of power or ground buses 67: Via formed to be located above passivation layer 62; more such vias are shown in FIG. 3a.
But are omitted for reasons of clarity in the figure. Reference numeral 68: Power supply or ground pin for multiple semiconductor devices in layer 58. From the cross-section shown in FIG. What is important is that the ability to form interconnects to the semiconductor devices formed in or on the surface of the substrate is not limited to forming these interconnects in the fine wire interconnects in layer 60, By extending by forming a wide and thick interconnect network located above the passivation layer,
It is clear that it has been enlarged. This is because the interconnect network formed to overlie the passivation layer can contain robust objects, i.e., thicker and wider interconnect lines, and these lines (either within or at the surface of the substrate). To reduce the parasitic effects of interconnect lines on the semiconductor devices formed above)
It offers immediate and significant advantages in that it is further removed from the surface of the substrate. Thick and wide metal interconnects can be used for power and ground wiring, which occurs above the passivation layer and is partially replaced, and for this purpose the fine wire below the passivation layer Extends traditional methods with interconnected networks. Certain concerns may be listed here in the context of conventional methods and the present invention. Prior Art: Providing an ESD circuit for each pin used for external input / output interconnections; after the ESD stimulus passes through the ESD circuit, a fine wire interconnect for further distribution of power and ground stimuli A connection network is provided; and a fine wire feed and ground wiring network is formed below the passivation layer.

In this regard and in connection with the above description, it must be kept in mind that the power and ground pins do not require driver and / or receiver circuitry. The present invention: It is not necessary to form an ESD circuit for each pin used for external input / output interconnections; this allows for more robust wiring to drive the ESD circuits and extends over the interconnect lines. To reduce power loss due to unexpected power surges and to deliver more power to the ESD circuit; to enable power and ground interconnects to be directly connected to the internal circuitry of the semiconductor device;
No circuit or standard ESD (as described above)
With a smaller ESD circuit than the circuit.

The method used to form the interconnect network shown in cross-section in FIG. 3a deals only with the use of power and ground connections and does not apply to clock and signal interconnect lines. FIG. 3a can be summarized as follows: a silicon substrate having a surface having semiconductor devices and at least one electrostatic discharge (ESD) circuit formed therein, and a first dielectric layer on the substrate. A deposited wire interconnect network is formed in the first dielectric layer to contact the active and ESD circuits. A passivation layer is deposited on the surface of the first dielectric layer and a metal plug (or, for low aspect ratio vias, a direct interconnect between the overlying metal layers, as noted above). Are formed in the passivation layer to match the contacts formed in the surface of the first dielectric layer. A second dielectric layer is deposited on the surface of the passivation layer, and a wide and thick line interconnect network is formed in the second dielectric layer and contacts the ESD circuit. Electrical contacts, comprising power or ground contacts, are provided in the surface of the second dielectric layer.

FIG. 3b provides further insight into the formation of the power and ground interconnect lines of the present invention, which interconnect lines 66 and 66 '.
It is shown as An interconnect line 66 is formed above the passivation layer 62 and acts as a global power and ground interconnect line. An interconnect line 66 'is formed below the passivation layer 62 and acts as a local power and ground interconnect line.

Referring now to FIG. 4a, FIG. 4a deals with the interconnection of signal and clock lines. FIG. 4a shows a cross section of a silicon substrate 40 on which an interconnect network according to the invention is formed. Access pins to the ESD or driver circuit or the receiver or I / O circuit are provided through the surface of the dielectric layer for external connection. Although an ESD circuit is required for all circuits that establish I / O connections, independent of the type of circuit that establishes the I / O connections, the I / O connections can also be receiver circuits or driver circuits or I / O circuits. It can be provided for the O circuit.

The features shown in FIG. 4a and not highlighted above are as follows: The present invention provides an interconnect network with wide and thick interconnect lines for delivering clock and signal stimuli. The present invention overlies the passivation layer and forms a thick and wide interconnect line for clock and signal stimulation; 70 for the ESD circuit 45 and of the driver / receiver / I / O circuit 45 '; External connections (pins) provided for: Pin 70 provides external access for clock and signal stimulation to circuits 45, 45 '; 72: Using thick and wide wires for interconnect lines A clock or signal bus formed in the interconnect layer 64;
It should be noted that the I / O interconnect is entirely contained within layer 64 without providing external contacts.

The method used to form the interconnect network shown in cross section in FIG. 4a can be summarized as follows. A silicon substrate is provided, and active circuits including ESD, receivers, drivers and I / O circuits are formed on the surface of the substrate. A first dielectric layer of inorganic material is deposited on the substrate, and a fine wire interconnect network is formed in the dielectric layer to contact the active circuit. A passivation layer is deposited on the first thin dielectric layer, and a pattern of metal plugs is formed in the passivation layer (or, for low aspect ratio openings, through openings in the intervening dielectric layer). Direct contact is established between the upper metal layers),
Metal interconnects align with electrical contacts in the surface of the first dielectric layer. One or more thicker dielectric layers are deposited on the surface of the passivation layer, typically of an organic material;
A wide and thick line interconnect network including one ESD, receiver, driver or I / O circuit is formed in the thicker dielectric layer to make electrical contact with metal plugs or pads in or below the passivation layer I do.

FIG. 4b provides further insight into the formation of the signal and clock interconnect lines of the present invention, which interconnect lines 71 and 7
Shown as 1 '. An interconnect line 71 is formed above the passivation layer 62 and acts as a global signal and clock interconnect line. An interconnect line 71 'is formed below the passivation layer 62 and serves as a local signal and clock interconnect line.

FIG. 5a shows a cross section of a silicon substrate 40 on which an interconnect network according to the present invention has been formed, the interconnect network being formed in a thick dielectric layer overlying the passivation layer and having a thick dielectric layer. Located internal to body layer. No ESD, receiver, driver or I / O circuit access pins for external connection are provided through the surface of the dielectric layer. As shown in FIG. 5a, but not emphasized earlier, is a clock or signal interconnect line 74, which is a thick and wide line located on a passivation layer without external I / O connections. Provide an interconnect scheme. Due to the thick and wide lines of the interconnect network formed overlying the passivation layer, the clock and signal distribution is controlled by the interconnect layer 64.
This can occur entirely within the clock and signal wiring lines, where each thick and wide interconnect line (if used) has at least one I / O for off-chip connections. It differs from prior art methods in which a connection point must be provided.

The method used to form the wide and thick line interconnect shown in cross section in FIG. 5a can be summarized as follows and is similar to that described above in connection with FIG. 4a. A silicon substrate is provided and an active device is provided within the surface of the substrate. A first thin dielectric layer is deposited on a surface of the substrate, and a fine wire interconnect network with fine wire interconnect lines is formed in the first dielectric layer;
Make contact with electrical contacts in the surface of the substrate. A passivation layer is deposited on the surface of the first dielectric layer, and a pattern of conductive interconnects is formed in the passivation layer to match electrical contacts in the surface of the first dielectric layer. One or more second dielectric layers are deposited on the surface of the passivation layer and make electrical contact with conductive interconnects in the passivation layer.

FIG. 5b provides further insight into the formation of the signal and clock interconnect lines of the present invention, which interconnect lines 74 and 7
4 '. An interconnect line 74 is formed above the passivation layer 62 and acts as a global signal and clock interconnect line. An interconnect line 74 'is formed below the passivation layer 62 and serves as a local signal and clock interconnect line.

The present invention is also possible if FIGS. 3-5 show the fine wire interconnect network 60 located below the passivation layer 62, and the fine wire interconnect network 60
It has to be further emphasized that this can be completely eliminated and can be further expanded to form an interconnect network 64 using only thick and wide wires. For this application of the invention, the first dielectric layer 60 is not applied, and the passivation layer 62 is deposited directly on or on the surface of the semiconductor device 58 formed on or above the substrate 40.

It is even more valuable to briefly describe the above distinction between thin interconnect lines and wide and thick interconnect lines. The following points apply to this. Whereas conventional thin interconnect lines are formed below the passivation layer, the wide and thick interconnect lines of the present invention are formed above the passivation layer; the thin interconnect lines are typically formed of an inorganic dielectric layer. The thick and wide interconnect lines formed therein are typically formed in a dielectric layer of a polymer. The reason is that the inorganic material cannot be deposited as a thick dielectric layer because the dielectric layer results in cracks and fissures; fine wire interconnect metals are typically sputtered by resistive etching or electroplated Is formed using a corrugated patterning process using an oxidized etch in step 1 followed by CMP. Neither of these two methods can form thick metals due to cost or oxidation cracking; thick and wide interconnect lines sputter a thin metal base layer first,
Form by coating and patterning a thick layer of photoresist, applying a thick layer of metal by electroplating, removing the patterned photoresist, and performing a metal-based etch (of a sputtered thin metal base) can do. This method allows the formation of very thick metal patterns, in which a metal thickness of more than 1 μm is achieved, with the thickness of the dielectric layer formed with the thick metal interconnect lines being able to exceed 2 μm. it can.

Although the invention has been described and illustrated with respect to particular exemplary embodiments, they are not intended to limit the invention to these exemplary embodiments.
Those skilled in the art will recognize that various changes and modifications can be made without departing from the spirit of the invention. Therefore,
All such variations and modifications that fall within the spirit of the invention and their equivalents are included in the invention.

[Brief description of the drawings]

FIG. 1 shows a silicon substrate on which a conventional fine-wire interconnect network is formed, on which a passivation layer is deposited and which feeds and / or passes through the passivation layer for connection to the outside world. FIG. 4 is a cross-sectional view of a silicon substrate provided with a ground pin. The structure shown in cross-section in FIG. 1 handles only conventional power and ground wiring networks and is limited thereto.

FIG. 2 shows a silicon substrate on which a conventional fine wire interconnect network is formed, on which a passivation layer is deposited, and clocks and / or through the passivation layer for connection to the outside. FIG. 3 is a cross-sectional view of a silicon substrate provided with signal pins. The structure shown in cross-section in FIG. 2 handles only conventional clock and signal wiring networks and is limited to this.

FIG. 3a is a cross-sectional view of a silicon substrate on which an interconnect network according to the present invention has been formed. Power supply and / or ground pins are provided through the surface of the dielectric layer for connection to the outside. The structure shown in cross section in FIGS. 3a and 3b handles only the power and ground wiring network of the present invention and is limited thereto. FIG. 3b shows the difference between the power and ground wiring lines below the passivation layer and the power and ground wiring lines above the passivation layer.

FIG. 4a is a cross-sectional view of a silicon substrate on which an interconnect network according to the present invention has been formed. ESD and / or driver and / or receiver circuit access pins are provided through the surface of the dielectric layer for external connections. The structure shown in cross-section in FIGS. 4a and 4b handles only the clock and signal wiring network of the present invention and is limited thereto. FIG. 4b illustrates the difference between the clock and signal wiring lines under the passivation layer and the clock and signal wiring lines above the passivation layer.

FIG. 5a is a cross-sectional view of a silicon substrate on which an interconnect network according to the present invention has been formed. No I / O connection pins are provided to penetrate the surface of the dielectric layer for connection to the outside. The structure shown in cross-section in FIGS. 5a and 5b handles only the clock and signal wiring network of the present invention and is not limited thereto. FIG.
FIG. 4 is a diagram showing a difference between a clock and signal wiring line below a passivation layer and a clock and signal wiring line above a passivation layer.

FIG. 6 is a cross-sectional view of an interconnect scheme according to the invention of the above-mentioned continuation-in-part application.

FIG. 7a is a cross-sectional view of a simplified version of a substrate and layers formed on the surface of the substrate by the process of the continuation-in-part application referenced above. FIG.
FIG. 7b is a cross-sectional view of FIG. 7a with an inductor added over the passivation layer.

[Explanation of symbols]

 10, 40 Silicon substrate 12 Dielectric layer 14 Interconnect layer 16 Electrical contact 18, 62 Passivation layer 20 Thick layer 21 Conductive plug 22, 36, 38 Opening (via) 26, 28 Pad 42 Semiconductor device 44, 45 ESD circuit 60 Fine wire interconnect layer (network) 61, 63, 67 Via 64 Dielectric layer 65 Power or ground bus 68 Power or ground pin 72 Clock or signal bus

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) EE52 EE54 EE56 EE58 GG10

Claims (46)

[Claims] 1. A post-passivation interconnect structure comprising: one or more internal circuits with one or more active devices formed in and on a semiconductor substrate; and in and on said semiconductor substrate. One or more ESD circuits formed; a fine metallization system formed on the semiconductor substrate as one or more thin dielectric layers; a passivation layer on the fine metallization system; A thick and wide metallization system formed above the passivation layer as the thick dielectric layer, wherein the thick dielectric layer is thicker than the thin dielectric layer and the thick and wide metallization system. Are used as wiring networks for electrical stimulation, said thick and wide metallization system comprising said one or more ESD circuits, said one or more internal circuits and at least Interconnect structure wherein the One of which is connected to the off-chip contact pin. 2. The ESD circuit and the one or more vias formed by the interconnect network through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. The interconnect structure of claim 1, wherein said interconnect structure is connected to said internal circuit. 3. The interconnect structure of claim 2, wherein said electrical stimulus comprises a power supply or a ground voltage. 4. The interconnect structure of claim 3, wherein said ESD circuit is connected in parallel to said one or more internal circuits via said wiring network. 5. The wiring network acts as a global wiring for the power or ground voltage, and the via is further connected to a local power / ground wiring network formed in the fine metallization system. The interconnect structure of claim 3, wherein 6. The interconnect structure according to claim 2, wherein said electrical stimulus comprises a clock or a signal voltage. 7. The circuit of claim 6, further comprising a driver, receiver or I / O circuit connected in series between said one or more off-chip contact pins and said wiring network. Interconnect structure. 8. The interconnect structure according to claim 7, wherein said ESD circuit is connected in parallel to said driver, receiver or I / O circuit. 9. The wiring network serves as a global wiring for the clock or signal voltage, and the via is further connected to a local clock / signal wiring network formed in the fine metallization system. The interconnect structure of claim 6, wherein 10. The interconnect structure of claim 1, wherein the metal in the thick and wide metallization system has a thickness greater than about 1 μm. 11. The interconnect structure of claim 1, wherein said one or more thick dielectric layers each have a thickness greater than about 2 μm. 12. A post-passivation interconnect structure comprising: one or more internal circuits with one or more active devices formed in and on a semiconductor substrate; and in and on said semiconductor substrate. One or more ESD circuits formed; a fine metallization system formed on the semiconductor substrate as one or more thin dielectric layers; a passivation layer on the fine metallization system; A thick and wide metallization system formed above the passivation layer as the thick dielectric layer, wherein the thick dielectric layer is thicker than the thin dielectric layer and the thick and wide metallization system. Are used as feed or ground wiring networks for the feed or ground inputs, respectively, wherein said thick and wide metallization system comprises said one or more internal circuits and at least one Interconnect structure characterized in that it is connected to off-chip contact pin. 13. One or more Es formed in and on said semiconductor body, connected to said wiring network, and connected in parallel to said one or more internal circuits.
The interconnect structure of claim 12, further comprising an SD circuit. 14. The ESD network and the one or more of the above, wherein the interconnect network is formed by a via formed through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. 14. The interconnect structure according to claim 13, wherein the interconnect structure is connected to the internal circuit. 15. The wiring network acts as a global wiring for the power or ground input, and wherein the vias are further formed in a local metallization system formed in the fine metallization system.
13. The interconnect structure of claim 12, connected to a ground wiring network. 16. The interconnect structure of claim 13, wherein there is one or more ESD circuits for each of said off-chip contact pins. 17. The interconnect structure of claim 12, wherein the metal in the thick and wide metallization system has a thickness greater than about 1 μm. 18. The interconnect structure of claim 12, wherein said one or more thick dielectric layers each have a thickness greater than about 2 μm. 19. A post-passivation interconnect structure, comprising: one or more internal circuits with one or more active devices formed in and on a semiconductor substrate;
A thin metallization system formed on the semiconductor substrate as a thinner or more thin dielectric layer; a passivation layer on the thinner metallization system; and one or more thick dielectric layers above the passivation layer. A thick and wide metallization system formed, wherein the thick dielectric layer is thicker than the thin dielectric layer and the thick and wide metallization system is used as a wiring network for clock or signal voltages. An interconnect structure wherein said thick and wide metallization system is connected to said one or more internal circuits. 20. The one or more internal circuits, wherein the wiring network is formed by vias formed through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. 20. The interconnect structure of claim 19, wherein the interconnect structure is connected to: 21. The wiring network acts as a global wiring for the clock or signal voltage, and the vias further connect to local clock or signal wiring networks formed in the fine metallization system, respectively. 21. The interconnect structure of claim 20, wherein 22. The interconnect structure of claim 19, wherein the metal in the thick and wide metallization system has a thickness greater than about 1 μm. 23. The interconnect structure of claim 19, wherein said one or more thick dielectric layers each have a thickness greater than about 2 μm. 24. A method of forming a post-passivation interconnect, comprising: forming one or more internal circuits in a semiconductor body and having one or more active devices thereon; Forming one or more ESD circuits formed thereon; forming a fine metallization system on the semiconductor substrate as one or more thin dielectric layers; and forming the fine metallization system Depositing a passivation layer thereon; and forming a thick and wide metallization system above the passivation layer as one or more thick dielectric layers, wherein the thick dielectric layer is thin. The thick and wide metallization system, which is thicker than the dielectric layer, is used as a wiring network for electrical stimulation, and the thick and wide metallization system includes one or more E D circuit, wherein the connected to the one or more internal circuits and at least one off-chip contact pin. 25. The ESD circuit and one or more of the above, wherein the interconnect network is formed by a via formed through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. The method according to claim 24, wherein the method is connected to the internal circuit. 26. The method of claim 25, wherein the electrical stimulus comprises a power or ground voltage. 27. The method of claim 26, wherein said ESD circuit is connected in parallel to said one or more internal circuits via said wiring network. 28. The interconnect network acts as a global interconnect for the power or ground voltage, and the vias further include a local power / power supply formed in the fine metallization system.
The method of claim 26, wherein the method is connected to a ground wiring network. 29. The method according to claim 25, wherein said electrical stimulus comprises a clock or a signal voltage. 30. The method of claim 29, further comprising connecting a driver, receiver or I / O circuit in series between said one or more off-chip contact pins and said wiring network. the method of. 31. The method according to claim 30, wherein said ESD circuit is connected in parallel to said driver, receiver or I / O circuit via said wiring network. 32. The wiring network acts as a global wiring for the clock or signal voltage, and the via is further connected to a local clock / signal wiring network formed in the fine metallization system. 30. The method of claim 29, wherein: 33. The method of claim 24, wherein the metal in the thick and wide metallization system has a thickness of greater than about 1 μm. 34. The method of claim 24, wherein said one or more thick dielectric layers each have a thickness greater than about 2 μm. 35. A method of forming a post-passivation interconnect, comprising: forming one or more internal circuits in a semiconductor substrate and having one or more active devices thereon; And one or more E
Forming an SD circuit; forming a thin wire metallization system on the semiconductor substrate as one or more thin dielectric layers; depositing a passivation layer on the thin wire metallization system; Forming a thick and wide metallization system above the passivation layer as one or more thick dielectric layers thicker than the dielectric layer, wherein the thick and wide metallization system is powered or grounded, respectively. A method for use as a power or ground wiring network for an input, wherein said thick and wide metallization system is connected to said one or more internal circuits and at least one off-chip contact pin. 36. One or more ESs in and on said semiconductor body, connected to said wiring network and connected in parallel to said one or more internal circuits.
The method of claim 35, further comprising forming a D-circuit. 37. The ESD circuit and the one or more of the above, wherein the interconnect network is formed by a via formed through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. The method according to claim 36, wherein the method is connected to the internal circuit. 38. The interconnect network acts as a global interconnect for the feed or ground input, and the via further comprises a local feed / power supply formed in the fine metallization system.
The method of claim 35, wherein the method is connected to a ground wiring network. 39. The method of claim 36, wherein there is one or more ESD circuits for each of said off-chip contact pins. 40. The method of claim 35, wherein the metals in the thick and wide metallization system have a thickness greater than about 1 μm. 41. The method of claim 35, wherein the one or more thick dielectric layers each have a thickness greater than about 2 μm. 42. A method of forming a post-passivation interconnect, comprising: forming one or more internal circuits with one or more active devices in and on a semiconductor substrate; Forming a thin line metallization system on the semiconductor substrate as a thin dielectric layer; depositing a passivation layer on the thin line metallization system; one or more layers thicker than the thin dielectric layer Forming a thick and wide metallization system above the passivation layer as a dielectric layer, wherein the thick and wide metallization system is used as a wiring network for clock or signal voltages; A method wherein a wide range of metallization systems are connected to the one or more internal circuits. 43. The one or more internal circuits, wherein the wiring network is formed by vias formed through the one or more thick dielectric layers, the passivation layer and the one or more thin dielectric layers. 43. The method of claim 42, wherein the method is connected to: 44. The wiring network acts as a global wiring for the clock or signal voltage, and the vias further connect to local clock or signal wiring networks formed in the fine metallization system, respectively. 44. The method of claim 43, wherein the method is performed. 45. The method of claim 42, wherein the metal in the thick and wide metallization system has a thickness greater than about 1 μm. 46. The method of claim 42, wherein said one or more thick dielectric layers each have a thickness greater than about 2 μm.