JP2792628B2 - Semiconductor device - Google Patents

Description

The present invention relates to an output buffer, and more particularly, to an output buffer in a CMOS (complementary metal oxide semiconductor) integrated circuit.

Industrial Applications One of the well-known causes of electronic integrated circuit failure is exposure to a large amount of rapid electrostatic discharge. In the manufacture and use of integrated circuits, devices and humans often charge a significant amount of charge due to triboelectricity that accumulates due to the contact and subsequent separation of different materials.
This charged charge is rapidly discharged when the charged object comes into contact with the integrated circuit, especially when that portion of the circuit is connected to a power source that includes the device ground. This discharge
Significantly for integrated circuits, due to dielectric breakdown of oxides and other thin films, and also to high levels of conduction through relatively small areas of the circuit resulting from reverse breakdown of pn junctions on the circuit. Cause damage. In particular, if the diode enters the negative resistance region of its diode collapse characteristics and a sufficient current flows to melt conductive materials such as polycrystalline silicon and aluminum due to resistance heating, damage will be severe. The molten material flows along the electric field, causing a short circuit such as a short circuit between the source and drain of the MOSFET.
It is assumed that the short circuit remains even after the completion of the electrostatic discharge, and the integrated circuit becomes useless.

Quantifying the sensitivity of an integrated circuit to electrostatic discharge is based on measuring the integrated circuit sample in a known state of electrostatic discharge such that the charge and discharge characteristics are controlled in a known manner. Done. One test method is MIL-STD-883C, published by the U.S. Department of Defense, Method 3015.3, Standard "Test Methods for Microelectronics.
d and Procedures for Microelectronics). This method uses a "human body model" consisting of a 100pF capacitor connected in series with a 1500Ω resistor.
Is used. Experience has shown that exposing an integrated circuit to a discharge through this equivalent circuit is a good approximation of electrostatic discharge from the human body. The sensitivity threshold of a given circuit design is measured by the capacitor repeatedly boosting the voltage charged before discharging its charge to the terminals of the circuit. The failure threshold is
Circuits as low as 2000 volts or less, for example, require special precautions in their manufacture and handling during use, in addition to the manufacturing costs of both the manufacturer and the user. Of course, for more sensitive circuits, the actual number of electrostatic discharge failures will be higher, adding to the cost of manufacture and use. It is desirable that the fault threshold voltage be as high as possible for both the manufacturer and the user of the integrated circuit.

To reduce the sensitivity of integrated circuits to electrostatic discharge (ESD), modern integrated circuits are designed with protective devices on their external terminals. The intent of providing such a protective device is to provide a path for the static charge to flow safely, and such a safe path design may cause damage even if the electrostatic discharge flows to the attached terminals of the charged object. It's not like that. Such circuits include diffused resistors and punch-through diodes. An example of such a protection device is the thick field oxide transistor described in U.S. Pat. No. 4,692,781 and Japanese Patent Application No. 60-122365 (Japanese Patent Application Laid-Open No. 61-44471). An example of a protection device for a complementary metal-oxide-semiconductor (MOS) integrated circuit is described in Japanese Patent Application No. 62-88589 (Japanese Patent Application Laid-Open No. 62-295448) assigned to Texas Instruments.

Traditionally, output buffer circuits have not included such devices for a variety of reasons. In a sufficiently large integrated circuit, the transistors in the push-pull output buffer are large enough to safely handle the presence of a significant amount of electrostatic discharge current at the output terminals. Thus, the characteristics of the output terminal against electrostatic discharge protection were often better than those of the input terminal of the device. Since the electrostatic discharge protection in an integrated circuit is no longer as good as that of its weakest terminal, there is no motivation to improve the performance of the output buffer as long as the input terminal is weaker than the push-pull drive circuit. Further, adding a protection device to the output terminal of the integrated circuit often does not provide protection because the turn-on voltage of such a protection device is often greater than the turn-on voltage of the output drive circuit itself for ESD events.

The technology for manufacturing integrated circuits has become more advanced, and the features used to implement components in integrated circuits have become smaller, thus reducing the cost of silicon in the circuit and increasing its operational performance. However, as transistor dimensions have become smaller, the ability of the push-pull output buffer to safely discharge static charge without damaging the circuit has decreased. In addition, electrostatic discharge protection for output buffers has become important for some circuits now, as improvements to the input terminals of the integrated circuit have advanced beyond the protections provided by push-pull drive circuits.

OBJECTS OF THE INVENTION Accordingly, one object of the present invention is to obtain an output buffer with advanced ESD sensitivity.

Yet another object of the present invention is to obtain such an output buffer using CMOS technology.

Yet another object of the present invention is to provide such a branching output path by providing a branch current path that keeps the terminal voltage below the breakdown threshold of the reverse biased diode appearing at the terminal. Is to get.

Other objects of the present invention will become apparent to those skilled in the art from the following detailed description with reference to the drawings.

SUMMARY OF THE INVENTION The present invention is applied to an output buffer to provide protection against reverse bias collapse of an n-channel pull-down transistor resulting from an ESD event. The n-channel pull-down transistor is formed in the p-type region of the substrate and has a drain connected to the output of the output buffer, a source connected to the first reference power supply, and a gate controlled by an input to the output buffer. . Like an n-well in CMOS technology, a diode is formed by p-type diffusion formed in an n-type region of a substrate. This p-type spreading is connected to the output of the output buffer. The n-well is connected to a second reference power source at a location near the p-type diffusion.
This connection is preferably made to an n-type diffusion in the n-well. The distance between the p-type diffusion and the connection to the n-well is limited to a distance that provides a sufficiently small "on" resistance, and if the p-type region is positively biased with respect to the second reference power supply, n
The pn junction formed by the drain of the channel device does not lead to reverse bias collapse, thus preventing damage to the circuit. This diode can be used in a p-channel pull-up device in a CMOS output buffer.

That is, an output buffer according to the present invention is an output buffer formed on a surface of a semiconductor substrate, comprising: a first conductivity type source diffusion region having a plurality of elongated edges; a plurality of elongated channel regions; A first MOS transistor including a plurality of elongated drain diffusion regions of the first conductivity type connected to an output terminal through an elongated contact area of the first MOS transistor; and a plurality of elongated diffusion regions of a second conductivity type. Each of the plurality of elongate channel regions is disposed adjacent to one of the plurality of elongate edges and formed above the surface for controlling the conductivity of each of the elongate channel regions. Wherein each of the plurality of elongated drain diffusion regions is disposed adjacent to one of the plurality of elongated channel regions. Each of which is connected to a reference terminal via a different one of the second plurality of elongated contact areas and is opposite to one of the plurality of elongated channel regions. Are closely spaced from one side of the elongated drain diffusion region.

An output buffer according to the present invention is an output buffer formed on a surface of a semiconductor substrate, wherein the MO is formed in a first region of a first conductivity type of the substrate.
An S transistor; and a low-resistance diode formed at least partially in a second region of a second conductivity type of the substrate, wherein the MOS transistor has a source diffusion region of the second conductivity type; A channel region disposed adjacent to the source diffusion region, the channel region having a gate electrode formed above the surface for controlling the conductivity of the channel region, the channel region being connected to an output terminal; A drain diffusion region of the second conductivity type, wherein the low resistance diode is connected to the output terminal via a first elongated contact area. And a plurality of second elongate diffusion regions of the second conductivity type, each of the second elongate diffusion regions being via a different one of the second plurality of elongate contact areas. It is connected to the terminal and is spaced closely from the side of the one to be opposite to the first elongated diffusion region of the plurality of second elongated diffusion region.

Embodiment First, referring to FIG. 1, an n-channel transistor 10 will be described.
Are used in a pull-down device in a push-pull output buffer according to the prior art. Transistor 10
Since is an n-channel, it is made in a silicon-chip p-type substrate 5. Bond pad 2 is an output terminal and is connected to drain region 6 of transistor 10 by aluminum or other metal line 4. The source region 8 is also connected by a metal line 4 to a reference power supply V _ss which supplies the ground for the integrated circuit. The source region 8 and the drain region 6 are n-type diffusions into each p-type substrate, and such diffusions are made by a well-known diffusion process called ion implantation followed by drive-in diffusion. The connection between the diffusions 6, 8 and the metal lines 4 is made by contacts 12, such contacts being etched into the dielectric film 13 insulating the diffusions 6, 8 from the metal lines 4. It is formed by opening and pattern processing. Gate electrode 14 has an overlap in the space between source region 8 and drain region 6, is insulated therefrom by a thin gate oxide, and is connected to the input node of the output buffer. The gate electrode 14 is made of polycrystalline silicon, and is generally deposited and patterned before diffusion of the source region 8 and the drain region 6. This is a method of obtaining a self-aligned MOS transistor well known to those skilled in the art. FIG. 1a is a cross-sectional view of a portion of the transistor 10 of FIG.

If an electrostatic charge having a negative potential with respect to V _ss is applied to the bond pad 2, the pn junction at the interface between the drain region 6 and the p-type substrate 5 will be forward biased. This forward-biased diode has the ability to conduct large currents to the power supply to which substrate 5 is connected, and therefore the output buffer using transistor 10 has a high fault threshold (the channel length of transistor 10 is approximately In the case of 2 microns, it generally has 8000 volts according to the above cited reference 3015.3).

However, for an electrostatic charge having a positive potential with respect to V _ss , the diode between the drain region 6 and the substrate 5 will be reverse-biased. Once the voltage developed by the ESD event exceeds the reverse bias breakdown voltage of this diode, the source region 8 from the drain region 6 via the substrate 5
The current flows to This is because a parasitic npn bipolar transistor is formed in the structure shown in the figure using the drain region 6 as a collector, the substrate 5 as a base and the source region 8 as an emitter. This conduction protects the rest of the integrated circuit depending on the level of discharge. However, a large amount of heat is generated by the current flowing through the collapsed reverse-biased diode. The generation of heat due to this resistance heating is exacerbated by the thermal generation of the intrinsic carrier in the substrate 5, causing the second breakdown of the parasitic npn transistor, and the current from the drain region 6 to the source region 8. Is further increased, leading to more heat generation. If the heat generated by this resistance heating is large enough, the metal 4 in the contact 12 will melt and flow along the electric field to the source region 8, as shown by the filament 4 'in FIG. 1b. Further, the generated heat reaches the gate electrode 14 through the thin gate oxide 15, and the polycrystalline silicon filament 14 'shorts the gate electrode 14 to the drain region 6, or further, the polycrystalline silicon filament 14 " This causes the electrode 14 to be shorted to the source region 8. Of course, such a filament renders the transistor inoperable.

Recent advances in integrated circuit manufacturing technology have been directed toward reducing the series resistance of the conductive materials used therein. Among these advances is the "cladding" technique of depositing silicide films on diffusion and polycrystalline conductors. This cladding is performed by obtaining a titanium silicide layer on the surface of silicon by a direct reaction between a metal such as titanium and an underlying monocrystalline silicon or polycrystalline silicon layer.
Referring to FIG. 1c, there is shown a cross section of a transistor formed from this clad diffusion region and polycrystalline silicon. The silicide film 19 is shown on the surface of the drain region 6, the source region 8, and the gate electrode 14. FIG. 1c also shows that the failure threshold of transistor 10 is
When used to lower the resistance of these layers, it shows that the silicide filaments 19 'are reduced due to the heat generated by the reverse bias conduction as described above. The distance between the filament forming material (here silicide 19) and the local hot part (junction between the drain region 6 and the substrate 5) is such that the aluminum metal wire 4 shown in FIG. 1b supplies the filament material. Because it is shorter than in the case, the failure threshold is reduced.

Certain methods have been used to improve the output buffer threshold by using n-channel transistors as pull-down devices. Referring to FIG. 2, the method used in the prior art is shown,
It is shown as increasing the fault threshold of transistor 10 for a positively biased ESD event. Transistor 10 is configured according to a "ladder" structure and includes a plurality of drain regions 6 and source regions 8 each having a gate electrode 14 therebetween. The ladder structure shown in FIG. 2 has an equivalent transistor width of four times the width of transistor 10 of FIG. 1 (assuming all other dimensions are the same), so that in reverse bias collapse The local current density at the pn junction at the end of the drain region will be reduced, thus reducing the associated local heating. Further, the formation of a metal filament as shown in FIG. 1b can be minimized by placing the contact 12 a sufficiently large distance from the gate electrode 14 as shown by the dimension DS in FIG. Local heat at the end of the region 6 is dissipated before reaching the metal wire 4.

A similar phenomenon occurs in the ESD stress of the CMOS output buffer circuit. An inverting push-buffer circuit implemented by CMOS is shown schematically in FIG. In this configuration, p-channel transistor 20 acts as a pull-up device, and n-channel transistor 10 acts as a pull-down device, as described above. The path from the source to the drain of the p-channel transistor 20 is connected between the positive supply voltage V _dd (to the source of the transistor 20) and the output terminal OUT (the drain of the transistor 20), while the path from the source of the n-channel transistor 10 The path to the drain is the reference power supply V _ss (source of transistor 10) and the output terminal OUT
(Drain of the transistor 10). The gate of transistor 10 is connected to input IN ₁₀ to the output buffer, and the gate of transistor 20 is connected to input IN ₂₀ to the output buffer. Inputs IN ₁₀ and IN ₂₀ are made according to the function of the integrated circuit. Input IN ₁₀ is essentially input IN ₂₀
Therefore, the output buffer of FIG. 3 operates essentially as a CMOS inverter. But with input IN ₁₀
IN ₂₀ is offset from each other during switching of terminal OUT so that transistor 10 and transistor 20 do not conduct simultaneously. Such deviations, those skilled in the art as well known, can be obtained cowpea the logic circuit predriver used to generate the input IN ₁₀ and IN _20.

FIG. 4 is a cross-sectional view of a typical CMOS output buffer corresponding to the circuit diagram of FIG. 3 and constructed in accordance with the prior art. The output buffer of FIG. 4 is a p-type epitaxial layer 5 '.
Prepared therein, this layer 5 ′ is a lightly doped p-type layer grown on a p-type substrate 5. Epitaxy layer 5 '
The use of CMOS, as is well known to those skilled in the art,
Useful for reducing the latch-up sensitivity of the circuit. n
The channel transistor 10 connects the drain region 6 to the output terminal through the metal line 4 and connects the source region 8 to V _ss through the metal line 4 as described above with reference to FIG. 1 (both connections are shown in FIG. 4 for clarity). ). Source region 8 and drain region 6
Is formed in the epitaxial layer 5 'as described above.
Type diffusion. The gate electrode 14 again overlaps the channel region between the source region 8 and the drain region 6 and is separated therefrom by a gate oxide 15.

A p-channel transistor 20 is formed in n-well 22;
N well 22 is an n-type diffusion into epitaxial layer 5 '. The p-channel transistor 20 has its p-type drain region 26 connected to the output terminal by a metal line 4 and its p-type source region 28 connected to _Vdd by another metal line 4.
Source region 28 and drain region 26 are p-type diffusions made into n-well 22 by diffusion and ion implantation techniques well known to those skilled in the art. Polycrystalline silicon gate electrode 24 overlaps the channel region between source region 28 and drain region 26 and is separated therefrom by a thin gate oxide 15, as in transistor 10. The p-channel transistor 20 is, of course, a self-aligned transistor formed by depositing and patterning a gate electrode before forming the p-type diffusions 26 and 28. Gate electrode 24 is transistor 10
To the gate electrode 14 to receive an input signal to the output buffer.

An additional n-type diffusion 30 is provided in the n-well 22 to provide V _dd
Connected. As is well known to those skilled in the art, if n-well 22 is connected to the same potential as the most positively biased p-type diffusion in n-well 22, latch-up can be essentially prevented. . The n-type diffusion 30 in FIG. 4 is more heavily doped than the n-well 22 for the purpose of easily achieving ohmic contact to the metal 4 (not shown). The connection of n well 22 to V _dd is connected to source region 28 and n _dd
The pn junction to well 22 is prevented from being forward biased, thus preventing the CMOS output buffer of FIG. 4 from latching up. The position of the n-type diffusion 30 is such that the connection is at the n-well 22
According to the conventional shape of the CMOS output buffer, it has not been strict as long as it is made somewhere in. In general, it has been performed to form the n-type diffusion 30 in a ring shape around the n-well 22. This is done not only to avoid layout collisions, but also to reduce the possibility of latch-up caused by charge injection from circuits outside the n-well 22. FIG. 4a is a plan view of the output buffer of FIG. 4 and shows the presence of guard ring diffusion 30. FIG.

A parasitic equivalent circuit for the CMOS output buffer of FIGS. 3 and 4 is shown in FIG. In this circuit, the diode D _p corresponds to p-n junction between the drain region 26 and the n-well 22, R _p corresponds to the forward bias resistance of the diode. The n-well 22 is generally lightly doped compared to the drain region 26, and has a relatively high sheet resistance (tens of ohms per square in the drain region 26, on the order of thousands of ohms per square). Is). Therefore, R _p is p
It resides essentially in n-well 22 rather than in type drain diffusion 26. Similarly, the diode D _n corresponds to p-n junction between the drain region 6 and the epitaxial layer 5 ', R _n corresponds to the forward bias resistance of the diode, it is similar to that described with respect to R _p For this reason, it depends on the resistivity of the epitaxial layer 5 '. Diodes D _v are power supplies V _dd and V
_ss (for example, n
A diode between the well 22 and the epitaxial layer 5 ', the substrate 5 is generally in the V _ss), the capacitance C _v is the capacitance between them. In modern integrated circuits, especially those using CMOS, enough wiring to supply V _dd and V _ss is formed in the diffusion region, so that the value of the capacitance C _v is increased from 2000 _pF to 10 pF.
000 _pF range.

Referring now to FIG. 6, there is shown a circuit of the ESD source 49 of the human body model connected to the parasitic equivalent circuit of FIG. MI
As already mentioned for method 3015.3 of L-STD-883C,
This model has a capacitor 50 with a capacitance of 100pF and 1500Ω
Is connected in series with a resistor 52 having a value of
A relay 54 is connected between them to apply the charge stored in the capacitor 50 to the circuit under test by the D source 49. As apparent from FIG. 6, the parasitic capacitance C _v is removed from the equivalent circuit. Since the value of C _v is much greater than the value of 100 pF for capacitor 50 (and because the charging voltage of capacitor 50 is on the order of 5 volts, which is comparable to the value of V _dd ), a model of the behavior of the output buffer in response to ESD events For this purpose, it is assumed that V _ss and V _dd are common. Moreover, as it will become apparent from the following discussion, since the series resistance of the diode D _n and D _p would control the discharge path, even accuracy ignoring the effect of the diode D _v is a loss I can't.

In the positive polarity ESD event, the diode D _p is forward biased, the diode D _n is reverse biased. However, a voltage drop occurs when a current flows through the resistor R _p. As apparent from FIG. 6, if it current high enough level, the voltage drop in the reverse bias direction diode D _n may sometimes in excess of reverse Baiusu collapse voltage of it. As described above with respect to FIG. 1b, the parasitic npn
Due to the effect of the bipolar transistor, damage results from local heating when the drain-to-substrate diode collapses in the opposite direction. Therefore, for the purpose of ESD sensitivity, the value of R _p should be kept below a certain level and the transistor 10
Is desired to be avoided below a certain desired failure threshold.

The value for resistor R _p is for a given desired failure threshold can be readily calculated Te cowpea to knowing reverse bias decay threshold of the transistor 10. For example,
Assume that the desired failure threshold is 6000 volts using the human body model of the above cited MIL-STD-883C method 3015.3. The peak current appearing in bond pad 2 will then be 4 amps (6000 volts divided by the resistance of resistor 52, 1500Ω). The maximum value of R _p can be calculated from the following equation.

_{V Bn = V onp + (R} p × 4) where, V _Bn is reverse biased collapse voltage of the diode D _n, V
_onp is the forward bias voltage drop of the diode D _p (typically 0.7 volts for a silicon diode). For example,
If reverse bias collapse voltage of the diode D _n is 20 volts, R _p for avoiding a reverse bias collapse of the diode D _n
Can be calculated as follows:

R _p = (20.0−0.7) volts / 4 amps = 4.825Ω Such a parasitic “on” resistance has never been obtained with a conventional CMOS output buffer. Thus, such an output buffer is limited in its ESD sensitivity by the ability of transistor 10 to conduct the discharge safely with reverse bias decay.

Referring now to FIG. 7, there is shown a plan view of an output buffer constructed in accordance with the present invention. A sectional view of a portion of this output buffer is shown in FIG. The n-channel transistor 110 is the transistor 10 shown in FIG.
It is produced in the same manner as described above. Transistor 120 is an n-well 122
Inward, formed as shown for the CMOS output buffer of FIG. For example, n according to a preferred embodiment of the present invention.
The sheet resistance of well 122 is typically in the range of 1000 to 4000 Ω / □. Gate electrode 124 has four “fingers”, each of which overlaps the region of n-well 122 between drain region 126 and source region 128. As before, the drain region 126 and the source region 128 are p-type diffusions formed into the n-well 122 after deposition and patterning of the gate electrode 124, and thus the resulting transistor is self-aligned. For example, the sheet resistance of source region 128 and drain region 126 is typically between 30 and 40 ohms / square. Drain region 12
6 is connected to a metal wire 104 via a contact in an insulating dielectric, and is connected to a bond pad 102 (not shown) serving as an output terminal. Source area also contacts 11
2 through a metal wire 104 to a V _ss reference power supply. The gate electrode 124 is made of polycrystalline silicon as before and is connected to the input IN ₁₂₀ to the output buffer (corresponding to the terminal IN ₂₀ in the circuit diagram of FIG. 5). For the sake of simplicity, the cross-sectional view of FIG. 8 schematically shows the electrical connection by the metal wire 104.

On the opposite side of the drain region 126 from the source region, at a short distance D from the drain region 126, an additional n-type diffusion region 1
40 are formed in n-well 122. These diffusion regions 140, together with the source regions 128, are connected to the _Vdd reference power supply by contacts 112 and metal lines 104. As discussed above with respect to the parasitic model of FIG. 6, V _ss and V _dd can be considered in common for the purpose of the output buffer response to an ESD event. Diffusion region 140 is n-type, more heavily doped than n-well 120, and can be made by the same ion implantation and subsequent diffusion forming source region 108 and drain region 106 into n-channel transistor 110. it can. For example, the diffusion region 140 (and also the source region 1
08 and the typical sheet resistance of the drain region 106) is 20-3
It is in the range of 0Ω / □. The high doping concentration in the diffusion region 140, of course, allows for good ohmic contact between the metal line 104 and the diffusion region 140. The high doping further reduces the resistance in diffusion region 140, that is, the resistance between its end and contact 112, as compared to n-well 122. Therefore, the drain region 126 and the contact (V _dd
Potential) between the drain region 126
Between the edge of the diffusion region 140 and the edge of the diffusion region 140 within a distance D. The width W of each diffusion region 140 is the same as the width of the source region 128 and the drain region 126 in this example, and as will become apparent below, such a width reduces the series resistance between them. Help.

The distance D is designed to be sufficiently short so that the resistance between the drain region 126 and the _Vdd reference power supply is sufficiently small, and the drain region 1 in the n-channel transistor 110 is
The pn junction between 06 and the epitaxial layer 105 'does not collapse at a reverse bias from a positive polarity ESD event, as described above with respect to FIG. As described above in a model of FIG. 6, the resistance R _p is the drain region 12
The resistance between 6 and the _Vdd reference supply (in diffusion region 140) can be calculated as follows:

R _p = (R _sheet122 ) × (D / W _eff ) As an example, _{assume that} the value of the sheet resistance (R _sheet122 ) of the n-well 122 is 3000Ω / □ (within the above range).
The width W of each of the regions is about 250 microns in this example. As already described with respect to FIG. 2, the ladder structure provides an equivalent transistor width of four times the width of each channel. Similarly, the equivalent width between the source region 128 and the diffusion region 140 is also four times the width W of one of the regions 140, so _Weff is 1000 microns. For modern integrated circuits, such as the preferred embodiment of the present invention, the typical minimum spacing between p-type and n-type diffusions is 1.5 microns (also for transistors 110 and 120). Work as). The values described above using the above equation, 4.5Omu obtain the distance D using the value of 1.5 microns as the as the value of R _p.
As mentioned above, this value is the 6000 volt positive ESD of an n-channel transistor with a reverse decay voltage of 20 volts.
Meet the requirement to prevent backward collapse in events (human body model). Using the diffusion region 30 as shown in FIGS. 4 and 4a above, because of the distance of the diffusion region 30 from the drain region 28, the low resistance obtained in the diffusion region 140 of FIG. Will not get. Therefore, FIG. 4 and FIG.
The structure of FIG. 4a would not eliminate the reverse bias collapse of n-channel transistor 10 as in the case shown in FIG. 7 for n-channel transistor 110.

As is clear from FIG. 7, the n-channel transistor
110 is not in the arrangement according to the invention already described for transistor 120. For a negative ESD event appearing in the pond pad 102, the pn junction between the drain-in region 126 and the n-well 122 collapses with a reverse bias,
It has been found that the "second" collapse zone will not be reached. This is due to the lower mobility of the minority carriers in n-well 122 (compared to the mobility of electrons in epitaxial layer 105 '). Therefore, transistor 11
Additional layout intervals to reduce the series resistance R _n of 0 is not required for modern integrated circuits, the drain region
The junction between 126 and n-well 122 can safely conduct the discharge in reverse bias collapse. The preferred layout for n-channel transistor 110 would be the ladder structure of FIG. In that case, as described with respect to FIG. 2, the equivalent device width would provide additional protection in the event that an event occurs that exceeds the failure threshold that determined the distance D.
However, if the configuration of the p-channel transistor 120 is such that it becomes necessary to protect the p-channel transistor 120 from entering reverse bias collapse, then the configuration of the n-channel transistor 110 will be similar to that of the p-channel transistor shown in FIG. Note that, like transistor 120, this can be done by simply reversing the type of dopant in the source and drain regions and performing an additional diffusion corresponding to diffusion region 140.

As described above, the use of silicide to clad diffusion regions and polycrystalline silicon conductors in an integrated circuit causes a reverse bias collapse to occur (especially in the n-channel transistor 10 shown in FIG. 1C). ), Which worsens the failure of the output buffer. The output buffers shown in FIGS. 7 and 8 are particularly suited for use in such integrated circuits by using diffusion regions 140 with proper spacing in transistors 120. It has become. FIG. 9 is similar to that described above with respect to FIG. 1c,
FIG. 8 is a cross-sectional view of the output buffer of FIG. 7 constituted by using a diffusion region therein and a silicide film 119 for cladding polycrystalline silicon. Typical sheet resistance of the silicide film 119 is 1 to 2Ω / □. Accordingly, the resistance between diffusion region 140 and drain region 126 in transistor 120 of FIG. 7 is more limited to the region of n-well 122 therebetween. As discussed above with respect to FIGS. 7 and 8, the low series resistance R _p helps to keep the voltage at terminal OUT from rising above the reverse bias threshold voltage of transistor 120. I have. Thus, as long as the pn junction between drain region 106 and epitaxial layer 105 'does not collapse under reverse bias, the use of silicide film 119 does not adversely affect the sensitivity of the device to ESD events. As mentioned above, the distance D is specifically designed to avoid this operating region.

The ladder structure shown in FIGS. 7-9 for the transistor 120 reduces the surface area of the integrated circuit required to create the width required to reduce the resistance R _p below the calculated maximum. Note that it is used for Of course, the use of a ladder structure (ie
It is also possible to achieve the desired value of the resistance R _p without using one length of 0) or by other changes in the process and structure. However, it has been found that the ladder structure of FIG. 7 is desirable for current integrated circuits.

From the above description, the n-channel transistor 110 is inverted by the action of the diode between the drain region 126 and the n-well 122 and by reducing the series resistance by the diffusion region 140 and by connecting it to the _Vdd supply. It is clear that it has been prevented from becoming a bias collapse. Therefore, the transistor
The transistor operation of 120 is the operation of the n-channel transistor 112.
It is not required for ESD protection and is only useful as a pull-up device for a CMOS output buffer, as shown in FIG. The present invention can therefore be employed in non-CMOS output buffers by using the shapes shown in FIGS. 7 and 8, but by removing the gate electrode 124 and the source region 128. it can.

FIG. 10a is an example of such a non-CMOS output buffer in an open-drain configuration without using a pull-up device in an integrated circuit, which protects against ESD events by using a low series resistance diode according to the present invention. Have been. FIG. 10a shows a diode 120 '(p-type drain region).
126 and a resistor R _{120 ′} (a forward bias resistance of the diode 120 ′). By connecting the cathode of diode 120 'to power supply _Vdd at n-well 122, diode 120'
During the normal operation of the output buffer shown in the figure, it is surely reverse biased.

FIG. 10b shows another example of a non-CMOS output buffer, where the pull-up device is an n-channel transistor 130. The output buffer is protected by a diode 120 'and an associated resistor R _120' connected in parallel with transistor 130. The gate of the transistor 130 is input as in the case of the p-channel transistor described above.
Controlled by IN ₁₃₀ . Similar to transistor 110 described above, n-channel transistor 130 also has a voltage drop across diode 120 'and associated resistor R _120' that is less than the reverse bias collapse voltage of the diode from the drain of transistor 130 to the substrate. As long as the diode
Protected by 120 '. FIG. 10c schematically illustrates another output drive circuit that may be protected by a diode constructed in accordance with the present invention, wherein the pull-up device is a resistor 140. Resistor 140 may be any of the well-known integrated circuit resistors, such as polysilicon or a diffused resistor, and resistor 140 may also be a depletion mode n-channel transistor whose gate is connected to a V _dd power supply. Good. In this circuit, the series resistance, denoted by R _{120 ′} , is comprised of a diffusion resistance or depletion mode transistor whose value is low enough to prevent reverse bias breakdown of transistor 110 and reverse bias breakdown of resistor 140. As long as it stays at the value, the value of resistor 1 is sufficiently smaller than the value of resistor 140.
As long as the current drawn from 40 stays within its power consumption capacity, it is protected.

FIG. 11 shows a plan view of an output buffer constructed in accordance with this embodiment of the present invention, which has an open drain structure similar to that shown schematically in FIG. 10a. The construction of the diode 120 'according to this embodiment of the invention is the first
When used in the output buffer structure according to FIGS. 0b to 10c, they are identical. The pull-up device can be comprised of any of a number of well-known structures and is electrically connected in parallel with diode 120 '.

Transistor 110 is constructed in a manner similar to that shown in FIGS. The diode 120 'in FIG.
Is the transistor 12 described above with respect to FIGS. 6 and 7.
Except for 0, the gate electrode 124 and the source region 128, they are formed in the same shape and the same manner in the n-well 122 'in the same manner. The p-type region 126 'is a diffusion formed in the n-well 122' in the same manner as the drain region 126 described above with reference to FIGS. The p-type region 126 'is connected to the bond pad 102 (not shown) at the output terminal of the integrated circuit. An n-type diffusion region 140 'is formed within an n-well 122', as in transistor 110 of FIGS.
It is located a distance D from 6 'and is connected to a _Vdd power supply via a metal line 104'. In this example, the seventh
As shown, the width W of the diffusion region 140 'is the same as the width of the p-type region 126'. W of the same dimensions as the transistor 120 described above
And a diode 120 'having a series resistance R of about 4.5Ω.
_{120 '(i.e.} a six view R _p) Similarly has, when the positive polarity ESD event to follow connexion 6000 volts on the human body model is generated, the drain of the transistor 110 - to the diode reverse bias collapsed state between the substrate Prevent entry.

Although the present invention has been described in detail herein with reference to a preferred embodiment thereof, it will be understood that the description is by way of example and not limitation. Modifications to details of the embodiments of the invention and additional embodiments of the invention will be apparent to, and may be made by, those having ordinary skill in the art to which this description pertains. It should be understood that Such modifications and additional embodiments are to be considered within the spirit and scope of the invention as set forth in the appended claims.

 The following items are further disclosed with respect to the above description.

(1) An output buffer formed in a semiconductor surface of a substrate, a first field-effect transistor, mounted in the surface, connected to a first reference power source, and having a first conductivity type. A source region, mounted in the surface away from the source region, connected to the output of the output buffer; a drain region having a first conductivity type; mounted on the surface, remote from the source region, to form an output buffer; A first field effect transistor including a gate electrode coupled to an input, a first doped region in the surface having the first conductivity type, mounted in the first doped region. A second doped region, electrically connected to the output of the output buffer, having a second conductivity type, the first doped region being connected to the second buffer. Means for coupling to a second reference power source at a predetermined distance from the doped region, whereby the resistance between the second doped region and the second reference power source is increased. Is sufficiently low, and the electric charge whose potential at the junction between the drain region and the surface of the first field-effect transistor is significantly higher than that of the first reference power supply and the second reference power supply, is Means for preventing collapse when applied to the output of the output buffer.

(2) An output buffer according to the first term, wherein the applied charge results in an electrostatic discharge.

(3) The output buffer of item 1, wherein the predetermined distance is calculated with respect to a predetermined upper limit of the applied charge.

(4) The output buffer of paragraph (1), wherein said connection means is mounted in said third doped region and in said first doped region to said second reference power supply. An output buffer, comprising: a third doped region having an impurity concentration greater than that of the first doped region and having the first conductivity type.

(5) The output buffer of paragraph (4), wherein the third doped region is separated from the third doped region by:
An output buffer, such that the output buffer is separated by a distance that is substantially less than the width of the second doped region.

6. The output buffer of claim 5, wherein the width of the third doped region is substantially equal to the width of the second doped region.

(7) An output buffer according to the first term, wherein the first derivation type is an n-type.

(8) An output buffer formed in a semiconductor surface on a substrate, the first electric field having a source connected to a first reference power supply, a drain connected to an output of the output buffer, and a gate connected to an input of the output buffer. An effect transistor, a first doped region having a first conductivity type in the surface, disposed within the first doped region, and electrically connected to the output of the output buffer. A second doped region having a second conductivity type, a distance from the second doped region substantially less than a width of the second doped region. Means for connecting said first doped region to a second reference power supply.

(9) The output buffer according to item 8, wherein the first conductivity type is an n-type.

(10) The output buffer of paragraph (8), further disposed within said first doped region and spaced apart from said second doped region and electrically connected to said second reference power supply. A third doped region having the second conductivity type connected thereto, connected to an input of the output buffer, disposed on the first doped region, and connected to the second doped region; A first gate electrode separating the third region from the third doped region.

(11) The output buffer of paragraph 10, further disposed within said first doped region and electrically coupled to said output of said output buffer, from said second doped region. A fourth, spaced apart, of the second conductivity type,
A doped region coupled to the first gate electrode and disposed on the first doped region to separate the fourth doped region from the third doped region , Second
Connecting the first doped region to the second reference power source, wherein the fourth doped region is substantially less than the width of the fourth doped region from the fourth doped region. Sustaining means for causing the potential of the second reference power supply to appear at a remote location.

(12) An n-channel CMOS output buffer formed in a semiconductor surface on a substrate, wherein a source is connected to a first reference power supply, a drain is connected to an output of the output buffer, and a gate is connected to an input of the output buffer. Transistor, first n of said surface
An n-channel transistor fabricated in the mold region, wherein the first p-type region is electrically connected to the output of the output buffer in the first n-type region; a second p-type region disposed in the n-type region, electrically connected to a second reference power supply, and separated from the first p-type region by a first channel region; The first p-type region from the first p-type region by connecting the gate electrode disposed on the first channel region and the first n-type region to the second power supply. CMOS output buffers, comprising: p-channel transistors, including: sustaining means for causing the potential of the second reference power supply to appear at a distance substantially less than the width of the region.

(13) The output buffer according to the twelfth aspect, wherein the connection means is arranged in the first n-type region so as to be connected to the second reference power supply, and has a higher concentration than the first n-type region. An output buffer comprising: a second n-type region having an impurity concentration of

(14) The output buffer of the thirteenth term, wherein the second n
An output region such that a mold region is separated from the first p-type region by a second channel region and the length of the second channel is substantially less than its width. Batua.

15. The output buffer of claim 14, wherein the width of the second channel region is essentially the same as the width of the first channel region.

(16) A CMOS output buffer fabricated in a p-type semiconductor surface on a substrate, wherein a source is connected to a first reference power supply, a drain is connected to an output of the output buffer, and a gate is connected to an input of the output buffer. An n-channel transistor, the drain of which includes n-type diffusion in the surface, a p-channel transistor fabricated in a first n-type region of the surface, wherein the p-channel transistor is formed in the first n-type region. A first p-type region disposed and electrically connected to the output of the output buffer; a first p-type region disposed in the first n-type region and electrically connected to a second reference power supply; A second p-type region separated from the first p-type region by a first channel, a gate electrode connected to an input of the output buffer, and disposed on the first channel region, 1 n-type region The first reference power supply is connected to a second reference power supply so that the potential of the second reference power supply appears at a predetermined distance from the first p-type region. And when a charge having an order of magnitude higher than that of the second reference power supply is applied to the output of the output buffer, the resistance between the first n-type region and the second reference power supply is sufficient. A p-channel transistor, comprising: connecting means for preventing the junction between the drain region and the surface from being collapsed, the p-channel transistor being small.

(17) The output buffer according to paragraph 16, wherein the applied charge is due to electrostatic discharge.

(18) The output buffer according to paragraph 16, wherein the predetermined distance is calculated with respect to a predetermined upper limit of the applied charge.

[Brief description of the drawings]

FIG. 1 is a plan view of an n-channel pull-down transistor in an output buffer constructed in accordance with the prior art. FIG. 1a is a cross-sectional view of the transistor of FIG. FIG. 1b is a cross-sectional view of the transistor of FIG.
Figure 4 shows a typical failure mode that occurs with a D event. FIG. 1c is a cross-sectional view of the transistor of FIG. 1, which uses a silicide film on a conductor to illustrate another typical failure mode caused by an ESD event. FIG. 2 is a plan view of an n-channel pull-down transistor in another output buffer constructed in accordance with the prior art. FIG. 3 is a schematic circuit diagram of a CMOS output buffer. FIG. 4 is a cross-sectional view of a CMOS output buffer constructed according to the prior art. FIG. 4a is a plan view of the CMOS output buffer of FIG. FIG. 5 is a diagram showing a parasitic equivalent circuit of a CMOS output buffer;
It is a schematic circuit diagram. FIG. 6 is a schematic circuit diagram showing the circuit of FIG. 5 connected to an ESD source. FIG. 7 is a plan view of a CMOS output buffer constructed in accordance with the present invention. FIG. 8 is a cross-sectional view of a portion of the output buffer of FIG. FIG. 9 is a cross-sectional view of a portion of the output buffer of FIG. 7, illustrating the use of a silicide conductor. 10a to 10c are schematic circuit diagrams of a non-CMOS output buffer constructed according to another embodiment of the present invention. FIG. 11 is a plan view of the output buffer of FIG. 10a constructed in accordance with the present invention. Reference numeral 2 ... bond pad, 4 ... metal wire, 5 ... substrate, 6 ... drain region, 8 ... source region, 10 ... transistor, 12 ... contact, 13 ... dielectric film, 14 ... Gate electrode, 15 gate oxide, 19 silicide film, 20 p-channel transistor, 22 n-well, 24 gate electrode, 26 drain region, 28 source region, 30 n-type diffusion, 49: ESD source, 50: capacitor, 52: resistor, 54: relay, 102: bond pad, 104: metal wire, 105 ': epitaxial layer, 106: drain region .., 108 source region, 110 transistor, 112 contact 112, silicide film, 120 transistor, 120 'diode, 122 well n 124, gate electrode 126 drain Region, 128, source region, 130, transistor, 1 40 ... n-type diffusion region

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-260669 (JP, A) JP-A-60-123053 (JP, A) JP-A-61-29169 (JP, A) JP-A 59-260 169225 (JP, A) JP-A-58-197870 (JP, A)

Claims (18)

(57) [Claims] 1. A semiconductor device formed on a surface of a semiconductor substrate, comprising: a first conductivity type source diffusion region having a plurality of elongated edges; a plurality of elongated channel regions; and a first plurality of elongated contacts. A first MOS transistor including a plurality of elongated drain diffusion regions of the first conductivity type electrically connected to a terminal serving as a bond pad via an area;
A plurality of elongate diffusion regions of a second conductivity type, wherein each of the plurality of elongate channel regions is disposed adjacent to one of the plurality of elongate edges; A gate electrode formed above the surface for controlling conductivity, wherein each of the plurality of elongate drain diffusion regions is disposed adjacent to one of the plurality of elongate channel regions. Each of the plurality of elongate diffusion regions is connected to a reference terminal via a respective one of the second plurality of elongate contact regions, and a channel region of one of the plurality of elongate drain diffusion regions. Each of the first plurality of elongate contact areas and each of the second plurality of elongate contact areas are disposed adjacently from a side opposite to A semiconductor device including a plurality of contacts arranged in close proximity. 2. The method according to claim 1, wherein the first MOS transistor is formed in the first region of the second conductivity type on the substrate, so that each of the elongated drain diffusion region and one of the elongated diffusion regions is formed. 2. The semiconductor device according to claim 1, wherein a low-resistance PN junction diode that conducts a forward bias current between the terminal serving as the bond pad and the reference terminal is formed between the two. 3. The apparatus of claim 2, further comprising at least one extended diffusion region of the second conductivity type, wherein the extended diffusion region is connected to at least one end of each of the elongated diffusion regions. 13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, further comprising a second MOS transistor formed in the second region of the first conductivity type on the substrate, wherein the second MOS transistor has a source diffusion region of the second conductivity type. A channel region disposed adjacent to the source diffusion region, the channel region having a gate electrode formed above the surface for controlling conductivity of the channel region; and the bond pad. 3. The semiconductor device according to claim 2, further comprising: a drain diffusion region of the second conductivity type connected to the terminal that is: 5. The semiconductor device according to claim 1, wherein said first MOS transistor is a P-channel transistor.
5. The semiconductor device according to claim 4, wherein the semiconductor device is an OS transistor, and the second MOS transistor is an N-channel MOS transistor. 6. The semiconductor device according to claim 1, wherein said first MOS transistor is an N-channel transistor.
The semiconductor device according to claim 4, wherein the semiconductor device is an OS transistor, and the second MOS transistor is a P-channel MOS transistor. 7. A semiconductor device formed on a surface of a semiconductor substrate, wherein the MOS device is formed in a first region of a first conductivity type of the substrate.
A low-resistance PN junction diode at least partially formed in a second region of a second conductivity type of the substrate, wherein the MOS transistor has a source diffusion region of the second conductivity type; A channel region disposed adjacent to the source diffusion region, the channel region having a gate electrode formed above the surface for controlling the conductivity of the channel region; and a terminal being a bond pad. The second electrically connected to
A drain diffusion region of the first conductivity type, wherein the low resistance PN junction diode is electrically connected to a terminal that is the bond pad via a first elongated contact area. An elongate diffusion region, and a plurality of second elongate diffusion regions of the second conductivity type, each of the second elongate diffusion regions passing through each of the second plurality of elongate contact areas. A semiconductor device, which is connected to the reference terminal and is disposed close to the first elongated diffusion region. 8. The apparatus of claim 7, further comprising at least one extended diffusion region of the second conductivity type, wherein the extended diffusion region is connected to at least one end of each of the elongated diffusion regions. 13. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 7, wherein each of said first elongated contact area and said second plurality of elongated contact areas includes a plurality of contacts arranged close to each other. 10. Each of said first plurality of elongate contact areas is at least half the length of each of said elongate drain diffusion regions, and each of said second plurality of elongate contact areas is each 2. The semiconductor device according to claim 1, wherein the length is at least half the length of the elongated diffusion region. 11. The plurality of elongate diffusion regions are each disposed proximate one side of the plurality of elongate drain diffusion regions a distance less than one-tenth the length of the elongate diffusion regions. 11. The semiconductor device according to claim 10, wherein: 12. The first elongate contact area is at least half the length of the first elongate diffusion region, and each of the second plurality of elongate contact areas is connected to the plurality of second elongate contact areas. 8. The semiconductor device according to claim 7, wherein the length of each of the elongated diffusion regions is at least half. 13. A method according to claim 1, wherein each of said plurality of second elongate diffusion regions is close to said first elongate diffusion region by a distance less than one tenth of a length of said second elongate diffusion region. 13. The semiconductor device according to claim 12, wherein the semiconductor device is arranged in a manner as described above. 14. The semiconductor device according to claim 1, wherein the first MOS transistor is formed in the first region of the second conductivity type on the substrate, so that each of the elongated drain diffusion region and one of the elongated diffusion regions is formed. 12. The semiconductor device according to claim 10, wherein a low-resistance PN junction diode that conducts a forward bias current between the terminal serving as the bond pad and the reference terminal is formed between the two. 15. The method of claim 15, wherein each of the first plurality of elongated contact areas and the second plurality of elongated contact areas.
12. The semiconductor device according to claim 10, wherein each of the areas includes a plurality of contacts arranged close to each other. 16. The apparatus of claim 12, further comprising at least one extended diffusion region of the second conductivity type, wherein the extended diffusion region is connected to at least one end of each of the elongated diffusion regions. 14. A semiconductor device according to claim 13. 17. The semiconductor of claim 12, wherein each of the first elongated contact area and the second plurality of elongated contact areas includes a plurality of closely located contacts. apparatus. 18. A semiconductor device formed on a surface of a semiconductor substrate, comprising: at least one source region of a first conductivity type; a plurality of channels arranged adjacent to the source region, each having a plurality of gate electrodes. A plurality of regions of the first conductivity type, each of which is disposed adjacent to the channel region opposite to the source region and electrically connected to a terminal which is a bond pad via a first plurality of contact areas. A first MOS transistor including a drain region of at least two diffusion regions of at least two second conductivity types, each of the diffusion regions being connected to a reference terminal via a second contact area, A plurality of drain regions located on both sides of the first MOS transistor of the plurality of drain regions, the first plurality of contact regions being disposed in close proximity to the first plurality of contact transistors; Each of A and the second contact area includes a plurality of contacts arranged in proximity to the semiconductor device.