JP3185723B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a protection transistor for protecting an internal circuit from electrostatic breakdown.

[0002]

2. Description of the Related Art Conventionally, as a technique for protecting a semiconductor integrated circuit from an electrostatic breakdown phenomenon, for example, Japanese Unexamined Patent Publication No.
No. 59 is disclosed. Hereinafter, this conventional technique will be described. FIG. 4 is a circuit diagram showing a circuit configuration of the conventional semiconductor device. FIG.
FIG. 5 is a plan view showing a pattern layout corresponding to the circuit shown in FIG. FIG. 6 is a cross-sectional view showing a BB ′ cross section of FIG.

As shown in FIG. 4, when a high voltage pulse due to the entry of a positive charge is applied to an input / output terminal 41 which is a metal terminal, a surge current causes an output transistor 42 and a wiring 4
When the semiconductor device flows through the gate driver circuit (not shown) through the input resistor 43 or through the input resistor 43 and the wiring 401 to the internal circuit, the semiconductor device may fail. For this reason,
A protection transistor 44 forming a discharge path is provided near the input / output terminal 41 of the internal circuit. The protection transistor 44 is formed of a bipolar transistor having a large current capacity, and becomes conductive when a high-voltage pulse is applied to clamp the applied voltage.

[0004] As shown in FIG.
Is configured as an n-type LDD structure MOSFET having n-type diffusion layers 46 and 47 and a gate electrode 48 formed on the surface of a p-type semiconductor substrate 45. Note that a gate oxide film 55 is interposed between the p-type semiconductor substrate 45 and the gate electrode 48. The n-type diffusion layer 46 serving as the source of the output transistor 42 is connected to the installation by an aluminum wiring 49. The n-type diffusion layer 47 serving as the drain of the output transistor 42 is connected to the input terminal 41 (FIGS. 4 and 5) by an aluminum wiring 50. The gate electrode 48 and the aluminum wirings 49 and 50 are insulated by the sidewall 56 and the interlayer insulating film 57.

On the other hand, the protection transistor 44 comprises an npn bipolar transistor having a p-type semiconductor substrate 45 as a base, an n-type diffusion layer 47 as a collector, and an n-type diffusion layer 51 as an emitter. The n-type diffusion layer 47
And n-type diffusion layer 51 are insulated by field oxide film 58. The n-type diffusion layer 47, which is the collector of the protection transistor 44, is connected to the input / output terminal 41 by the aluminum wiring 50, and the n-type diffusion layer 51, which is the emitter of the protection transistor 44, is connected to the ground line by the aluminum wiring 52. Is done. Then, a p-type semiconductor substrate 45 serving as a base
Are connected to an aluminum wiring 52 via ap ^{+ type} diffusion layer 60 as shown in FIG.

Such a semiconductor device has an output transistor 4
2 and the collector of the protection transistor 44,
It is formed commonly as the n-type diffusion layer 47, and has a structure in which the pattern area is reduced and no extra capacitance is added to the input / output terminal 41. Further, as shown in FIGS. 4 and 5, in the conventional semiconductor device, the distance S between the gate electrode 48 of the output transistor 42 and the contacts 53 and 54 is reduced.
1, the resistance value of the parasitic resistance 402 determined by S2, and the effective channel length L1 of the output transistor 42 is equal to the effective base width L2 of the protection transistor 44.
About the same.

[0007]

By the way, in the above-mentioned conventional semiconductor device, when a high voltage pulse caused by the entrance of the electrostatic charge is applied to the input / output terminal, the output transistor operates as a parasitic bipolar transistor. That is, the surge current input to the input / output terminal does not always flow through the protection transistor. Then, there is a problem that the surge current flows to an output transistor or an internal circuit to be protected and the semiconductor device is destroyed. Further, in the case where the output transistor has an LDD structure in order to achieve an integrated circuit of the semiconductor device, the electrostatic breakdown resistance of the output transistor is reduced due to the structure, so that the electrostatic breakdown phenomenon of the semiconductor device is likely to occur. Problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and enables an output transistor and an internal circuit to be protected from an electrostatic breakdown phenomenon by a circuit configuration having a minimum pattern area. The purpose is to:

[0009]

SUMMARY OF THE INVENTION The semiconductor device of the present invention, first is connected to the metal terminals provided on a semi-conductor substrate, the formed in the region of the first conductivity type and the metal terminals of the semiconductor substrate An output transistor having a drain of a first diffusion layer of two conductivity type and a source of a second diffusion layer of second conductivity type connected to a first reference potential; and an output transistor provided in the vicinity of the first diffusion layer. A third diffusion layer of the second conductivity type, which is separated from the first diffusion layer by the element isolation insulating film and connected to the first reference potential or the second reference potential, is used as an emitter;
A protection transistor having a first diffusion layer as a collector and a base of a first conductivity type region as a base;
Of not covering at least a portion of the insulating film formed on the boundary of the semiconductor substrate surface of the diffusion layer, and was set to a control electrode which is an area the same potential of the first conductivity type.
With such a configuration, a gate controlled diode is formed by the first diffusion layer, the region of the first conductivity type, and the control electrode formed via the thin insulating layer. And
When the current applied to the first diffusion layer reaches a voltage equal to or higher than a predetermined value, a current path is formed between the first diffusion layer below the control electrode and the region of the first conductivity type.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing a pattern layout corresponding to the circuit shown in FIG. Then, FIG.
It is sectional drawing which shows A 'cross section. As shown in FIG. 1, the semiconductor device according to the present embodiment has an input / output terminal The output transistor 12 that controls the potential of the signal
Is provided through. In addition, a protection transistor 14 forming a discharge path and a trigger diode 15 are connected to the input / output terminal 11 via a parasitic resistor 102 in order to protect the internal circuit and the output transistor 12 from surge current.

As shown in FIG. 3, the output transistor 12 includes n-type diffusion layers (first and second diffusion layers) 17a and 17b and a gate electrode 18 formed on the surface of a p-type semiconductor substrate 16. With n-type LDD structure
Is configured as Note that a gate oxide film 28 is interposed between the p-type semiconductor substrate 16 and the gate electrode 18. The n-type diffusion layers 17a and 17b are provided with low-concentration regions 17a 'and 17b', respectively. The n-type diffusion layer 17a, which is the source region of the output transistor 12, is connected to a common wiring (not shown) by a metal wiring 19a made of aluminum. The n-type diffusion layer 17b, which is a drain region, is connected to the input / output terminal 11 (FIGS. 1 and 2) by a metal wiring 20 also made of aluminum. Here, the source of the output transistor 12 is connected to the ground, but the present invention is not limited to this, and the source may be connected to the reference potential of the high potential power supply line.

As shown in FIG. 2, the gate electrode 18 of the output transistor 12 is connected to the wiring 1 to the gate drive circuit.
00, the potential of the input / output terminal 11 is controlled by switching between conduction and non-conduction of the output transistor 12 according to a drive signal from the gate drive circuit. The gate electrode 18 and the metal wirings 19a, 19b, 20 are insulated by the sidewall 26 and the interlayer insulating film 27. As shown in FIG. 3, the protection transistor 14 is an npn bipolar transistor having a semiconductor substrate 16 as a base, an n-type diffusion layer 17b as a collector, and an n-type diffusion layer (third diffusion layer) 17c as an emitter. Be composed. N-type diffusion layer 17b and n-type diffusion layer 17c are insulated by field oxide film (element isolation insulating film) 22. Further, the collector n-type diffusion layer 17b is
At 0, it is connected to the input / output terminal 11, and the emitter n-type diffusion layer 17c is connected to a common wiring (not shown) by a metal wiring 19b made of aluminum.

The trigger diode 15 comprises a diode composed of a semiconductor substrate 16 and an n-type diffusion layer 17b, and a control electrode 21 formed on a thin insulating film 22a following the field oxide film 22. . That is, it is a gate control type MOS diode. The control electrode 21 is formed so as to cover the region of the n-type diffusion layer 17b via the thin insulating film 22a. Note that, as shown in FIG.
P ⁺ diffusion layer 22 is formed so as to surround 2 and protection transistor 14, and is connected to metal wiring 19b. As a result, the base of the protection transistor 14, the control electrode 21 of the trigger diode 15, and the emitter of the protection transistor 14 are connected.

Since the semiconductor device of this embodiment is configured as described above, when an overvoltage is applied to the input / output terminal 11, first, the trigger diode 15
A potential difference is generated between the n-type diffusion layer 17b and the control electrode 21 via the thin insulating film 22a. This is the control electrode 21
Is the same potential as that of the semiconductor substrate 16.
For this reason, the depletion layer spreads from the junction between the n-type diffusion layer 17b and the semiconductor substrate 16. However, electrolysis concentrates on the semiconductor substrate 16 immediately below the control electrode 21, and breakdown occurs promptly from that portion, and a current path is formed at the junction surface of the trigger diode 15. As a result, the input / output terminal 1
When an overvoltage is applied to the trigger diode 1, the trigger diode 1
In part 5, a small amount of current flows through the semiconductor substrate 16. Next, since a current flows through the semiconductor substrate 16, a current flows through the base of the protection bipolar transistor 14. That is, between the collector and the emitter of the protection bipolar transistor 14 is turned on. Then, the surge (overvoltage) applied to the input / output terminal 11 flows to the metal wiring 19b through the space between the collector and the emitter of the protection bipolar transistor 14.

As described above, according to this embodiment, a trigger diode is newly provided, so that when a surge current is applied to the input / output terminal, the protection bipolar transistor operates reliably. The surge current always flows through the protection transistor. As a result, according to this embodiment, even if a surge current is applied to the input / output terminal, it does not flow to the output transistor or the internal circuit. In the above embodiment, as shown in FIG. 3, the control electrode 21 and the n-type diffusion layer 17c are connected by the metal wiring 19b, but the present invention is not limited to this. The control electrode 21 may be formed on the field oxide film 22 from the thin insulating film 22a to the contact of the n-type diffusion layer 17c. Further, in the above-described embodiment, the metal wirings 19a, 19b, 20 are made of aluminum. However, the present invention is not limited to this, and another metal such as copper or tungsten may be used.

[0016]

As described in the foregoing, in the present invention, a metal terminal disposed on the semi <br/> conductor substrate, connected to be formed in the region of the first conductivity type and the metal terminals of the semiconductor substrate An output transistor having the second diffusion layer of the second conductivity type as a drain and the source of the second diffusion layer of the second conductivity type connected to a first reference potential; The third diffusion layer of the second conductivity type, which is separated from the first diffusion layer by the provided element isolation insulating film and is connected to the first reference potential or the second reference potential, is used as an emitter. A protection transistor based on a region of the first conductivity type, using the diffusion layer as a collector, and at least a part of an insulating film formed on a boundary between the region of the first conductivity type and the first diffusion layer on the surface of the semiconductor substrate the not covered, and is an area the same potential of the first conductivity type And to a control electrode.

With such a configuration, a gate controlled diode is formed by the first diffusion layer, the region of the first conductivity type, and the control electrode formed via the thin insulating layer. When the current applied to the first diffusion layer reaches a voltage equal to or higher than a predetermined value, first, a current path is formed between the first diffusion layer below the control electrode and the region of the first conductivity type. Then, the current starts flowing to the substrate side, and the current flows to the base of the protection transistor. Then, a current flows between the emitter and the collector of the protection transistor. That is, when the current applied to the first diffusion layer reaches a voltage equal to or higher than a predetermined value, this current flows to the emitter side of the protection transistor and does not flow to the output transistor. As is apparent from the above description, according to the present invention, the output transistor and the internal circuit can be protected from the electrostatic breakdown phenomenon by the circuit configuration with the minimum pattern area.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a pattern layout corresponding to the circuit shown in FIG.

FIG. 3 is a sectional view showing an AA ′ section in FIG. 2;

FIG. 4 is a circuit diagram showing a circuit configuration of a conventional semiconductor device including a protection transistor.

FIG. 5 is a plan view showing a pattern layout corresponding to the circuit shown in FIG. 4;

FIG. 6 is a cross-sectional view showing a BB ′ cross section of FIG. 5;

[Explanation of symbols]

11 input / output terminal, 12 output transistor, 13 resistor, 14 protection transistor, 15 trigger diode, 16 p-type semiconductor substrate, 17a, 17b, 17c
n-type diffusion layer, 18 ... gate electrode, 19a, 19b, 20
... metal wiring, 21 ... control electrode, 22 ... field oxide film, 26 ... side wall, 27 ... interlayer insulating film, 28 ...
Gate oxide film, 100, 101 ... wiring, 102, 103
... parasitic resistance.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 21/8234-21/8238 H01L 21/8249 H01L 27/04 H01L 27/06 H01L 27 / 08-27/092 H01L 29/78

Claims (5)

(57) [Claims] A metal terminal provided on a semiconductor substrate; and a metal terminal formed in a first conductivity type region of the semiconductor substrate.
A first diffusion layer of the second conductivity type connected to the metal terminal;
And a second conductivity type connected to a first reference potential.
An output transistor having the second diffusion layer as a source and an element isolation insulating film provided near the first diffusion layer;
Is separated from the first diffusion layer by the first reference
Potential of the second conductivity type connected to the potential or the second reference potential.
3 as an emitter, and the first diffusion layer as a collector.
And a protective transformer based on the first conductivity type region.
A transistor, a region of the first conductivity type, and the semiconductor of the first diffusion layer.
Fewer insulating films formed on the boundary line on the substrate surface
And partially cover and have the same potential as the region of the first conductivity type.
The semiconductor device is characterized in that and a control electrode with. 2. The semiconductor device according to claim 1, wherein said control electrode and said third diffusion layer are formed of a metal.
A semiconductor device which is connected by a wire . 3. The semiconductor device according to claim 1, wherein a boundary between said first conductivity type region and said first diffusion layer is formed.
The insulating film formed at the gate of the output transistor
A semiconductor device formed of the same layer as an insulating film . 4. The semiconductor device according to claim 1 , wherein a gate of said output transistor is formed on said semiconductor substrate.
A semiconductor device, which is connected to an internal circuit formed . 5. The semiconductor device according to claim 1 , wherein the metal terminal is formed on an external circuit and the semiconductor substrate.
A semiconductor device, which is an input / output terminal for connecting to an internal circuit .