JP2585633B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, particularly an MIS (Metal Insu
The present invention relates to a protection device in a lator semiconductor type device.

[Conventional technology]

A conventionally known protection device is disclosed in Japanese Patent Application No. 58-1076.
MOSF with gate fixed at contact potential as described in No. 78
The method of connecting the source of ET to the ground potential and connecting the drain to the output terminal via a protective resistor has been used.

[Problems to be solved by the invention]

Hereinafter, the problems of the prior art will be described with reference to FIGS. 2, 3, and 4. FIG. FIG. 2 is a circuit diagram of the prior art. According to the conventional technique, the destruction of the gate oxide film of the MOSFET 23 due to static electricity applied to the terminal
The protection is intended to be prevented by a combination of a protection resistor and 22 MOSFETs. Here, the MOSFET 22 does not work in the case of normal circuit operation, but when a high voltage is applied, so-called surface breakdown occurs, so that a large current flows between the drain and the source. Accordingly, the static electricity applied to the terminal 24 passes through the 21 and is bypassed by the MOSFET 22. Therefore, it is possible to prevent the high voltage of the gate insulating film of the MOSFET 23 from being applied. Here, the protection resistor 21 functions to reduce the current flowing through the MOSFET 22.

FIG. 3 shows a cross-sectional structure diagram of the MOSFET 22. 35 n-type substrates are provided on the surface of 36 n-type substrates, and 31 and 32 n-type high-concentration impurity regions are provided on the surface. On the upper part of the base, there are an electrode 37 and an insulating film 38, forming a MOSFET with 31, 37 and 32 as drain, gate and source, respectively. On the other hand, reference numeral 33 denotes a p-type high-concentration impurity layer. In order to fix the potential of the p-well of 35 to the ground potential, the n-type high-concentration impurity layer of 34 comprises n of 36.
It is provided to fix the potential of the mold base.

FIG. 4 shows a voltage-current characteristic of the device of FIG. 3 with respect to the ground potential of the drain terminal 39. The point indicated by A is that when a voltage is applied to the terminal 39, the junction consisting of 31 and 35 breaks down. The junction consisting of 31 and 35 is covered with a gate electrode structure consisting of 37 and 38,
As a result, the breakdown of the junction causes a so-called surface breakdown which occurs at a lower voltage than a normal junction. Once the surface breakdown has occurred, as shown in B, 31, 35, 32
The npn structure causes a bipolar operation, and the drain voltage decreases. As the current further increases, the voltage increases due to the influence of the parasitic resistance of the source and drain, as shown at point C.

Further, the impurity layers 31, 35 and 36 in FIG.
When a voltage having the terminal 41 as a ground potential is applied to the terminal 39, a parasitic bipolar operation occurs between the power supply terminal 41 and the terminal 39, and the voltage V between the terminal 39 and the ground terminal shown in FIG.
It shows characteristics similar to -I characteristics. Normally, a large capacitance of about 1000pF or more is connected between the power supply terminal and the ground terminal.
This vertical bipolar operating current plays an important role in bypassing static electricity because the transistor is transiently conductive.

As described above, the conventional method can be said to be an excellent method by utilizing surface breakdown, but in recent years MOSFET
However, the following problem arises with respect to the reduction in the thickness of the gate oxide film.

First, in FIG. 1, when a large current due to static electricity applied to the MOSFET terminal 24 shown in FIG. 2 flows, the voltage at the terminal 25 increases due to the internal resistance as shown at the point C, and the MOSF 23
This may destroy the gate insulating film of the ET. In order to prevent this, there is a method of increasing the resistance 21. The problem of increase arises.

The second problem is that the MOSFET itself of the protection element 22 uses the thin gate insulating film 38 shown in FIG.
That is, the gate insulating film of the protection element is broken by static electricity.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a protection device that protects a gate insulating film of a MOSFET against high-voltage static electricity and does not destroy a gate oxide film of a protection element itself.

[Means for solving the problem]

The above object is achieved by taking the following measures.

First, an electrode for wiring is used as a gate electrode in the first stage of the protection device, and an interlayer film is used as a gate insulating film.

Second, a low antibody is made using the same n-type high concentration impurity layer as the drain electrode of the first protection device.

Third, a surface breakdown type MOSFET using the n-type high concentration impurity layer is manufactured.

Fourth, a resistor made of a conductive layer is inserted between the first protection device and the input terminal.

Fifth, the resistance of the high-concentration impurity layer provided outside the well is reduced by the conductive layer.

[Action]

 The above means has the following effects.

Since the MOSFET using the first interlayer film has a thick gate insulating film of the protection element, it is possible to prevent the gate insulating film of the protection element itself from being destroyed. However, since the first element is not of the surface breakdown type, the voltage of the drain terminal cannot be sufficiently reduced. Therefore, by forming a resistor using the second impurity layer resistance and further forming a third surface breakdown type MOSFET, the voltage at the drain of the MOSFET can be sufficiently reduced. At this time, the resistance of the second impurity layer has the effect of reducing the current flowing through the third surface breakdown type MOSFET and reducing the voltage applied to the gate oxide film of the third MOSFET. Further, by making this resistor common to the drains of the first and third MOSFETs, a sufficiently large resistor can be obtained with a small area.

The resistance provided by the fourth conductive layer has an effect of preventing a large current from flowing through the first MOSFET and thermally damaging the drain junction.

In addition, by lowering the resistance of the high-concentration impurity layer provided outside the fifth well, it is possible to prevent an increase in the potential of the drain terminal due to the current flowing to the power supply terminal and the resistance of the high-concentration impurity layer.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of a first embodiment of the present invention. In this embodiment, a case in which a p-well is formed on an n-type substrate will be described to simplify the description. In the figure
109 is a p-well region. 107 and 108 are n-type high-concentration impurity layers, and a part of 107 and 108 are adjacent to each other. The n-type high-concentration impurity layer 107 is connected to the conductive layer 101 of the input terminal through the contact hole 114.
Thick gate oxide parasitic MOS covering area adjacent to and 108
Forming FET. Further, the n-type high-concentration impurity region 108 is connected to the conductive layer 103 fixed to the ground potential through the contact hole 113. On the other hand, in another region of the conductive layer 107, a gate electrode of a MOSFET which performs a surface breakdown operation of a thin gate oxide film 110 is provided, and is fixed to the ground potential through a contact hole 117. A contact hole 123 is provided near the gate electrode 110 and is connected to the conductive layer 102. p well 109 is p
Type high concentration impurity layer 106 and contact holes 121, 118, 1
It is connected to the conductive layer 103 through 16, 112 and fixed at the ground potential. Further, the n-type substrate has contact holes 122, 11
Through 9,115,111, it is connected to the conductive layer 104 fixed at the power supply potential.

In the case of this embodiment, in a normal operation, an input signal is transmitted from the input terminal to the conductive layer 102 through the conductive layer 101, through the high-concentration impurity layer 107.

FIG. 5 shows a sectional view of the first embodiment.
Each code corresponds to the code in FIG. Conductive layer
When static electricity is applied to 101, npn consisting of 107, 109, 108
The structure and the npn structure composed of 107, 109, and 124 cause a bipolar operation, and currents i _A and i _B flow.

The operation of the first embodiment will be described with reference to FIG. 6 (A) and 6 (B) show the time change of the potentials of the nodes A and B and the time change of the bipolar operation currents i _A and i _B shown in FIG. Very large current i _A flows because npn structure static electricity having a constant charge amount in the node A is made of the applied 107,109,108 performs the bipolar operation. At this time, the bipolar element has a parasitic resistance,
to produce a potential difference between the i _A, the node A is considerably higher potential. Since the gate insulating film in this portion is an interlayer insulating film of a conductive layer, the withstand voltage is sufficiently ensured, and this portion is not broken. However, as shown in FIG. 6 (A), the voltage at point A exceeds the withstand voltage of the gate oxide film, and is therefore insufficient as a device for protecting the gate oxide film. Therefore, MOSFE with a gate electrode of 110
T is provided. At this time, since the current flowing through the MOSFET is limited by the resistance of the impurity layer 107, the potential of the node B is kept low, and the potential of the point B is also kept low. In this embodiment, the resistance of the impurity layer 107 plays an important role as described above. This resistor may be a resistor made of a conductive layer, but requires a large area. However, as shown in FIG. 5, by sharing the n-type high-concentration impurity layer serving as a resistor with the drains of the two MOSFETs, the required area can be reduced. On the other hand, generally, a large parasitic capacitance is provided between the power supply potential terminal and the ground potential terminal, and the potential of the base is transiently grounded in an alternating current.
Accordingly, a current i _C flows into the conductive layer 105 due to the npn structure composed of the bases 107 and 109. This i _C is i _A
And the function of reducing i _B , the structure that facilitates the flow of i _C has the function of strengthening the protection element. In the present embodiment has an effect capable of strongly protective element by easily flow i _C to reduce the resistance of the impurity layer 105 with a conductive layer 104.

FIG. 7 shows a layout diagram of the second embodiment of the present invention. In this embodiment, the input terminal 125 is connected to the conductive layer 101 through a resistor 124 made of a conductive layer. In the case of the present embodiment, since the current flowing through the protection element is reduced by the resistor 124, there is an effect that the node terminal voltage is reduced more than in the first embodiment.

FIG. 8 shows a layout diagram of the third embodiment of the present invention, and FIG. 9 shows an equivalent circuit. In this embodiment, parasitic MOSFETs are provided at the boundary between the impurity layers 107 and 108 and at the boundary between the impurity layers 107 and 127, respectively. The former gate is the input conductive layer 101, and the latter gate is the power supply. The conductive layer 104 for applying a potential. Further, impurity layer 108 is connected to conductive layer 103 which applies a ground potential, and impurity layer 127 is connected to conductive layer 104 which applies a power supply potential. On the other hand, the impurity layer 107
In other parts, the MOSFET with the conductive layer 110 as the gate electrode
Is formed, and its source is fixed to the ground potential. The conductive layer 110 itself serves as a resistor, and is fixed at the ground potential through the resistor. This MOSFET
Is formed between the region and the region of the parasitic MOSFET, thereby forming a resistor. The potential of the drain of the MOSFET is taken out by the conductive layer 124.

In the equivalent circuit of FIG. 9, when static electricity is applied from the input terminal 200, current flows to the ground terminal and the power supply terminal through the parasitic MOSs 201 and 202. Static electricity is also an impurity layer resistance
It will flow through the MOSFET 205 through the 204.

In this embodiment, since the parasitic MOSFET is connected not only to the ground terminal but also to the power supply terminal, the current flowing through the parasitic MOSFET connected to the ground terminal is reduced, and the potential rise of the node 208 is suppressed. Can be. Also, resistance 2
Since 04 is formed by using the constriction of the impurity layer 107, a necessary resistance value can be realized with a small area. The resistance value 209 is 2
Although it is inserted to prevent the gate insulating film of the MOSFET 05 from being destroyed, the gate electrode can be fixed to the ground potential without affecting the normal circuit operation. No.
FIG. 10 shows a cross-sectional view of the parasitic MOS portion 10 of this example. When static electricity is applied to the node 200, np of the impurity layers 107, 109, 130
The n-type structure bypasses the ground terminal, and the npn structure of the impurity layers 107, 109, and 108 bypasses the power supply terminal.

FIG. 11 shows a fourth embodiment of the present invention. In this embodiment, the resistors 211 and 210 are connected in series to the source side of the parasitic MOS 201 and the drain side of the parasitic MOS, respectively. Each of these resistors can be provided by taking the resistance of the impurity layer. In the case of the present embodiment, the presence of the resistors 210 and 211 reduces the current flowing through the parasitic MOSFETs 201 and 202,
This has the effect of preventing the parasitic MOSFETs 201 and 202 from being thermally destroyed.

FIG. 12 shows a fifth embodiment of the present invention. In this embodiment, the potential of the gate electrode of the parasitic MOSFET 202 is fixed to the input terminal 200 or the ground potential. However, the parasitic MOSF
Since the drain electrode of the ET 202 is connected to the power supply terminal and the static electricity can be bypassed to the power supply terminal side, the effect similar to that of the third embodiment is obtained and the structure is strong against electrostatic breakdown.

FIG. 13 is a circuit diagram of a sixth embodiment of the present invention, and FIG. 14 is a circuit diagram of a seventh embodiment of the present invention. In either method, the potentials of the gate electrodes of the parasitic MOSs 201 and 202 are different.
Since the source of the OS 201 is connected to the ground terminal and the drain of the parasitic MOS 202 is connected to the power supply terminal, the structure has the same effect as that of the third embodiment and is resistant to electrostatic breakdown.

〔The invention's effect〕

As a method against electrostatic breakdown of a protection element, a method of applying a charge charged to a capacity of 1000 pF through a resistance of 1.5 KΩ to the protection element is widely used.

According to the present invention, it is possible to provide a protection element having almost the same area as the conventional method and having resistance to about twice the electric charge.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional method, FIG.
4 is a view showing the operation of the conventional method, FIG. 5 is a sectional view of the first embodiment of the present invention, FIG. 6 is a view showing the operation of the present invention, and FIG. FIG. 8 is a layout diagram of the third embodiment of the present invention, FIG. 9 is a circuit diagram of the third embodiment of the present invention, and FIG. 10 is a third embodiment of the present invention.
FIG. 11 is a circuit diagram of the fourth embodiment of the present invention, FIG. 12 is a circuit diagram of the embodiment of FIG. 5 of the present invention, and FIG. The circuit diagram of the sixth embodiment,
FIG. 14 is a circuit diagram of a seventh embodiment of the present invention. 101: conductive layer, 102: conductive layer, 104: conductive layer, 107, 1
08 ... n-type high concentration impurity layer, 109 ... p-type well, 110 ...
Gate electrode.

Continuing on the front page (72) Inventor Toshio Sasaki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor: Osamu Takahashi 1450, Josui-Honcho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor: Masaru Yamamoto 1450, Musashi-Honcho, Kodaira-shi, Tokyo, Musashi Factory, Hitachi, Ltd. ) References JP-A-48-66976 (JP, A)

Claims (5)

(57) [Claims] A semiconductor substrate; a well region of one conductivity type provided in a surface region of the semiconductor substrate; and a conductive region for wiring provided on the semiconductor substrate via a first insulating film. A semiconductor device having a layer, further comprising a first impurity region, a second impurity region, and a third impurity region having a conductivity type different from the conductivity type on a surface of the well region. The first impurity region is electrically connected to a ground terminal; the second impurity region is electrically connected to an input terminal; the third impurity region is electrically connected to a ground terminal; An impurity region, the second impurity region, and the conductive layer provided with the first insulating film interposed therebetween;
A MOSFET is formed, and another MOSFET is formed by the second semiconductor region, the third semiconductor region, and a gate electrode provided on the semiconductor substrate via a second insulating film. The thickness is formed to be smaller than the thickness of the first insulating film, the conductive layer is electrically connected to an input terminal, a ground terminal, or a power supply terminal, and the gate electrode is electrically connected to a ground terminal. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said second impurity region is formed such that one of said second impurity regions is adjacent to said first semiconductor region and the other is adjacent to said third semiconductor region. 2. The semiconductor device according to claim 1. 3. A fourth impurity region of a first conductivity type is formed on the surface of the semiconductor substrate around the well region.
The low resistance conductive layer connected to a power terminal is formed on the impurity region, and the low resistance conductive layer and the fourth semiconductor region are connected. 13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said gate electrode is connected to a ground terminal through a low antibody made of the same conductive layer as said gate electrode. 5. The semiconductor device according to claim 1, further comprising a resistance provided by a conductive layer between said second impurity region and said input terminal.