JP2555890B2 - Input protection device for semiconductor integrated circuit - Google Patents

Description

The present invention relates to an input protection device for a semiconductor integrated circuit, and more particularly, to an input protection device for a semiconductor integrated circuit.
The present invention relates to a semiconductor integrated circuit input protection device using a MOS device.

[Conventional technology]

Conventionally, this type of input protection device is intended to clamp an excessive input voltage by utilizing the breakdown phenomenon of an nMOS transistor.Basically, the source region and the gate electrode are grounded, and the input pad and the drain pad are connected to the drain region. It is configured to connect the input gate of the internal circuit, and further as a protection resistor between the input pad and drain region, or the gate electrode and GN.
There is a structure in which a resistor is inserted between the D wiring.

FIG. 4 shows such an input protection device. The gate electrode 5 and the source region (N ⁺ diffusion layer 2) of the nMOS transistor are connected to the GND wiring 9 made of an aluminum film, and the drain region (N ⁺ diffusion layer 4) is an aluminum film 6 which is an input pad (not shown) and the inside. It is connected to the input gate (not shown) of the circuit.

[Problems to be Solved by the Invention]

In the above-mentioned conventional input protection device, when a positive voltage exceeding the breakdown voltage is applied, the nMOS transistor causes avalanche breakdown and causes a current to flow to the GND terminal via the NPN parasitic bipolar transistor. The electric field is concentrated on the PN junction of the and the electrons accelerated at the boundary with the channel are injected into the gate oxide film, which causes a minute leakage current.

[Means for solving the problem]

The present invention is an nM formed in a P-well or P-type substrate.
The source region and the gate electrode of the nMOS transistor having an OS transistor are connected to the GND wiring directly or via a resistor, respectively, and the drain region is connected to the input pad and the input gate of the internal circuit. In the input protection device, a conductive electrode that is connected to the gate electrode of the nMOS transistor and covers the gate electrode and the capacitor electrode through an interlayer film and a capacitance electrode formed of the same layer as the gate electrode, and connects to the input pad. The layers are provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a pattern layout diagram showing an input protection device related to the present invention, and FIG. 1 (b) is a sectional view of a semiconductor chip taken along the line AA line in FIG. 1 (a). is there.

The N ⁺ diffusion layer 2 in the source region of the nMOS transistor formed in the P well 1 is connected to the GND wiring 9 through the contact hole 301, and the gate electrode 5 is connected to the GND wiring 9 through the polysilicon resistor 8 and the drain region. N ⁺ diffusion layer 4
Are connected to the aluminum film 6a through contact holes 3-2. The aluminum film 6a is connected to the input pad and the input gate and covers the upper part of the gate electrode 5 of the nMOS transistor. A coupling capacitance C is formed between the gate electrode and the gate electrode.

FIG. 2 is an equivalent circuit diagram of the input protection device related to the present invention.

The nMOS transistor Mn is off during normal operation, but when a positive voltage higher than the breakdown voltage is applied to the input, the potential of the gate is affected by the coupling capacitance C between the aluminum film 6a and the gate polysilicon (5). And the nMOS transistor Mn is turned on for a time determined by the product of the coupling capacitance C and the resistance R between the gate GND. By forming the channel, the electric field concentration at the drain PN junction is relaxed and the electrostatic breakdown voltage is improved.

FIG. 3 is a pattern layout diagram showing the first embodiment of the present invention.

Referring to FIGS. 1 and 2, the polysilicon layer 9 having a certain area is connected to the gate electrode 5 of the nMOS transistor, and the upper portion thereof is also covered with the aluminum film 6b similarly to the gate electrode 5. The input protection device described above is different.

In this embodiment, the coupling capacitance between the input terminal and the gate electrode can be further increased, and the time for turning on the nMOS transistor by increasing the gate potential when a static voltage is applied can be increased.

〔The invention's effect〕

As described above, according to the present invention, the positive electrode is applied to the input terminal by covering the upper part of the gate electrode inserted between the input pad and the input gate of the internal circuit with the conductive layer connected to the input pad. Sometimes raising the potential of the gate electrode
This has the effect of making the nMOS transistor conductive and relaxing the electric field concentration at the drain PN junction and improving the electrostatic breakdown voltage.

[Brief description of drawings]

FIG. 1 (a) is a pattern layout diagram showing an input protection device relating to the present invention, and FIG. 1 (b) is an A in FIG. 1 (a).
-A sectional view of the semiconductor chip taken along the line A-part, FIG. 2 is an equivalent circuit diagram of the input protection device shown in FIG. 1, FIG. 3 is a pattern layout diagram showing the first embodiment, and FIG. FIG. 4A is a pattern layout diagram showing a conventional example, and FIG. 4B is a cross-sectional view of a semiconductor chip taken along a portion corresponding to the line AA of FIG. 4A. 1 ... P well, 2 ... N ⁺ diffusion layer (source region), 3,3
-1,3-2 ... Contact hole, 4 ... N ⁺ diffusion layer (drain region), 5 ... gate electrode, 6,6a, 6b ... aluminum film, 7 ... P ⁺ diffusion layer (well contact) , 8 ...
… Polysilicon resistor, 9 …… Capacitor polysilicon film, 10
... GND wiring, 11 ... N-type semiconductor substrate, 12 ... input pad, 13 ... input gate.

Claims (1)

(57) [Claims] 1. An nM formed in a P-well or P-type substrate
The source region and the gate electrode of the nMOS transistor having an OS transistor are connected to the GND wiring directly or via a resistor, respectively, and the drain region is connected to the input pad and the input gate of the internal circuit of the semiconductor integrated circuit. In the input protection device, a conductive electrode which is connected to the gate electrode of the nMOS transistor and which covers the gate electrode and the capacitor electrode through an interlayer film and a capacitance electrode formed of the same layer as the gate electrode and connects to the input pad. An input protection device for a semiconductor integrated circuit, wherein a layer is provided.