JPS63291470A - Protective circuit for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a protective circuit which has a large effect by using the small area of a semiconductor substrate by forming a ringlike diffused layer around a diffused layer formed under a pad or a diffused layer connected to the pad, and composing the protective circuit of a protective transistor or the like by both the diffused layers. CONSTITUTION:Since the gate electrode 12 of a MOS transistor 19 is a ground potential and a gate-source voltage is 0V, the transistor 19 is normally OFF. When a positive surge voltage is applied to a pad 16, a current flows from a drain 6 to a source 8 by a source-drain punch-through characteristic, a breakdown occurs between a diffused layer 6 and a substrate 2, and a current flows from the pad 16 to the substrate 2. When a negative surge voltage is applied to the pad 16, the transistor 19 of this protective circuit becomes ON, a current flows from the source 8 to the drain 6, or a current flows from the substrate 2 to the pad 16 by the forward direction of a diode. Since a N-channel MOS transistor which becomes a protective device is composed in a ring shape around the pad 16 in this manner, the protective circuit having a large effect can be obtained by a small chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention provides a method for detecting surge voltages (abnormal voltages) applied to input pins during operation or handling of semiconductor integrated circuit devices including field effect semiconductor devices. The present invention relates to a protection circuit that prevents a type semiconductor device from being destroyed.

(Prior art) A semiconductor integrated circuit device including a MoS transistor, which is a field-effect semiconductor device, has an insulated gate electrode.
It is an integrated OS transistor and is particularly vulnerable to electrostatic damage.

A common method for preventing MOS transistors from being damaged by electrostatic discharge is to insert a protection circuit between an input terminal and an input circuit, and to absorb overvoltage with the protection circuit. Examples of the protection circuit include a resistor, a PN diode, a combination of a resistor and a PN diode, and a combination of a resistor and a MOS transistor.

However, the purpose is to make it half-full in order to construct these protection circuits.

(Structure) In the present invention, in order to constitute a protection circuit, a ring-shaped impurity diffusion region is formed on the surface of a semiconductor substrate, and an impurity diffusion region is also formed within the ring, and the protection circuit is constituted by these diffusion regions.

Examples will be specifically described below.

1 and 2 show one embodiment, and FIG. 2 is a sectional view taken along line A--A in FIG. 1.

Reference numeral 2 denotes a P-type silicon substrate, and field regions separated by field oxide films 4 are formed on the surface of the silicon substrate 2. An N-type diffusion layer 6 is formed on the surface of the silicon substrate 2 in the field region, and the diffusion layer 6
A ring-shaped N-type diffusion layer 8 is formed around the .

A gate oxide film IO is formed on the silicon substrate 2, and a polysilicon layer 12 is formed in a ring shape on the gate oxide film 10 in a region between the diffusion layers 6 and 8.

An interlayer insulating film 14 is formed to cover the polysilicon layer 12, and the interlayer insulating film 14 is formed in the portions of the diffusion layer 6 and the diffusion layer 8.
A contact hole is formed in the diffusion layer 6, and a bonding pad 16 made of a metal layer is formed on the diffusion layer 6.
The metal layer 18 is connected to the diffusion layer 8 through the contact hole 15 on the diffusion layer 8 . 20 is a passivation film.

Polysilicon layer 12 is also connected to metal layer 18 via contact hole 17 . Metal layer 18 is connected to ground potential.

In this embodiment, an N-channel type MO8 transistor is constructed in which the diffusion layer 6 is used as a drain, the diffusion layer 8 is used as a source, and the polysilicon layer 12 is used as a gate electrode. The bonding pad 16 and the diffusion layer 6 which is the drain have the same electrical potential, and the gate electrode 12 and the diffusion layer 8 which is the source
Both are at ground potential.

The equivalent circuit of this embodiment is shown in FIG.
The transistor 19 is formed in a ring shape. 2
1 is an input circuit.

Next, the operation of this embodiment will be explained.

This MOS transistor 19 is normally in an off state because its gate electrode 12 is at ground potential and its gate-source voltage is Ov.

If a positive surge voltage is applied to pad 16, the source
Depending on the characteristics of the drain junction, a current flows from the drain 6 to the source 8, or breakdown occurs between the diffusion layer 6 and the substrate 2, and a current flows from the pad 16 to the substrate 2.

When a negative surge voltage is applied to the pad 16, the MOS transistor 19 of this protection circuit is turned on, and current flows from the source 8 to the drain 6.

Or, due to the forward characteristics of the diode, from the substrate 2 to the pad 1
Current flows to 6.

In this embodiment, since the N-channel MOS transistor serving as a protection device is arranged in a ring shape around the pad 16, a highly effective protection circuit can be obtained with a small chip area.

4 and 5 show a second embodiment, and FIG. 5 is a sectional view taken along line B--B in FIG. 4.

An N-type diffusion layer 6 is formed on the surface of a P-type silicon substrate 2, and a ring-shaped N-type diffusion layer 8 is formed around the diffusion layer 6 via a field oxide film 4a. Silicon substrate 2
An interlayer insulating film 14 is formed on the surface of the gate oxide film 10 via a gate oxide film 10, and contact holes are formed in the first interlayer insulating film 14 on the diffusion layer 6 and the diffusion layer 8.

A bonding pad 16a is formed on the diffusion layer 6,
It is connected to the diffusion layer 6. The bonding pad 16a extends over the field oxide film 4a, and its outer side extends to the inside upper part of the diffusion layer 8.

On the other hand, the diffusion layer 8 is connected to a metal wiring 18 connected to the ground potential through a contact hole on the diffusion MIB. 20 is a passivation film.

In this embodiment, an N-channel MOS transistor 19a (FIG. 6) has the diffusion layer 6 as the drain, the diffusion layer 8 as the source, and the bonding pad 16a itself as the gate electrode.
is configured as a protection circuit.

The equivalent circuit of this protection circuit is shown in FIG.

The gate voltage for turning on the Mo8)-transistor 19a can be adjusted depending on the gate width, and is, for example, 12V. In other words, under normal conditions, this M
The OS transistor 19a is in an off state.

Next, the operation of this embodiment will be explained.

When a positive surge voltage is applied to pad 16a, this M
The OS transistor 19a is turned on, and the drain 6
Current flows from the diffusion layer 6 to the source 8, or from the diffusion layer 6 to the substrate 2 due to breakdown.

When a negative surge voltage is applied to the pad 16a, a current flows from the substrate 2 or from the source 8 to the drain 6 due to diode characteristics.

In this embodiment, the MoS transistor 1 constituting the protection circuit is
By configuring pad 9a under pad 16a, the area of silicon substrate 2 can be used effectively.

Moreover, it becomes possible to construct a large-sized protection device with great effect.

FIGS. 7 and 8 show a third embodiment.

FIG. 8 is a sectional view taken along line CC in FIG. 7.

An N-type diffusion layer 6 and a ring-shaped N-type diffusion layer 8 surrounding the diffusion layer 6 are formed on the surface of the P-type silicon substrate 2 via a field oxide film 4a.

An interlayer insulating film 14 is formed on the silicon substrate 2 , a metal wiring 16 b connected to the input pad 16 is formed on the interlayer insulating film 14 , and the metal wiring 16 b and the diffusion layer 6 are connected through a contact hole in the interlayer insulating film 14 . There is. Further, a metal wiring 18 connected to the ground potential is formed on the first interlayer insulating film 14 , and an N-type diffusion layer 8 extends to the lower side of the metal wiring 18 . Diffusion layer 8 and metal wiring 18 are connected.

20 is a passivation film.

In the protection circuit of this embodiment, the distance between the N-type diffusion layer 6 in the surge input section and the surrounding ring-shaped N-type diffusion M8 needs to be narrow because the purpose is not to penetrate between the N-type diffusion layers. There isn't.

Next, the operation of this embodiment will be explained.

When a negative surge voltage is applied to the input pad 16, due to the diode characteristics, it flows from the substrate 2 through the diffusion layer 6, or from the N-type diffusion layer 8 at ground potential through the substrate 2 and the diffusion layer 6.
Current flows from the input pad 16 to the input pad 16.

When a positive surge voltage is applied, current flows from the pad 16 to the substrate 2 via the diffusion layer 6 due to breakdown.

In this embodiment, when the charge escapes through the substrate 2.

Surrounding V from the surge input part N-type diffusion layer 6 through the substrate 2
When a path to the cc-diffusion contact is created, in order to avoid a short circuit between Vcc and the substrate 2 due to contact breakdown, the N-type diffusion layer 8, which has the same potential as the substrate 2, is connected to the surge input section N in advance.
It is arranged around the mold diffusion layer 6.

(Effects) In the present invention, a ring-shaped diffusion layer is formed around the diffusion layer formed under the pad or the diffusion layer connected to the pad,
Since a protection circuit such as a protection transistor is formed by both diffusion layers, a highly effective protection circuit can be formed using a small area of the semiconductor substrate.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing the pattern of the main part of one embodiment;
The figure is a sectional view taken along line A-A in Figure 1 of the same embodiment, and
The figure shows an equivalent circuit of the same embodiment, FIG. 4 is a plan view showing the main part pattern of the second embodiment, FIG. 5 is a cross-sectional view of the same embodiment at the B-BM position in FIG. Fig. 6 is an equivalent circuit of the same embodiment, Fig. 7 is a plan view showing the pattern of the main part of the third embodiment, and Fig. 8 is a cross-sectional view of the same embodiment taken along line CC in Fig. 7. It is. 2...P-silicon substrate, 6.8...N-type diffusion layer, 12...polysilicon layer, 16.16a...pad, 18. ...Metal wiring at ground potential.

Claims (2)

[Claims] (1) A bonding pad is connected to a first impurity diffusion region formed on one surface of a semiconductor substrate on which a field effect semiconductor device is formed, and the first impurity diffusion region is connected to the first impurity diffusion region on the surface of the semiconductor substrate. A protection circuit for a semiconductor integrated circuit device, in which a second impurity diffusion region is formed surrounding the semiconductor integrated circuit device, and the second impurity diffusion region is connected to a ground potential. (2) A protection circuit for a semiconductor integrated circuit device according to claim 1, wherein a field effect semiconductor device is configured with the first impurity diffusion region as a drain and the second impurity diffusion region as a source.