JPH0240960A - Input protecting circuit device - Google Patents

Abstract

PURPOSE:To reduce an occupied area and prevent dielectric breakdown of a pad lower layer by constituting a MOS transistor and a diode constituting an input protecting circuit device, in a region almost directly under the pad. CONSTITUTION:On a P-type semiconductor substrate, a pad 2 is formed of a metal layer like aluminum. At a position directly under the pad 2, an N-type impurity layer 5 and an N-type impurity layer 6 are formed. The layer is adjacent to the impurity layer 5 and a part of the layer 6 is arranged directly under the pad 2. By the pad 2 and the impurity layers 5, 6, a MOS transistor(TR) 22 is formed in which the pad, the layer 5 and the layer 6 are used as a gate, a drain and a source, respectively. By the impurity layer 5 and the the substrate 1, a diode (D) 23 is constituted directly under the pad 2. The gate and the source of TR 22 and the cathode of D 23 are connected with the pad 22 and a first stage circuit, and the drain and the anode are grounded, thereby forming a circuit. Hence, an occupied area is reduced and dielectric breakdown of the pad lower layer can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input protection circuit device provided in a semiconductor integrated circuit device, and particularly to an input protection circuit device that reduces the layout area and takes measures against electrostatic damage directly under the pad electrode. Related to circuit devices.

[Conventional technology]

FIG. 3 shows an example of a human power protection circuit device in a conventional MO3 type semiconductor integrated circuit device. Here, an example is shown in which an input protection circuit device is constructed using an N-type impurity layer on a P-type semiconductor substrate.
) is an electrical circuit diagram.

In the figure, a pad 2 made of a metal layer is formed on a P-type semiconductor substrate 1, and an N-type impurity layer 5.6 is formed adjacent to the pad 2.
are formed side by side. Then, a part of the pad 2 is connected to the N-type impurity layer 5 via the contact 7, and this N-type impurity layer 5 is connected through the contact 7.
The type impurity layer 5 is electrically connected to the polycrystalline silicon wiring 4 via the contact 3, and is electrically connected to a first stage circuit (not shown).

A part of the pad 2 is disposed adjacent to the N-type impurity layer 5.6, and a MOS transistor 2 is formed with the pad 2 as the gate and the N-type impurity layer 5.6 as the source and drain.
2. Further, the N-type impurity layer 5 and the P-type semiconductor substrate 1 constitute a diode 23. Note that the N-type impurity layer 6 is electrically connected to a ground wiring 9 via a contact 8. Further, 10 is a cover opening.

In the second configuration, the protection circuit shown in FIG. 3(b) is configured, and when an abnormally high voltage such as static electricity is applied from the outside to the input terminal 21, a MOS transistor 22 formed with a high threshold voltage is activated. The diode 23 is turned on, and the breakdown current of the diode 23 causes the surge charge to escape to the substrate, lowering the voltage at the node between the input terminal 21 and the input first-stage transistor, and reducing the electric field strength applied between the gate of the input first-stage transistor and the semiconductor substrate. This prevents the gate oxide film of the input first stage transistor from being destroyed.

[Problem to be solved by the invention]

In the above-described conventional input protection circuit device, the PN junction area of the diode 23 and the MO3I- It is necessary to make the channel width of the transistor 22 sufficiently large. Usually, the width of the N-type impurity layer 5.6 is 10 to 20 μm, and the width of the MOS
The channel width of the transistor 22 is required to be approximately 50 to 100 μm.

Therefore, diode 23 and MO3I-transistor 2
The area of the N-type impurity layers 5 and 6 constituting 2 becomes larger,
This increases the area occupied by the input protection circuit device, which is undesirable in terms of high integration. In addition, for pad 2, input terminal 2
There is also the problem that the abnormal voltage applied to the semiconductor substrate 1 causes dielectric breakdown of the glabellar membrane below the pad 2, causing a short circuit between the pad 2 and the semiconductor substrate 1, which may cause a defect.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input protection circuit device that reduces the occupied area and prevents dielectric breakdown of the layer below the pad.

[Means to solve the problem]

In the input protection circuit device of the present invention, an impurity layer of the opposite conductivity type is formed directly under a pad as an input terminal formed on a semiconductor substrate of one conductivity type, and is electrically connected to the pad. A part of the other impurity layers of opposite conductivity type is extended, and these impurity layers of opposite conductivity type constitute the source and drain of the MO3I transistor, and the above-mentioned impurity layers of opposite conductivity type and the semiconductor substrate are connected. constitutes a diode.

[Effect]

In the above-described configuration, the MOS transistor and the diode are formed in the area directly under the pad, reducing the area occupied. Further, the N-type impurity layer provided directly under the pad is kept at the same potential as the pad to prevent dielectric breakdown of the insulating film below the pad.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and FIG.
1 is a plan layout diagram, and FIG. 3(b) is a circuit diagram.

In the same figure (a), a pad 2 is formed on a P-type semiconductor substrate 1 using a metal layer such as aluminum, and a part of this pad 2 is electrically connected to a polycrystalline silicon wiring 4 via a contact 3. electrically connected to the first stage circuit. Further, an N-type impurity layer 5 is formed directly below the pad 2, and an N-type impurity layer 6 is formed adjacent to the N-type impurity layer 5, with a portion of the N-type impurity layer 6 being located directly below the pad 2. ing. The N-type impurity layer 5 is electrically connected to the pad 2 through a contact 7, and the N-type impurity layer 6 is electrically connected to a ground wiring 9 through a contact 8. Note that 10 is a cover opening.

In this configuration, as shown in the same figure (b), pad 2 and N
The type impurity layer 5.6 makes an MO with the pad 2 as a gate), the N type impurity layer 5 as a drain, and the N type impurity layer 6 as a source.
3I-transistor 22 is configured. Further, directly under the pad 2, a diode 23 is formed of an N-type impurity layer 5 and a P-type semiconductor substrate l. And MOS) transistor 2
A circuit is constructed in which the gate and source of diode 23 and the cathode of diode 23 are connected to pad 2 and the first stage circuit, and the drain and anode are grounded.

Therefore, in this circuit, during normal operation, input terminal 2
The signal from the pad 2 passes through the contact 3 and the polycrystalline silicon wiring 3 to reach the first stage circuit. Input terminal 2
When an abnormally high voltage is applied to the pad 2, the high threshold MOS transistor 22, which normally does not operate, turns on, and a breakdown current flows through the diode 23, causing the pad 2 to
It operates to release the electric charge to the semiconductor substrate 1. This protects the first stage circuit from destruction due to high bias application. Further, since the N-type impurity layer 5 of the same potential exists directly under the pad 2, the strength of the electric field against the semiconductor substrate 1 is significantly reduced, and the glabellar membrane at the pad 2 due to the abnormally high voltage applied to the input terminal 21 is Dielectric breakdown is prevented.

It goes without saying that by disposing the N-type impurity layer 5 directly under the pad 2, the occupied area can be reduced.

FIG. 2 shows a second embodiment of the present invention, in which FIG. 2(a) is a plan layout diagram and FIG. 2(b) is a circuit diagram thereof. In addition,
Components equivalent to those in FIG. 1 are given the same reference numerals.

In this embodiment, polycrystalline silicon is formed on a region adjacent to an N-type impurity layer 5 formed directly under the pad 2 and an N-type impurity layer 6 adjacent thereto, a portion of which is located directly under the pad 2. A film 11 is formed, and a MOS transistor 22A having this polycrystalline silicon film 11 as a gate is configured. Note that this polycrystalline silicon film 11 is electrically connected to the ground wiring 9 via a contact 12.

In this configuration, the circuit configuration is shown in FIG. 2(b), and M
OS) The transistor 22A performs protection by utilizing the breakdown current between the source and drain. Therefore, in this embodiment as well, it is possible to protect the first stage circuit from an abnormally high voltage as in the embodiment shown in FIG.
By providing it directly under the pad 2, dielectric breakdown directly under the pad 2 can be prevented. Furthermore, since the N-type impurity layer 5 and the like are formed directly under the pad 2, the occupied area can be reduced.

Note that the present invention can be similarly applied to a semiconductor device using an N-type semiconductor substrate.

〔Effect of the invention〕

As explained above, the present invention reduces the area occupied by the input protection circuit device by configuring the MOS transistors and diodes constituting the input protection circuit device in the area directly under the pad, and enables highly integrated semiconductor devices. Realize the In addition, by keeping the N-type impurity layer provided directly under the pad at the same potential as the pad, the electric field between the pad and the semiconductor substrate is relaxed, preventing dielectric breakdown of the lower insulating film and preventing pad short circuits. There is an effect that can be done.

[Brief explanation of the drawing]

1 shows a first embodiment of the present invention, FIG. 1(a) is a plan layout diagram, FIG. 2(b) is an electric circuit diagram, and FIG. 3(a) is a plan layout diagram, FIG. 3(b) is an electric circuit diagram, and FIG. 3 is a conventional input protection circuit device.
b) is an electrical circuit diagram. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Pad, 3... Contact, 4... Polycrystalline silicon wiring, 5.6...
N-type impurity layer, 7.8... Contact, 9... Ground wiring, 10... Cover opening, 11... Polycrystalline silicon film, 12... Contact, 21... Input terminal, 2
2,22A...M Fig. 1 (a) (b) Fig. 3 (a) (b) Fig. 3 (a) (b)

Claims (1)

[Claims] 1. Directly below a pad as an input terminal formed on a semiconductor substrate of one conductivity type, one impurity layer of the opposite conductivity type is electrically connected to the pad, and another impurity layer of the opposite conductivity type is connected to the ground. By extending a part of the layer, these two impurity layers of opposite conductivity type constitute the source and drain of a MOS transistor, and the one impurity layer of opposite conductivity type and the semiconductor substrate constitute a diode. Characteristic input protection circuit device.