JPH0373567A - Input protector for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To relieve concentration of electric field at the P-N junction of drain and to improve electrostatic breakdown strength by covering a gate electrode, inserted between an input pad and the input gate of inner circuit, with a conductive layer connected with the input pad thereby raising the potential at the gate electrode, upon application of positive voltage onto the input terminal, and conducting an nMOS transistor. CONSTITUTION:A gate electrode 5 is connected through a polysilicon resistor 8 with GND wiring 10, and the N<+> diffusion layer 4 in drain region is connected through a contact hole 3-2 with an aluminum film 6a. The aluminum film 6a is connected with an input pad and an input gate and applied onto the gate electrode 5 of an nMOS transistor, thus providing a coupling capacitance C between the aluminum film 6a and the gate electrode. Upon application of positive voltage higher than the breakdown voltage onto the input, potential at the gate rises through the coupling capacitance C between the aluminum film 6a and the gate polysilicon 5, and the nMOS transistor Mn is turned ON for a time interval determined by the product of the coupling capacitance C and the resistance R between the gate and the GND. Concentration of electric field at the P-N junction of drain is relieved through the channel, resultingin in the improvement of electrostatic breakdown strength.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input protection device for a semiconductor integrated circuit, and in particular to an input protection device for a semiconductor integrated circuit.
The present invention relates to an input protection device for a semiconductor integrated circuit using an OS device.

[Conventional technology]

Conventionally, this type of input protection device was designed to clamp excessive input voltage by utilizing the breakdown phenomenon of nMO3) transistors, and basically the source region and gate electrode were grounded, and the input pad was connected to the drain region. There is also a structure in which a resistor is inserted between the input pad and the train region or between the gate electrode and the GND wiring as a protection resistor.

FIG. 4 shows such an input protection device, where the gate electrode 5 and source region (N+ diffusion layer 2) of an nMOS transistor are shown.
is connected to a GND wiring 9 made of an aluminum film, and the drain region (N+ diffusion layer 4) is connected to an input pad (not shown) and an input gate (not shown) of an internal circuit through an aluminum film 6.

[Problems that Senyo tries to solve]

In the conventional input protection device described above, when a positive voltage exceeding the breakdown voltage is applied, the nMO3) transistor causes avalanche breakdown and current flows to the GND terminal via the NPN parasitic bipolar transistor. An electric field concentrates at the PN junction of the drain, and electrons accelerated particularly at the boundary with the channel are injected into the gate oxide film, causing a small leakage current.

[Means to solve the problem]

The present invention provides an n-well formed in a P-well or a P-type substrate.
A semiconductor integrated circuit comprising a MOS transistor, and the source region and gate electrode of the nMO3) transistor are each connected to a GND wiring directly or through a resistor, and the drain region is connected to an input pad and an input gate of an internal circuit. In the circuit input protection device, the nMO3)
A conductive layer is present above the electrode gate of the transistor in a range that covers at least a part of the gate electrode via an interlayer film,
The conductive layer is connected to the input pad.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a pattern layout diagram showing one embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of the semiconductor chip taken along the line A--A in FIG. 1(a).

The N+ diffusion layer 2 in the source region of the nMO3) transistor formed in the P well 1 is connected to the GND wiring 9 through a contact hole 301, and the gate electrode 5 is connected to the GND wiring 9 via a polysilicon resistor 8 in the drain region. The N1 diffusion layer 4 is connected to the aluminum film 6a through a contact hole 3-2. Aluminum film 6a
is connected to the input pad and input gate, and nMO3h
Gate voltage of transistor f! It covers the top of 5. A coupling capacitance C is formed between the gate electrode and the gate electrode.

FIG. 2 is an equivalent circuit diagram of the first embodiment.

During normal operation, the nMOS transistor Mn is off, but when a positive voltage higher than the breakdown voltage is applied to the input, the aluminum film 6a and the gate polysilicon (5)
The potential of the gate rises due to the coupling capacitance C between nMOS and transistor Mn, and the transistor Mn turns on for a time determined by the product of the coupling capacitance C and the resistance R between the gate and GND. By creating a channel, the drain P
Electric field concentration at the N junction is alleviated and electrostatic withstand voltage is improved.

FIG. 6 is a pattern layout diagram showing a second embodiment of the present invention.

A polysilicon layer 9 having a certain area is connected to the gate electrode 5 of the nMO3h transistor, and its upper part is also covered with an aluminum film 6b like the gate electrode 5.

In this embodiment, the coupling capacitance between the input terminal and the gate electrode can be further increased, and the time for turning on the nMO8) transistor by increasing the potential of the gate when applying an electrostatic voltage can be increased.

〔Effect of the invention〕

As explained above, in the present invention, a positive voltage is applied to the input terminal by covering the upper part of the gate electrode inserted between the input pad and the input gate of the internal circuit with a conductive layer connected to the input pad. Sometimes the potential of the gate electrode is increased to
This has the effect of making the MOS transistor conductive, alleviating the concentration of electric field at the PN junction of the drain, and improving the electrostatic breakdown voltage.

[Brief explanation of drawings]

FIG. 1(a) is a pattern layout diagram showing a first embodiment of the present invention, FIG. 1(b) is a cross-sectional view of the semiconductor chip cut along the line A-A in FIG. 1(a), Fig. 2 is an equivalent circuit diagram of the first embodiment, Fig. 3 is a pattern layout diagram showing the second embodiment, Fig. 4(a) is a pattern layout diagram showing the conventional example, and Fig. 4(b) is A-A in Figure 4 (a>
FIG. 3 is a cross-sectional view of the semiconductor chip cut along a line corresponding to the line. 1...P well, 2...N+ diffusion layer (source region)
, 3.3-1.3-2... contact hole, 4...
・N+ diffusion layer (drain region), 5... gate electrode,
6.6a, 6b... Aluminum film, 7... P+ diffusion layer (well contact), 8... Polysilicon resistor, 9... Polysilicon film for capacitance, 10... GND wiring, 11... ...N-type semiconductor substrate, 12...input pad, 13...input gate.

Claims (1)

[Claims] It has an nMOS transistor formed in a P-well or a P-type substrate, the source region and gate electrode of the nMOS transistor are respectively connected to the GND wiring directly or through a resistor, and the drain region is connected to the input pad and the input gate of the internal circuit. In the input protection device for a semiconductor integrated circuit configured to be connected to An input protection device for a semiconductor integrated circuit, characterized in that the layer is connected to the input pad.