JPH0532908B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary MOS integrated circuit device (CMOS
IC).

[Prior art]

CMOS ICs have advantages such as low power consumption and a wide operating power supply voltage range, so they have rapidly become widely used in recent years. Figure 1 is
This is a circuit diagram showing the minimum unit of a CMOS circuit, and FIG. 2 is a sectional view showing a conventional example of a CMOS IC that actually realizes this circuit configuration. In the figure, A is a p-channel MOS transistor (p-MOST), and B is an n-channel MOS transistor (n-MOST). In Fig. 2, 1 is an n ^- type semiconductor substrate;
2 is a p ^- type island for forming n-MOST B, 3 is the source of p-MOST A, 4 is also the drain, 5 is the source of n-MOST B, 6 is also the drain, and 7 is the power supply terminal V. It is a p ⁺ contact layer for connecting to _{the SS} and also serves as a guard ring layer. 8 is an n ⁺ type contact layer for connection to the power supply terminal _VDD . Normally, as shown in Figure 1, the source 3 of p-MOST A is connected to the power supply terminal V _DD ,
The source 5 of n-MOST B is connected to the power supply terminal V _SS , the gates of both MOST A and B are commonly connected to the input terminal IN, and the drains 4 and 6 of both MOST A and B are commonly connected to the output terminal OUT. Connected.

Now, the breakdown voltage of a MOST is determined by the junction breakdown voltage and the gate voltage, and the thickness of the gate oxide film is usually the same for p-MOST and n-MOST. The source-drain breakdown voltage of n-MOST is
This is the withstand voltage of the CMOS circuit.

FIG. 3 shows an example of the voltage/current characteristics between the V _DD and V _SS terminals when the potential of the input terminal IN in FIG. 1 is set to V _SS . Under this condition, p-MOST A is completely turned on, and a voltage is present between the source and drain of n-MOST B. Point X in FIG. 3 is the source-drain breakdown voltage (BV _DS ) of n-MOST B, and when current is applied in this state, it is transferred to point Y as shown in the figure.

In FIG. 2, the n-MOST B includes a parasitic lateral npn transistor 11 whose base and emitter are connected through a resistor 12. Therefore, the breakdown voltage between its collector and emitter is BV _CER , which is almost the breakdown voltage between n ⁺ and p ^- . Therefore, in the region where the current value is low, the breakdown voltage BV _SD at the surface area (MOS part) where the gate electric field is applied is lower than the junction breakdown voltage mentioned above, and this determines the breakdown voltage between the source and drain ( X point). However, when avalanche occurs at point X, more and more electrons are injected into the base region of the parasitic npn transistor 11.
The breakdown voltage of the npn transistor 11 decreases to BV _CEO .
This point is point Y in FIG.

As explained above, the power supply breakdown voltage of a given CMOS circuit has a transfer phenomenon, and if a voltage higher than the voltage corresponding to point Y in Figure 3 is applied as a steady power supply voltage, it may be affected by surges etc. If the voltage exceeds the voltage corresponding to point X in FIG. 3, there is a problem in that due to the transfer phenomenon, the power supply voltage withstand voltage of the device drops to the voltage corresponding to point Y, resulting in destruction of the device. Furthermore, when avalanche breakdown occurs between the source and the drain, electrons and holes are injected into the gate, causing the device to deteriorate.

[Summary of the invention]

This invention was made in view of the above ^points , and it is an n ^{+ (} p ⁺ ) type diffusion region and n(p)− created on p ^- (n ^- ) type island
A Zener diode is formed by contacting the bulk of the MOST with a p ⁺ (n ⁺ ) type diffusion region for connecting to a low (high) potential, and this Zener voltage is
Lower the source/drain breakdown voltage (in the low current range) of MOST to eliminate the transfer phenomenon.
This provides a CMOS IC with substantially high power supply voltage.

[Embodiments of the invention]

FIG. 4 is a cross-sectional view showing the structure of an embodiment of the present invention. Portions equivalent to those of the conventional example shown in FIG. 2 are designated by the same reference numerals, and their explanation will be omitted.

In FIG. 4, 8a is an n ⁺ contact layer corresponding to 8 in the conventional example for connecting the bulk of p-MOST A to the high potential power supply terminal V _DD , but in this embodiment, this n ⁺ type contact layer 8
a connects the bulk of n-MOST B to the low potential power supply terminal
It is formed so as to be in contact with the p ⁺ type contact layer 7 for connection to V _SS , and the Zener voltage of the Zener diode 13 formed between the two is
If the avalanche breakdown voltage is set lower than the MOST source-drain avalanche breakdown voltage (point X in Figure 3), avalanche breakdown will not occur, so the power supply breakdown voltage will be transferred to the BV _CEO of the parasitic npn transistor 11 mentioned in the conventional example. There is no actual
It is possible to increase the power supply voltage of CMOS circuits.

Although the above embodiment shows a case where a p ^- type island is formed on an n type substrate, the present invention can be similarly applied to a case where an n ^- type island is formed on a p type substrate.

〔Effect of the invention〕

As detailed above, the CMOS according to this invention
In the IC, an n ⁺ type region for connecting the bulk of the p-MOST to a high potential point and a p ⁺ type region for connecting the bulk of the n-MOST to a low potential point are brought into contact,
Since the Zener voltage is set to be lower than the source/drain breakdown voltage of the MOST, the actual power supply breakdown voltage can be increased and deterioration of the MOST can be prevented.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the minimum unit of a CMOS circuit.
Figure 2 shows a CMOS that actually realizes this circuit configuration.
FIG. 3 is a cross-sectional view showing a conventional example of an IC, FIG. 3 is a diagram showing voltage/current characteristics between VV _DD and V _SS in this conventional example, and FIG. 4 is a cross-sectional view showing the structure of an embodiment of the present invention. . In the figure, 1 is an n ^- type substrate, 2 is a p ^- type island, 7 is a p ⁺ type region, 8a is an n ⁺ type region, 13 is a Zener diode, A is a p-MOST, and B is an n
-MOST. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 a p ⁽ or n) channel MOS transistor formed on an n - (or p ^- ) type semiconductor substrate;
In the semiconductor substrate connected in series with an n (or p) channel MOS transistor formed on a p ^- (or n ^- ) type island in the semiconductor substrate,
For connecting the bulk of the above p (or n) channel MOS transistor to the high (or low) potential point
An n ⁺ (or p ⁺ ) type region and a p ⁺ (or n ⁺ ) type region for connecting the bulk of the n (or p) channel MOS transistor to a low (or high) potential point are in contact with each other. The Zener voltage of the Zener diode is controlled by the n (or p) channel MOS.
A complementary MOS integrated circuit device characterized by having a source-drain breakdown voltage lower than that of a transistor.