JPH0669429A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To protect the breaking of a gate oxide film of a transistor for inter nal circuit protection concerning a semiconductor circuit having a protective device for protecting the breaking of the gate oxide film of the MOS transistor due to static electricity or the like. CONSTITUTION:First and second protective devices 21 and 22 are respectively inserted and connected between a signal line 15 extending from an input pad 1 to an internal circuit 2 of a semiconductor integrated circuit and each drain of first and second transistors QA and QB having different conductive from types each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit equipped with a protection element for protecting the gate oxide film of a MOS transistor from destruction due to static electricity or the like.

In a CMOS semiconductor circuit, a protection element is provided to protect an input circuit from electrostatic breakdown. However, when a MOS transistor is used as this protection element, the gate oxide film thereof may be destroyed by static electricity, and therefore protection of the protection element is also required.

[0003]

2. Description of the Related Art FIG. 9 shows a circuit diagram of an example of a conventional semiconductor circuit. In the figure, between the input pad 1 and the internal circuit 2,
P-channel MOS transistor Q _A and N-channel M
The drains of the OS transistors Q _B are commonly connected, and M
The source of the OS transistor Q _A is the power supply voltage _VDD terminal,
The source of the MOS transistor Q _B is connected to the power supply voltage V _SS terminal, respectively. D _A is a parasitic diode of the MOS transistor Q _A , and D _B is a parasitic diode of the MOS transistor Q _B.

FIG. 10 is a sectional view showing an example of a conventional semiconductor circuit. In the figure, P-type diffusion regions 4 and 5 formed on the N-type substrate 3 are the source and drain of the P-channel MOS transistor Q _A shown in FIG. 9, and the gate electrode 7 is formed on the oxide film 6. Has been formed.

On the other hand, a P well formed on the N type substrate 3
The N-type diffusion regions 9 and 10 formed in the
Channel MOS transistor Q_BSource and drain
In addition, the gate electrode 12 is formed on the gate oxide film 11.
Has been. N type substrate 3 is Q_AAnd Q_BBack gate of
I am configuring. The drains 5 and 10 are commonly connected.
ing. Furthermore, for the PN junction between the drain 5 and the N-type substrate 3
More parasitic diode D _AAre formed, and the drain 10 and P
Parasitic diode D due to PN junction of well 8_BFormed
Has been.

In the conventional semiconductor circuit having the above structure,
The input signal input to the input pad 1 is a signal within the voltage range lower than the power supply voltage V _{DD and} higher than the power supply voltage V _SS , and input to the internal circuit 2 as it is. On the other hand, when an excessively high voltage of V _DD or more is applied to the input pad 1 due to static electricity or the like, the parasitic diode D _A turns on and the MOS
Since the transistor Q _A is turned on, the input high voltage is limited to V _DD and input to the internal circuit 2.

On the other hand, when an excessively high voltage which is larger than V _{SS in the} negative direction is applied to the input pad 1, the parasitic diode D _B
Is turned on and the MOS transistor Q _B is turned on, the input high voltage is input to the internal circuit 2 while being limited to V _SS . Thus, in this conventional semiconductor circuit,
Excessive voltage (noise) above V _DD and below V _SS to the internal circuit 2
Acts as a protection circuit, which prevents the application of

[0008]

However, in the conventional semiconductor circuit described above, the P-channel MOS transistor Q _A of FIG. 10 is input when an excessively large voltage is input in the positive direction from V _DD .
When a high voltage is directly input to the gate oxide film 6 of the N channel MOS transistor Q _B , and when an excessively large voltage is input in the negative direction from V _SS , the high voltage is applied to the gate oxide film 11 of the N-channel MOS transistor Q _B. If a high voltage is input for a long period of time, the gate oxide film 6 or 11 will be destroyed, and as a result, a leak current will flow, leading to deterioration of the IC (integrated circuit).

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor circuit that solves the above problems by preventing the protection transistor from being destroyed.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in the figure, the present invention includes a signal line 15 extending from an input pad 1 to an internal circuit 2 of a semiconductor integrated circuit, and drains of first and second transistors Q _A and Q _{B having} different conductivity types. It is characterized in that the first and second protection elements 21 and 22 are respectively connected between them.

[0011]

In the present invention, one of the first and second transistors Q _A and Q _B is turned on for an excessive input,
When the internal circuit 2 is protected, the protection elements 21 and 22 prevent the gate oxide films of the transistors Q _A and Q _B from being applied with an excessively high level input voltage directly from the input pad 1.

[0012]

1 is a circuit diagram of a first embodiment of the present invention.
In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 2, Q ₁ is a P-channel MOS transistor corresponding to the first protection element 21, and its source is a P-channel MOS transistor corresponding to the first transistor.
The drain of the channel MOS transistor Q _{A and} the drain of Q ₁ are connected to the signal line 15.

Q ₂ is an N-channel MOS transistor corresponding to the second protection element 22, the source of which is connected to the drain of an N-channel MOS transistor Q _B corresponding to the second transistor, and the drain of Q ₂ . Is connected to the signal line 15. Further, both gates of the transistors Q ₁ and Q ₂ are open.

FIG. 3 shows a sectional view of the first embodiment of FIG.
In the figure, the N-type diffusion regions 32, P are directly formed on the N-type substrate 31.
The type diffusion regions 33, 34 and 35 are formed, and in the P well 40, the N type diffusion regions 41, 42 and 43 and the P type diffusion region 44 are formed.

Then, after gate oxide films 36, 38, 45 and 47 are formed at predetermined positions, gate electrodes 37 and 3 are formed.
9, 46 and 48 are deposited on the gate oxides 36, 38, 45 and 47. Furthermore, the N-type diffusion regions 32, P
The type diffusion region 33 and the gate electrode 37 are connected to the power supply voltage V _DD input terminal, and the N-type diffusion region 43, the P-type diffusion region 44 and the gate electrode 48 are connected to the power supply voltage V _SS input terminal, respectively. The P-type diffusion region 35 and the N-type diffusion region 41 are connected to the signal line 15 connecting the input pad 1 and the internal circuit 2.

As a result, the P-type diffusion regions 33 and 34 form the source and drain of the transistor Q _A , the P-type diffusion regions 34 and 35 form the source and drain of the transistor Q ₁ , and the gate electrodes 37 and 39 form. The gates of the transistors Q _A and Q ₁ are formed. The N-type diffusion regions 41 and 42 respectively form the drain and source of the transistor Q ₂ , and the N-type diffusion regions 42 and 43 respectively form the drain and source of the transistor Q _B.

In the first embodiment shown in FIGS. 2 and 3, when an excessive voltage larger than V _{DD in the} positive direction is input to the input pad 1, the transistors Q ₁ and Q _A are turned on, and the internal circuit 2 Is input to the circuit after being limited to the voltage V _DD . Also,
When an excessive voltage larger than V _{SS in the} negative direction is input to the input pad 1, the transistors Q ₂ and Q _B are turned on, and the internal circuit 2 is limited to the voltage V _SS and input.

Here, since no electric field is directly applied to the gate oxide films 36 and 47 of the transistors Q _A and Q _B when the above-mentioned excessive voltage is input, the gate oxide films 36 and 47 can be prevented from being destroyed.

Next, a second embodiment of the present invention will be described. FIG. 4 is a circuit diagram of the second embodiment of the present invention, and FIG. 5 is a sectional view of the second embodiment of the present invention. The same components as those in FIGS. Is omitted. Figure 4
In the above, Q ₃ is P corresponding to the first protection element 21.
In the channel MOS transistor, its gate and source are connected to the drain of the transistor Q _A , and its drain is connected to the signal line 15.

Q ₄ is an N-channel MOS transistor corresponding to the second protection element 22. Its gate and source are connected to the drain of the transistor Q _B , and its drain is connected to the signal line 15.

In FIG. 5, the P-type diffusion region 34 constitutes the drain of the transistor Q _A and the source of the transistor Q ₃ , and the P-type diffusion region 51 constitutes the drain of the transistor Q ₃ on the gate oxide film 52. The gate electrode 53 constitutes the gate of the transistor Q ₃ . A transistor Q ₄ having the N-type diffusion regions 54 and 45 as the drain and the source and the gate electrode 56 on the gate oxide film 55 as the gate is formed in the P well 40.

In this embodiment, the gates of the transistors Q ₃ and Q ₄ are the sources of the transistors themselves and the transistor Q _A.
And the point connected to the drain of Q _B is different from the first embodiment.

In this embodiment, V_DDGreater excess in the positive direction
Transistor Q when voltage is input₃And Q_AEach is on
And V_SSWhen inputting an excessively large voltage in the negative direction,
Register Q_FourAnd Q_BIs turned on respectively, in any case
Excessive input voltage V_DDOr V _SSInternal circuit 2
The output to the internal circuit 2 is protected.
At this time, the excessive input voltage is the transistor Q_A, Q_BGe of
Since it is not directly applied to the oxide films 36 and 47,
It is possible to prevent the gate oxide films 36 and 47 from being destroyed, and
The flow can be prevented from flowing.

Next, a third embodiment of the present invention will be described.
It FIG. 6 is a circuit diagram of the third embodiment of the present invention, and FIG. 7 is the present invention.
3 is a cross-sectional view of a third embodiment of the present invention, which has the same structure as FIG. 1 and FIG. 3, respectively.
The same reference numerals are given to the components, and the description thereof will be omitted. Figure 6
At transistor Q_ADrain and signal line 15
Between the first resistance R₁Is connected, and the transistor Q
_BA second resistor R is provided between the drain and the signal line 15.₂But
It is connected.

The above-mentioned first and second resistors R ₁ and R
_In the embodiment of FIG. 7, ₂ is realized by the resistors 62 and 63 made of polysilicon formed on the element isolation oxide film 61 between the transistors Q _A and Q _B. One end of the resistor 62 is connected to the P-type diffusion region 34, one end of the resistor 63 is connected to the N-type diffusion region 45, and the resistor 6 is also connected.
2 and 63 are connected to the signal line 15, respectively.

In this embodiment, the excessive voltage causes the resistance R ₁ (6
2) and R ₂ (63) to the drains of the transistors Q _A and Q _B, no excessive voltage is directly applied to the gate oxide films 36 and 47, and the gate oxide films 36 and 4 are not applied.
The noise resistance of No. 7 can be improved. This allows
It is possible to significantly reduce the ratio of leakage current flowing as compared with the conventional case.

Although the resistors R ₁ and R ₂ are described as the resistors 62 and 63 made of polysilicon in FIG. 7, the resistors are not limited to these, and as shown in the sectional view of FIG. It is also possible to use diffusion resistors 72 and 73 formed by N-type diffusion regions formed in 71.

[0028]

As described above, according to the present invention, since the excessive input voltage is not directly applied to the gate oxide film of the protective transistor, the gate oxide film of the protective transistor can be prevented from being destroyed. Therefore, it is possible to prevent the generation of leak current and the deterioration of IC.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit diagram of the first embodiment of the present invention.

FIG. 3 is a sectional view of the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a sectional view of a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a third embodiment of the present invention.

FIG. 7 is a sectional view of a third embodiment of the present invention.

FIG. 8 is a sectional view of a modification of the third embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional example.

FIG. 10 is a sectional view of a conventional example.

[Explanation of symbols]

1 Input Pad 2 Internal Circuit 15 Signal Line 21 First Protective Element 22 Second Protective Element 36, 47, 52, 55 Gate Oxide Film Q _A First Transistor Q _B Second Transistor Q ₁ , Q ₃ P Channel MOS transistor Q ₂ , Q ₄ N channel MOS transistor R ₁ , R ₂ resistance

Claims (4)

[Claims] 1. A first transistor and a second transistor (Q) having different conductivity types, each having a drain connected to a signal line (15) extending from an input pad (1) to an internal circuit (2) of a semiconductor integrated circuit. _A , Q _B ), which protects the internal circuit (2) by turning on one of the first and second transistors (Q _A , Q _B ) against an excessive input, The first and second protection elements (21, 22) are respectively connected between the drains of the first and second transistors (Q _A , Q _B ) and the signal line (15). Characteristic semiconductor circuit. 2. The first protection element (21) is the first protection element (21).
Transistor (Q _A) Same conductivity type and gate
Open the third transistor (Q₁) And said
The second protection element (22) is the second transistor (Q
_B) With the same conductivity type as the above, and the gate is opened.
Transistor (Q₂).
The semiconductor circuit described. 3. The first protection element (21) comprises the first protection element (21).
Transistor (Q _A) With the same conductivity type as the first
Register (Q_A) Its drain, its gate and source
A third transistor (Q₃), And
The second protection element (22) is the second transistor.
(Q_B) Same conductivity type as the second transistor
(Q_B) Drain has its gate and source connected respectively.
Continued fourth transistor (Q_Four) Is
The semiconductor circuit according to claim 1. 4. The first and second protection elements (21, 2)
2. The semiconductor circuit according to claim 1, wherein 2) are resistors (R ₁ and R ₂ ), respectively.