JP2979716B2 - CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit, and more particularly to a CMOS integrated circuit having a latch-up protection circuit.

[0002]

2. Description of the Related Art A P-well type CMO according to the prior art
The S integrated circuit will be described with reference to FIG.

On the surface of an N-type semiconductor substrate 1, independent P-type wells 2 and 3 are selectively formed.

The surface of the P-type well 2 has N ⁺ -type diffusion layers 4 to
7 and a P ⁺ type diffusion layer 8 are selectively formed. N
^A gate electrode 17 is formed between the ⁺ type diffusion layers 4 and 5 with a gate oxide film 22 interposed therebetween. On the other hand, a gate electrode 18 is formed between the N ⁺ type diffusion layers 6 and 7 via a gate oxide film 22.

On the surface of the P-type well 3, an N ⁺ type diffusion layer 9,
10 and a P ⁺ type diffusion layer 11 are formed. A gate electrode 15 is formed between N ⁺ type diffusion layers 9 and 10 via a gate oxide film 22.

On the surface of N-type semiconductor substrate 1 between P-type wells 2 and 3, independent N ⁺ -type diffusion layers 12 and P ⁺ -type diffusion layers 13 and 14 are formed. P ⁺ type diffusion layer 13
And 14, a gate electrode 16 is formed with a gate oxide film 22 interposed therebetween.

In general, a parasitic thyristor structure exists in a CMOS integrated circuit. When the thyristor loop is activated for some reason, a large current continues to flow in the circuit, and the metal wiring made of aluminum or the like may be blown, or the PN junction may be broken, and the integrated circuit may be damaged.

[0008] This phenomenon is called latch-up, and the CMO
This is a very significant disadvantage of the S integrated circuit. Generally, this latch-up is often caused by external noise that enters the input / output terminal of the CMOS integrated circuit from outside.

[0009]

In a CMOS integrated circuit to which three types of potentials are externally supplied, latch-up occurs due to the order in which the three types of potentials are supplied in addition to latch-up due to external noise. May be.

The three types of power supply potentials are defined as a maximum potential (V _CC ),
As the intermediate potential (GND) and the lowest potential ( _VSS ), the following power supply order may be considered.

After GND and V _CC are supplied, V _SS is supplied.

V _CC is supplied after GND and V _SS are supplied.

After V _SS and V _CC are supplied, G
ND is supplied.

There is a problem that latch-up is liable to occur particularly in these power supply sequences.

Next, a latch-up generation mechanism in the following case will be described with reference to FIGS. 3 (a) and 3 (b).

First, as shown in FIG.
_CC (positive potential) is supplied from an input terminal 19 to the N ⁺ type diffusion layer 12 and the P ⁺ type diffusion layer 14. GND (ground potential)
Is supplied from the input terminal 20 to the N ⁺ type diffusion layers 4 and 9 and the P ⁺ type diffusion layer 11. V _SS (negative potential) is input terminal 21
Is supplied to the N ⁺ type diffusion layer 7 and the P ⁺ type diffusion layer 8.

A predetermined wiring is connected to the N ⁺ type diffusion layers 5, 6, 10, the P ⁺ type diffusion layer 13 and the gate electrodes 15 to 18.

In the CMOS integrated circuit in such a potential connection state, the potential of the N-type semiconductor substrate 1 is fixed at V _CC via the N ⁺ -type diffusion layer 12. The potential of the P-type well 2 is fixed at V _SS via the P ⁺ -type diffusion layer 8. P
The potential of the mold well 3 is fixed to GND via the P ⁺ type diffusion layer 11.

The P ⁺ type diffusion layer 14 serves as a source of a P-channel MOSFET formed on the surface of the N-type semiconductor substrate 1. The N ⁺ type diffusion layer 7 becomes a source of an N channel MOSFET formed on the surface of the P type well 2. The N ⁺ type diffusion layer 9 is an N channel M formed on the surface of the P type well 3.
OSFET source. N ⁺ type diffusion layer 4 serves as a drain of an N channel MOSFET formed on the surface of P type well 2.

Next, as shown in FIG. 3B, the input terminal 21 is brought into a floating state. G as in the case of
ND and V _CC are supplied and V _SS is not supplied. At this time, since the P-type well 2 is not connected to the fixed potential (V _SS ), it becomes a floating state,
The potential of the mold well 2 becomes an intermediate potential between GND and V _CC .

That is, the value of the intermediate potential of the P-type well 2 is
The capacitance C ₁ P-N junction between the N-type semiconductor substrate 1 and the P-type well 2 that is fixed to V _CC, is fixed to the GND N ⁺
Junction capacitance C ₂ between the p-type well 2 and the p-type diffusion layer 4
Is determined by the capacity division.

Here, the potential of the P-type well 2 is
And N ⁺ -type diffusion layer when P-N ⁺ becomes more built-in potential of the junction diode consisting of 4, a large amount of electrons are injected into the P-type well 2 from the N ⁺ diffusion layer 4, V _CC and GND to which a trigger Latch-up occurs in between.

In such a CMOS integrated circuit, measures such as designating the order of supplying power are taken, and there is a problem that there are many restrictions on its use.

An object of the present invention is to provide a CMOS integrated circuit in which latch-up does not occur even when the lowest potential is supplied after the highest potential and the intermediate potential are supplied.

[0025]

In a CMOS integrated circuit according to the present invention, a first diffusion layer and a second diffusion layer of opposite conductivity type are selectively formed on one main surface of a semiconductor substrate of one conductivity type. A third diffusion layer of one conductivity type is selectively formed on the surface of the second diffusion layer, the semiconductor substrate is connected to an input terminal having the highest potential, and the second diffusion layer is connected to an input terminal having the lowest potential. An N-channel enhancement MOSFET, wherein the first diffusion layer and the third diffusion layer are connected to an intermediate potential input terminal, and a drain and a source are respectively connected to the lowest potential input terminal and the intermediate potential input terminal.
And the drain is the N-channel enhancement MOS
A P-channel enhancement MOSFET connected to the gate of the FET, the source and the gate of which are connected to the lowest potential input terminal; the drain, source and gate being the highest potential input terminal, the gate of the N-channel enhancement MOSFET, and the lowest potential An N-channel depletion MOSFET connected to an input terminal is provided.

The P-channel enhancement M
A resistor is provided instead of the OSFET, and one end of the resistor is connected to the gate of the N-channel enhancement MOSFET, and the other end is connected to the lowest potential input terminal.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG.

Descriptions of parts common to FIGS. 3A and 3B are omitted.

As shown in FIG. 1, V _CC (+5 V) is supplied from an input terminal 19 to an N ⁺ type diffusion layer 12 and a P ⁺ type diffusion layer 14.
Supplied to GND (0 V) is applied from the input terminal 20 to N ⁺
Are supplied to the diffusion layers 4 and 9 and the P ⁺ diffusion layer 11.
V _SS (−5 V) is supplied from the input terminal 21 to the N ⁺ type diffusion layer 7 and the P ⁺ type diffusion layer 8.

Further, the following three MOSFETs are connected as a latch-up prevention circuit.

An N-channel enhancement MOSFET N _E whose drain and source are connected to the V _SS input terminal 21 and the GND input terminal 20, respectively.

[0032] and the gate of the drain N-channel enhancement MOSFETN _E, drain, and a gate V
A P-channel enhancement MOSFET P _E connected to the _SS potential input terminal 21;

The drain, source, gate of the P-channel enhancement MOSFETP _E respectively drain and N-channel enhancement MOSFETN
N-channel depletion MOSFET N _D connected to the gate of _E , V _CC input terminal 19 and V _SS input terminal 21.

N _E , P _E and N _D constitute a ratio circuit,
Each gate, source, and drain are connected at a node 23.

Next, the operation of this embodiment will be described.

_Vcc (+ 5V) and GND (0V) are supplied to the _Vcc input terminal 19 and the GND input terminal 20, respectively, and _Vss (-5V) is not supplied to the _Vss input terminal 21. explain.

[0037] Here -3V the V _T of for example N-channel depletion MOSFETN _D, -1V the V _T of the P-channel enhancement MOSFETP _E, and 2V the V _T of the N-channel enhancement MOSFETN _E.

Although the _Vss input terminal 21 is floating, it has an intermediate potential between _Vcc and GND as described in the section of the task.

[0039] For example, and as a result, it becomes 2.5V, N-channel depletion MOSFETN _D has a gate 2.
ON because it is 5V. The P-channel enhancement MOSFET P _E is off since the gate is 2.5V. Therefore the potential of the node 23 becomes close to V _CC level, N-channel enhancement MOSFETN _E is turned ON.

The potential of the result V _SS input terminal 21 is GND
The GN formed in the P-type well 2 is fixed to a nearby value.
The potentials of the N ⁺ type diffusion layer 4 fixed to the D potential and the P type well 2 become substantially equal. Electron injection from the N ⁺ type diffusion layer 4 does not occur, so that the occurrence of latch-up is
00% can be prevented.

Subsequently, V _SS (−5) is applied to the V _SS input terminal 21.
V) is supplied, the gate potentials of the MOSFETs N _D and P _E are fixed at V _SS (−5 V), the MOSFET N _D is turned off, and the MOSFET P
_E is V _T is turned ON so -1V. As a result, node 23
Is the -4V fell one step of V _T of MOSFETP _E.
Since the drain potential of the MOSFET NE is V _SS (−5 V) and the source potential is GND (0 V), the MOSFET N _E
The potential difference between the drain and the gate of _E becomes 1 V, and MOSF
ETN _E turns off.

Therefore, when all the potentials are supplied, the latch-up prevention circuit is turned off, and has no adverse effect on the CMOS integrated circuit of the main body.

Next, a second embodiment of the present invention will be described with reference to FIG.

[0044] In this embodiment, one end in place of P-channel enhancement MOSFETP _E to the gate of N-channel enhancement MOSFETN _E in the first embodiment uses a resistor R connecting the other end to a minimum input voltage terminal 21 .

As in the first embodiment, the MOSFETs N _E ,
Without setting the V _T of N _D, it is possible to obtain the same effect as the first embodiment.

[0046]

According to the present invention, an N-channel enhancement MOSFET and an N-channel depletion MOSFET are provided in a CMOS integrated circuit.
OSFET, P-channel enhancement MOSFET
Alternatively, a ratio circuit combining resistance elements is connected.
As a result, it was possible to completely prevent the occurrence of latch-up of the CMOS integrated circuit.

This latch-up prevention circuit allows the lowest input terminal to be fixed near the intermediate potential between the time when the lowest potential input terminal and the intermediate potential input terminal are input and the time when the lowest input terminal is input. Further, after all the power is turned on, the latch-up prevention circuit has no adverse effect on the CMOS integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a CMOS integrated circuit showing a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a CMOS integrated circuit showing a second embodiment of the present invention.

FIG. 3 is a schematic sectional view illustrating a conventional CMOS integrated circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 N-type semiconductor substrate 2, 3 P-type well 4 to 7 N ⁺ -type diffusion layer 8 P ⁺ -type diffusion layer 9, 10 N ⁺ -type diffusion layer 11 P ⁺ -type diffusion layer 12 N ⁺ -type diffusion layer 13, 14 P ⁺ Diffusion layer 15-18 Gate electrode 19-21 Input terminal 22 Gate oxide film 23 Node N _E N-channel enhancement MOSFET N _D N-channel depletion MOSFET P _E P-channel enhancement MOSFET R Resistance

Claims (2)

(57) [Claims] A first diffusion layer and a second diffusion layer of a reverse conductivity type are selectively formed on one main surface of a semiconductor substrate of one conductivity type, and a first diffusion layer and a second diffusion layer are selectively formed on a surface of the second diffusion layer. Third of conductivity type
Is formed, the semiconductor substrate is connected to an input terminal having the highest potential, the second diffusion layer is connected to an input terminal having the lowest potential, and the first diffusion layer and the third diffusion layer are connected to each other. An N-channel enhancement M connected to an intermediate potential input terminal and having a drain and a source connected to the lowest potential input terminal and the intermediate potential input terminal, respectively;
An OSFET, a P-channel enhancement MOSFET having a drain connected to the gate of the N-channel enhancement MOSFET, a source and a gate connected to the lowest potential input terminal, and a drain, source and gate respectively connected to the highest potential input terminal and the N N-channel depletion MO connected to the gate of the channel enhancement MOSFET and the lowest potential input terminal
A CMOS integrated circuit including an SFET. 2. A P-channel enhancement MOSFE.
2. The CMOS integrated circuit according to claim 1, further comprising a resistor instead of T, one end of which is connected to the gate of the N-channel enhancement MOSFET and the other end is connected to the lowest potential input terminal.