JP3499578B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
The present invention relates to C), and particularly to a power supply protection circuit for an IC having three or more independent power supply wirings.

[0002]

2. Description of the Related Art ICs may have a surge caused by static electricity or the like from an external connection terminal even in an operating state after being mounted on a circuit board or the like. Here, the surge is defined as an overvoltage or an overcurrent whose value changes abruptly with respect to the signal voltage or signal current during normal operation. I
In C, a trigger current is generated due to the mixing of the surge, a parasitic transistor inside the semiconductor substrate is turned on, and a latch-up phenomenon occurs in which a large through current continues to flow between the power supplies. Further, when a relatively large surge is mixed in, the surge around the I
The C internal circuit may be destroyed.

To cope with these problems, conventionally, in an IC having three types of independent power supply wiring, measures such as provision of a power supply protection circuit as shown in FIG. 13A or 13B are taken. There is.

In the ICs of FIGS. 13 (a) and 13 (b), the first power supply terminal 11 is supplied with a high power supply potential VDD, and the second power supply terminal 12 and the third power supply terminal 13 respectively correspond. Power supply potentials VSS1 and VSS2 of low potential are supplied. Three types of independent power supply wirings 1 to 3 are laid out in correspondence with the above three types of independent power supply terminals.

Then, in the IC of FIG. 13A, between the signal input terminal 14 and the first power supply terminal 11,
A P-channel insulated gate transistor (PMOS transistor) P1 is inserted, and an N-channel insulated gate transistor (NMOS transistor) N1 is inserted between the signal input terminal 14 and the second power supply terminal 12. ing.
Furthermore, a PMOS transistor P2 and an NMOS transistor N2 are connected in parallel between the first power supply terminal 11 and the second power supply terminal 12, and between the first power supply terminal 11 and the third power supply terminal 13, PMOS transistor P
3 and the NMOS transistor N3 are connected in parallel with each other, and the PMOS transistor P6 and the NMOS transistor N6 are connected in parallel with each other between the second power supply terminal 12 and the third power supply terminal 13. Reference numeral 15 is an input buffer circuit for taking in the signal input from the signal input terminal 14 to the IC internal circuit.

Transistors P1 for protecting these power supplies,
P2, P3, P6 and N1, N2, N3, N6 are I
The respective gate / source / substrate regions are connected to each other so that they are turned off during the normal operation of C. In addition, these transistors have a bipolar transistor (not shown) and a source
Punch-through between the drain diffusion layers or an ON operation of the MOS transistor itself causes an apparent ON state between the source and the drain, and absorbs a surge in the power supply terminal (suppresses fluctuations in the power supply potential due to the surge). This makes it possible to prevent the surge from spreading inside the IC and prevent the occurrence of a latch-up phenomenon and the destruction of the IC internal circuit around the external terminal.

That is, in the IC shown in FIG. 13A, the surge applied to the input terminal is caused by the transistors P1 and N1.
Is turned on and absorbed by the first power supply terminal 11 and the second power supply terminal 12. The surge applied to the first power supply terminal 11 is generated by the transistors P2, N2 and the transistor P.
3 and N3 are turned on, and the second power supply terminal 12 and the third
It is absorbed by the power supply terminal 13. The surge applied to the second power supply terminal 12 is absorbed by the first power supply terminal 11 and the third power supply terminal 13 by turning on the transistors P2, N2 and the transistors P6, N6. The surge applied to the third power supply terminal 13 turns on the transistors P3, N3 and the transistors P6, N6, and the first power supply terminal 1
It is absorbed by the first and second power supply terminals 12.

On the other hand, in the IC shown in FIG.
A PMOS is provided between the second power supply terminal 12 and the third power supply terminal 13.
The transistor P6 and the NMOS transistor N6 are connected in parallel with each other. In this case, the transistor P
The gate of 6 is connected to the second power supply terminal 12 .

By the way, if the internal resistance of the power supply connected to the power supply terminal is high, the fluctuation of the power supply potential due to the surge cannot be instantaneously absorbed, and the occurrence rate of the latch-up phenomenon or the like cannot be suppressed small. .

That is, as shown in FIGS. 13A and 13B, in an IC in which three or more types of independent power supply wirings are laid out, two power supply terminals (for example, the first power supply terminal 11 and the second power supply terminal) are provided. From the power supply potentials VDD and VSS1 of the external power supply directly connected to the power supply terminal 12), the power supply potential VSS2 of the remaining power supply terminal (here, the third power supply terminal 13) is boosted to the outside of the IC or on the same IC. A system configuration generated by a circuit (not shown) or a step-down power supply circuit (not shown) is often used.

This step-up power supply circuit or step-down power supply circuit normally generates a step-up voltage or step-down voltage from the original power supply voltage by capacitive coupling or resistance division, and its internal resistance is the internal power supply of the original power supply. It is 100 to 1000 times more than the resistance. The internal resistance of the step-up power supply circuit or the step-down power supply circuit is set by the current consumption in the normal operation state, but the instantaneous overcurrent generated by the surge is much larger than the current consumption in the normal operation.

Therefore, when the step-up power supply circuit or the step-down power supply circuit is used as the surge absorbing power supply, the surge cannot be sufficiently absorbed, and the latch-up phenomenon is likely to occur. In addition, when a surge is directly applied to the power supply terminal to which power is supplied from the step-up power supply circuit or the step-down power supply circuit, the bipolar transistor itself that forms the thyristor parasitic on this power supply terminal turns on, so latch-up occurs. The phenomenon is more likely to occur.

Therefore, as described above, the third power supply terminal 13
In order to absorb the surge applied to the first power supply terminal 11, a transistor P3 and a transistor P3 in which respective gate / source / substrate regions are connected between the third power supply terminal 13 and the first power supply terminal 11 N3 is connected,
In order to absorb the surge applied to the third power supply terminal to the second power supply terminal 12, the third power supply terminal 13 and the second power supply terminal 12
A transistor P6 and a transistor N6 whose gates and sources are connected to each other are connected between and.

On the other hand, when the user desires to arbitrarily set the power supply potential VSS2 of the third power supply terminal 13 connected to the power supply having a relatively high internal resistance, the power supply potential VSS2 of the third power supply terminal 13 is compared with the internal resistance. If the transistor P6 and the transistor N6 are turned on during normal operation when the potential relationship between the second power supply terminal 12 connected to a relatively low power supply and the power supply potential VSS1 is reversed and used, P6 and transistor N6
Must be omitted.

However, if the transistors P6 and N6 are omitted, the path for absorbing the surge applied to the third power supply terminal 13 is connected to the first power supply terminal 11 and the transistors P3 and N are connected.
Since it is limited to 3, there is a problem that the surge absorption capacity becomes weak.

When the power supply potentials VSS1 and VSS2 are lower than the power supply potential VDD, the conditions for turning off the transistors P6 and N6 are as follows: VSS1 ≧ VSS2 or | Vthp |> | VSS1-VSS2 |, And Vthn> VSS
2-VSS1. Here, Vthp is the threshold voltage of the transistor P6, and Vthn is the threshold voltage of the transistor N6.

The above | Vthp | and Vthn are usually
The potential relation between VSS2 and VSS1 is about 1V, but the transistor N6 forms a forward diode when the above potential relation is reversed, so that the substrate region of the transistor N6 (P well region)
A forward leakage current flows from the drain to the drain (N-type impurity region). In order to prevent the occurrence of this forward leakage current, VSS2 must be set equal to or lower than VSS1.

[0018]

As described above, the conventional IC in which three or more types of independent power supply wirings are laid out
In consideration of the case where the potential relationship between the power supply terminal connected to the power supply having a relatively high internal resistance and the power supply terminal connected to the power supply having a relatively low internal resistance is reversed and used,
It is necessary to omit connecting a MOS transistor for power supply protection between two power supply terminals, and the ability to absorb a surge applied to a power supply terminal connected to a power supply having a relatively high internal resistance is weakened. was there.

The present invention has been made to solve the above problems, and the potential relationship between a power supply terminal connected to a power supply having a relatively high internal resistance and a power supply terminal connected to a power supply having a relatively low internal resistance. It is possible to connect a MOS transistor for power supply protection between the two power supply terminals even when they are used by reversing, and surge applied to the power supply terminal connected to the power supply with relatively high internal resistance. It is an object of the present invention to provide a semiconductor integrated circuit capable of enhancing the ability to absorb the.

[0020]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first power supply terminal formed on a semiconductor substrate and supplied with a predetermined power supply potential; and a first power supply terminal formed on the semiconductor substrate. A second power supply terminal, which is formed on the semiconductor substrate and has a lower or higher potential than the first power supply terminal, and a second power supply terminal to which a power supply potential lower or higher than that of the power supply terminal is supplied; A third power supply terminal, to which a power supply potential different from the power supply potential to be supplied to the terminal is supplied, and a source / drain formed between the second power supply terminal and the third power supply terminal formed on the semiconductor substrate. A MOS transistor connected to the power source for protection, the gate and the substrate region being connected to the first power terminal .
2, the power supply potential supplied to the third power supply terminal is
Both have a low potential with respect to the power supply potential supplied to the source terminal
Or high potential, the power source potential is applied to the second and third power source terminals.
Change the connection of the power supply that supplies power, or the second power supply
The potential obtained by boosting the power supply potential supplied to the terminal is
By supplying to the third power supply terminal, the second and third power supplies
Used by reversing the potential relationship of the power supply potential supplied to the terminals
It is characterized by being done .

[0021]

[Effect to the gate electrode of the P MOS transistors of the power protection that is connected between a second power supply terminal and a third power supply terminal, higher than the power supply potential of the power supply potential or the third power supply terminal of the second power supply terminal or by the power supply potential of the equivalent of the first power supply terminal is applied, never the PMOS transistor is turned on during normal operation by the potential relationship between the second power supply terminal and a third power supply terminal, i.e., second power supply Regardless of the potential difference between the terminal and the third power supply terminal, the surge applied to one of the second power supply terminal and the third power supply terminal can be released from the other and the surge withstand characteristic can be improved.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a power supply protection circuit for an IC according to the first embodiment of the present invention.

In this IC, a first power supply terminal 11, a second power supply terminal 12 and a third power supply terminal 13 are provided. The first power supply terminal 11 has a power supply potential VDD (for example, +5).
V) is supplied, and the second power supply terminal 12 is supplied with a power supply potential VSS1 (for example, 0V) lower than the power supply potential VDD,
The third power supply terminal 13 is supplied with a power supply potential VSS2 (eg, -5V) lower than the power supply potential VDD. Each of the power supply terminals is, for example, an external connection terminal, and three types of independent power supply wirings 1 to 3 are laid out corresponding to the three types of independent power supply terminals.

The second power supply terminal 12 and the third power supply terminal 13
Is connected between the source and drain of the enhancement type PMOS transistor P0, and the gate electrode and substrate region (substrate, back gate) of this transistor are connected to the first power supply terminal 11. .

In FIGS. 2A and 2B, 21
Is an N-type semiconductor substrate, and 22 and 23 are the N-type substrate 21.
, A source region and a drain region of the PMOS transistor P0, which are P + -type impurity regions selectively formed in the surface layer portion, and 28 is a gate insulating film formed on the surface of the substrate region (channel region) between the source and drain. , 24 are gate electrodes formed on the gate insulating film 28. Two
5 is an N formed selectively on the surface layer of the N-type substrate 21.
It is a substrate bias application region consisting of + type impurity region,
The power supply potential VDD is applied. As shown in FIG. 2A, a PNP transistor 26 having the source region 22 as the collector, the drain region 23 as the emitter region, and the substrate as the base region is parasitically formed in the substrate. There is. Further, between the base region and the substrate bias applying region 25, the resistance component 2 of the substrate itself is provided.
There are seven. The parasitic PNP transistor 26
The emitter / collector of the source region 22 and the drain region 23 may be inverted depending on the potential relationship between the source region 22 and the drain region 23. As shown in FIG.
Is an emitter, the drain region 23 is a collector region, and the substrate 21 is a base region.
6 may be formed parasitically. In the IC of FIG. 1, the surge is applied to the second power supply terminal 12 and the third power supply terminal 13 in the following four cases. (A) When a negative surge voltage is applied to the second power supply terminal 12. (B) When a positive surge voltage is applied to the second power supply terminal 12. (C) When a negative surge voltage is applied to the third power supply terminal 13. (D) When a positive surge voltage is applied to the third power supply terminal 13.

First, the operation in the case of the above (a) will be described with reference to FIG. In this case, as the potential VSS1 of the second power supply terminal 12 decreases due to the application of the negative surge voltage, the potential of the source region 22 also decreases. On the other hand, the power source potential VDD is applied to the substrate 21 via the substrate bias application region 25. The breakdown voltage VB of the PN junction between the source region 22 and the substrate 21 is usually
It is 20 V to 30 V, and when the potential of the source region 22 exceeds the breakdown voltage VB with respect to the substrate potential, a breakdown current starts flowing from the substrate 21 toward the source region 22. As a result, the substrate potential starts to drop, and the substrate potential drops so as to approach the potential of the source region 22.
Then, when the substrate potential drops to a value lower than the forward voltage VF (normally about 0.7 V) of the PN junction between the drain region 23 and the substrate 21 with respect to the potential VSS2 of the drain region 23, the drain region A PN junction current starts flowing from 23 toward the substrate 21. This current becomes the base current of the parasitic PNP transistor 26, the transistor 26 is turned on, and the collector current icol flows.

Further, the potential VSS of the second power supply terminal 12
If the potential difference between the source region 22 and the drain region 23 exceeds the punch-through voltage of the PMOS transistor P0 (which largely depends on the channel length of the PMOS transistor P0, usually 10 V to 20 V) with the decrease of 1, the source region 22 The drain region 23 is short-circuited, and the patch through current ipan flows between both regions.

Next, the operation in the above case (b) will be described with reference to FIG. 2 (b). In this case, as the potential VSS1 of the second power supply terminal 12 rises due to the application of the positive surge voltage, the potential of the source region 22 with respect to the substrate potential is the forward voltage V of the PN junction between the source region 22 and the substrate 21.
When the voltage exceeds F (usually about 0.7 V), a PN junction current flows from the source region 22 toward the substrate 21, and the potential of the substrate 21 rises. At this time, when the substrate potential with respect to the potential of the gate electrode 24 exceeds the threshold voltage of the PMOS transistor P0, the transistor P0 is turned on and the channel current icha flows. When a PN junction current starts flowing from the source region 22 toward the substrate 21, this current becomes the base current of the parasitic PNP transistor 26, which turns on, which is the reverse of FIG. 2A. A collector current iccol flows in the direction.

In the case of the above (c), the above (a)
In the case of (d), the source region 22 and the drain region 23 are exchanged, and in the case of (d), the source region 22 and the drain region 2 are operated.
The operation in which 3 and 3 are replaced is performed.

As described above, when a negative or positive surge voltage is applied to the second power supply terminal 12 or the third power supply terminal 13, various currents icha, icol, ipan are applied between the source region and the drain region. Flows, and these surges can escape to the third power supply terminal 13 or the second power supply terminal 12.

That is, according to the IC of FIG. 1, the gate electrode 24 of the PMOS transistor P0 for power supply protection connected between the second power supply terminal 12 and the third power supply terminal 13
By applying the power supply potential VDD1 of the first power supply terminal 11 higher than the power supply potential VSS1 of the second power supply terminal 12 or the power supply potential VSS2 of the third power supply terminal 13, the second power supply terminal 12
The PMOS transistor P0 is not turned on in the normal operation due to the potential relationship between the second power supply terminal 13 and the third power supply terminal 13, that is, regardless of the potential difference between the second power supply terminal 12 and the third power supply terminal 13. A surge applied to one of the terminal 12 or the third power supply terminal 13 can escape from the other, and surge resistance can be improved.

Therefore, even when the power source potential of one of the two power source terminals is connected to a power source having a relatively high internal resistance provided outside the IC or on the same IC, the power source having a relatively high internal resistance is used. It is possible to increase the ability to absorb the surge applied to the connected power supply terminal,
It is possible to improve anti-surge characteristics such as latch-up resistance.

Further, even when the potential relationship between the power source terminal connected to the power source having a relatively high internal resistance and the power source terminal connected to the power source having a relatively low internal resistance is reversed,
A surge absorption path can be formed by the PMOS transistor P0 for power supply protection, and the surge can be dispersed and effectively absorbed. FIG. 3 shows a modification of the IC shown in FIG.

This IC is different from the circuit shown in FIG.
Similar to the conventional example, the first power supply terminal 11 and the third power supply terminal 13
And a PMOS transistor P3 and an NMOS transistor N3 are additionally connected in parallel with each other.

According to this IC, it becomes possible to release the surge applied to the third power supply terminal 13 to the two of the second power supply terminal 12 and the first power supply terminal 11, and further improve the surge withstand characteristic. It will be possible. FIG. 4 shows another modification of the IC of FIG.

This IC is different from the circuit shown in FIG.
Similar to the conventional example, the first power supply terminal 11 and the second power supply terminal 12
And a PMOS transistor P2 and an NMOS transistor N2 are additionally connected in parallel with each other.

According to this IC, the surge applied to the second power supply terminal 12 can be released to the two of the third power supply terminal 13 and the first power supply terminal 11, and the surge resistance can be further improved. It will be possible. FIG. 5 shows the second aspect of the present invention.
3 illustrates a power supply protection circuit for an IC according to an embodiment.

In this IC, the first power supply terminal 51 has a low power supply potential VSS (0 V in this example, ground potential GN).
D) is applied, and the ground potential GND is applied to the second power supply terminal 52.
The higher power supply potential VDD1 is applied, and the third power supply terminal 53 is applied with the power supply potential VDD2 higher than the ground potential GND. Each of the power supply terminals is, for example, an external connection terminal, and three types of independent power supply wirings 1 to 3 are laid out corresponding to the three types of independent power supply terminals.

The drain-source of the enhancement type NMOS transistor N0 is connected between the third power supply terminal 53 and the second power supply terminal 52, and the gate electrode and the substrate region of this transistor are connected to each other. It is connected to the first power supply terminal 51.

6A and 6B show N in FIG.
FIG. 11 is a cross-sectional view showing different specific structures when the MOS transistor N0 is realized by using the P well region of the semiconductor substrate.

In FIGS. 6A and 6B, 61
Is an N type semiconductor substrate, 62 is a P well region formed in the N type substrate, and 63 and 64 are the P well regions 62.
The drain region and the source region of the NMOS transistor N0 formed of the N + type impurity region selectively formed in the surface layer part of the gate insulating film 70 are formed on the surface of the substrate region (channel region) between the drain and the source. , 65 are gate electrodes formed on the gate insulating film. 66 is a P formed selectively on the surface of the P well region 62
This is a P-well bias application region made of a + type impurity region, to which the ground potential GND is applied. Reference numeral 67 denotes a substrate bias application region composed of an N + type impurity region selectively formed in the surface layer portion of the N type substrate 61, to which the power supply potential VDD2 is applied.

In the P-well region 62, as shown in FIG. 6A, the drain region 63 is the collector, the source region 64 is the emitter region, and the P-well region 62 is the base region. The transistor 68 is parasitically formed. Furthermore, P-well territory between the between the base region P-well bias region 66
There is a resistance component 69 that the area 62 itself has. The collector / emitter of the parasitic NPN transistor 68 is
The potential may be reversed depending on the potential relationship between the drain region 63 and the source region 64. As shown in FIG. 6B, the drain region 63 serves as an emitter, the source region 64 serves as a collector region, and a P well is formed. The NPN transistor 68 having the region 63 as a base region may be parasitically formed. In the IC of FIG. 5, the second power supply terminal 52
The surge is applied to the third power supply terminal 53 in the following four cases. (E) When a negative surge voltage is applied to the second power supply terminal 52. (F) When a positive surge voltage is applied to the second power supply terminal 52. (G) When a negative surge voltage is applied to the third power supply terminal 53. (H) When a positive surge voltage is applied to the third power supply terminal 53.

First, the operation in the above case (e) will be described with reference to FIG. 6 (a). In this case, as the potential VDD1 of the second power supply terminal 52 decreases due to the application of the negative surge voltage, the potential of the source region 64 also decreases. When the potential of the source region 64 decreases to a value lower than the forward voltage VF of the PN junction between the P well region 62 and the source region 64 with respect to the potential of the P well region 62, the potential of the source region 64 shifts from the P well region 62 to the source region 64. As a result, a PN junction current flows and the potential of the P well region 62 decreases. At this time, the gate electrode 65
When the potential of the P well region 62 exceeds the threshold voltage of the NMOS transistor N0 with respect to the potential of, the transistor N0 is turned on and the channel current icha flows.
Also, when a PN junction current starts flowing from the P well region 62 toward the source region 64, this current causes a parasitic NPN.
It becomes the base current of the transistor 68, the transistor 68 is turned on, and the collector current icol flows.

Next, the operation in the case of the above (f) will be described with reference to FIG. 6 (b). In this case, as the potential VDD1 of the second power supply terminal 52 rises due to the application of the positive surge voltage, the potential of the source region 64 with respect to the potential of the P well region 62 is PN between the P well region 62 and the source region 64. When the breakdown voltage VB of the junction is exceeded, a breakdown current starts flowing from the source region 64 toward the P well region 62. As a result, the potential of the P well region 62 starts to rise, and the potential of the P well region 62 rises so as to approach the potential of the source region 64. When the potential of the P well region 62 exceeds the forward potential VF of the PN junction between the P well region 62 and the drain region 63 with respect to the potential VDD2 of the drain region 63, the potential of the P well region 62 moves toward the drain region 63. The PN junction current begins to flow. This current becomes the base current of the parasitic NPN transistor 68, the transistor 68 is turned on, and the collector current icol in the opposite direction to that of FIG. 6A flows.

Further, the potential VDD of the second power supply terminal 52
With the first rising, and the potential difference between the drain region and the source region exceeds a punch-through voltage of the NMOS transistors N0, short-circuited between the drain region and source region, flows pan Chisuru current ipan between both regions.

In the case of the above (g), the above (e)
In the case of (h), the drain region 63 and the source region 64 are replaced with each other, and in the case of (h), the drain region 63 and the source region 6 in the case of (f) are operated.
The operation in which 4 and 4 are replaced is performed.

As described above, when a negative or positive surge voltage is applied to the second power supply terminal 52 or the third power supply terminal 53, various currents icha, icol, ipan are applied between the drain region and the source region. Flow, and these currents allow the surge to escape to the third power supply terminal 53 or the second power supply terminal 52.

That is, the protection NMOS transistor N0 shown in FIG. 5 has the first power supply potential VDD1 of the second power supply terminal 52 or the power supply potential VDD2 of the third power supply terminal 53 lower than the first power supply potential VDD1.
By applying the ground potential GND of the power supply terminal 51 to the gate electrode, the NMOS transistor N0 does not turn on during normal operation due to the potential relationship between the second power supply terminal 52 and the third power supply terminal 53, that is, Irrespective of the potential difference between the second power supply terminal 52 and the third power supply terminal 53,
A surge applied to one of the power supply terminal 52 or the third power supply terminal 53 can be released from the other, and surge resistance can be improved. FIG. 7 shows the IC of FIG.
Shows a modified example of.

This IC is different from the IC shown in FIG.
Between the first power supply terminal 51 and the third power supply terminal 53, the PMO
The difference is that the S transistor P3 and the NMOS transistor N3 are additionally connected in parallel with each other.

According to this IC, the surge applied to the third power supply terminal 53 can be released to the two of the second power supply terminal 52 and the first power supply terminal 51, and the surge withstand characteristic can be further improved. It will be possible. FIG. 8 shows another modification of the IC of FIG.

Compared with the IC shown in FIG. 7, this IC is
Between the first power supply terminal 51 and the second power supply terminal 52, the PMO
The difference is that the S transistor P6 and the NMOS transistor N6 are additionally connected in parallel with each other.

According to this IC, the surge applied to the second power supply terminal 52 can be released to the two of the third power supply terminal 53 and the first power supply terminal 51, and the surge withstand characteristic can be further improved. It will be possible. FIG. 9 shows another modification of the IC of FIG.

This IC is different from the IC shown in FIG.
A fourth power supply terminal (external connection terminal) 54 to which a power supply potential VDD3 higher than the GND potential is applied is added, and the drain of the enhancement type NMOS transistor 60 is provided between the third power supply terminal 53 and the second power supply terminal 52. -The source is additionally connected, and the fourth power terminal 54 and the second power terminal 52 are connected.
Enhancement type NMOS transistor 6 between
The difference is that the drain and source of 1 are additionally connected. In the gate / substrate region of the transistor 60 and the gate / substrate region of the transistor 61, the second power supply terminal 52, the third power supply terminal 53, or the fourth power supply terminal 5 is provided.
Ground potential GN of the first power supply terminal 51 lower than the power supply potential of 4
D is applied.

According to this IC, any one of the NMOS transistors N0, 60, 61 for power supply protection during normal operation depends on the potential relationship among the second power supply terminal 52, the third power supply terminal 53 and the fourth power supply terminal 54. It is never turned on, that is, the second power supply terminal 52, the third power supply terminal 53, and the fourth power supply terminal 53.
Irrespective of the potential difference with the power supply terminal 54, the second power supply terminal 52
Alternatively, the surge applied to any one of the third power supply terminal 53 and the fourth power supply terminal 54 can be released and the surge resistance can be improved. FIG. 10 shows a further modification of the IC of FIG.

This IC is different from the IC shown in FIG.
A PMOS is provided between the fourth power supply terminal 54 and the first power supply terminal 51.
A transistor 62 and an NMOS transistor 63 are additionally connected in parallel with each other, and a PMOS transistor 64 and an NM are provided between the third power supply terminal 53 and the first power supply terminal 51.
The difference is that the OS transistors 65 are additionally connected in parallel with each other, and the PMOS transistor 66 and the NMOS transistor 67 are additionally connected in parallel with each other between the second power supply terminal 52 and the first power supply terminal 51.

According to this IC, the surge applied to the first power supply terminal 51 is applied to the second power supply terminal 52 and the third power supply terminal 53.
And it becomes possible to escape to three of the 4th power supply terminals 54, and it becomes possible to further improve anti-surge characteristics. .
FIG. 11 shows a power supply protection circuit for an IC according to the third embodiment of the present invention.

Compared to the IC shown in FIG. 1, this IC absorbs a surge input from the input / output terminal (external connection terminal) 71 in the power supply terminal and is resistant to the surge from the input / output terminal 71. The difference is that the latch-up characteristics are improved.

That is, the input / output terminal 71 and the first power supply terminal 11
PMO with gate and drain connected to each other
The S transistor P1 is inserted, and the input / output terminal 71 and the third
An NMOS transistor N1 whose drain and gate are connected to each other is inserted between the power supply terminal 13 and the power supply terminal 13. The input / output terminal 71 is connected to the internal circuit via the resistance element 72. The first power supply terminal 11 and the second power supply terminal 12 are supplied with power supply potentials VDD and VSS1 from an ordinary external power supply having a low internal resistance, and the third power supply terminal 1
3 is a power supply potential VSS2 from a power supply (step-up power supply circuit or step-down power supply circuit) having a higher internal resistance than the normal external power supply.
Is being supplied.

In the IC of FIG. 11, the input / output terminal 71
When a large current surge is applied to the
The S transistor P1 and the NMOS transistor N1 are turned on as parasitic bipolar transistors, and the surge is absorbed by the first power supply terminal 11 and the third power supply terminal 13. At this time, the lower the electrical resistance value of the surge absorption path and the more the surge absorption paths are, the more efficiently the overcurrent due to the surge can be absorbed, so that the latch-up occurrence rate can be suppressed to a low level.

In the case of the third embodiment, the first power supply terminal 11
The surge absorbed in the IC is released to the outside of the IC.
Since a power supply with a high internal resistance is connected to the power supply terminal 13, the release of overcurrent from the third power supply terminal 13 is extremely small. Therefore, most of the above surges are generated by the third power supply terminal 13
Is discharged from the second power supply terminal 12 to the outside of the IC through the PMOS transistor P0 which is turned on by the surge that has flown into the IC. Further, similarly to the conventional example, the PMOS transistor P3 and the NMOS transistor N3 are additionally connected in parallel between the first power supply terminal 11 and the third power supply terminal 13, so that they flow into the input / output terminal 71. PM through surge through NMOS transistor N1
OS transistor P3 and NMOS transistor N3
It is possible to release the power from the first power supply terminal to the outside of the IC via the.

In the IC of FIG. 11, I of FIG.
Similar to C, if the power supply potential VSS1 and the power supply potential VSS2 are lower than the power supply potential VDD, the potential relationship between the second power supply terminal 12 and the third power supply terminal 13 can be set arbitrarily. Figure 12
9 shows a power supply protection circuit for an IC according to a fourth embodiment of the present invention.

This IC is the same as the IC shown in FIG.
From the booster power supply circuit 81 formed on the IC chip 80
3 shows an example in which the power supply potential VDD2 is supplied to the three power supply terminals 53 , and a pair of external connection terminals F of the booster power supply circuit 81.
A boosting capacitor C1 connected between the first power supply terminal 51 and the second power supply terminal F2 is provided outside the IC chip.
A storage capacitor C2 connected between the two is provided outside the IC chip.

The boosting power supply circuit 81 includes the second power supply terminal 5
2 and the first power supply terminal 51 are connected in series with each other,
A PMOS transistor P1 having a source / substrate region connected to each other and an NMO having a substrate region / source connected to each other
The S transistor N1 and the transistors P1 and N
First external connection terminal F1 connected to the serial connection point of No. 1
A PMOS transistor P3 connected in series between the third power supply terminal 53 and the second power supply terminal 52 and having source / substrate regions connected to each other, and a PMOS transistor P2 having source / substrate regions connected to each other; A second external connection terminal F2 connected to the series connection point of the transistors P3 and P2, and the transistors P1 and N1.
And a wiring 82 for supplying the boosting clock signal CLK to the respective gates of P3 and P3, and the boosting clock signal CL.
An inverter circuit 83 for inverting K and supplying an inverted clock signal / CLK to the gate of the PMOS transistor P2.

Next, the operation in the state where the boosting capacitor C1 is connected to the boosting power source circuit 81 will be described. When the boosting clock signal CLK is at "H" level (potential VDD1), the transistors P2 and N1 are turned on, the transistors P1 and P3 are turned off, and the potential of the first external connection terminal F1 is GND. , The boosting capacitor C1 is charged so that the potential of the second external connection terminal F2 becomes VDD1.

On the other hand, the boosting clock signal CLK
Goes to "L" level (potential GND), the transistors P2 and N1 are turned off, the transistors P1 and P3 are turned on, and the potential of the first external connection terminal F1 becomes VDD1 and the second The potential of the external connection terminal F2 becomes 2 × VDD1 (boosted voltage) due to capacitive coupling of the boosting capacitor C1, and this boosted voltage is output to the third power supply terminal 53 via the transistor P3.

By repeating the above-described operation in which the boosting clock signal CLK changes in a pulse shape, the boosting operation as described above is repeated, and the boosted voltage is continuously and stably supplied to the storage capacitor C2. Therefore, in the normal operating state, only the output voltage from the boosting power supply circuit 81 is supplied to the third power supply terminal 53. In this state, the power supply protection transistor N0 is always in the off state and has no influence on the boosting operation as described above.

The third power supply terminal 53 and the second power supply terminal 5
2 has a transistor P3 as a surge absorption path, but since the current supply capacity (charge capacity for the boosting capacitor C1) of this transistor P3 is determined on the assumption of a normal operating state, it absorbs the surge. It does not have enough ability (transistor size) to do so. Also,
Between the transistor P3 and the second power supply terminal 52 is present the transistor P2, the third power supply terminal 53 and the resistance value of the surge absorption path rather high between the second power supply terminal 52, moreover, for the boost Since the capacitor C1 has only a small capacity necessary for the boosting operation and the boosted voltage holding operation, the surge absorbing capability when the surge is applied to the third power supply terminal 53 is low.

However, in this embodiment, the second embodiment,
Since the power supply protection transistor N0 similar to that of the third embodiment is provided, when a large current surge is applied to the third power supply terminal 53, the power supply protection transistor N0 is turned on, and most of the surge is generated. It is promptly discharged from the third power supply terminal 53 to the power supply outside the IC via the second power supply terminal 52.
In other words, it is possible to improve surge resistance characteristics such as latch-up resistance even when a power supply having a relatively high internal resistance is supplied to the power supply terminal like the boosting power supply circuit 81.

In each of the above embodiments, MOS transistors were used as the power protection transistors P0 and N0, but instead of this, a diode having a structure in which the gate electrode of the MOS transistor of the above embodiments is omitted may be used. You may change to.

The IC thus modified has a first power supply terminal formed on a semiconductor substrate and supplied with a predetermined power supply potential, and a first power supply terminal formed on the semiconductor substrate and more than the first power supply terminal, respectively. A second power supply terminal and a third power supply terminal to which a low-potential or high-potential power supply potential is supplied, and the second power supply terminal and the third power supply terminal which are formed in the semiconductor substrate or a well region in the semiconductor substrate, respectively. comprising an impurity region of opposite conductivity type to the semiconductor substrate or the well region Ru is connected correspondingly, that the first power supply terminal on the semiconductor substrate or the well region impurity region is formed is connected Is characterized by.

[0071]

As described above, according to the IC of the present invention,
Even when the power supply terminal connected to a power supply with a relatively high internal resistance and the power supply terminal connected to a power supply with a relatively low internal resistance are used by reversing the potential relationship, the power supply is protected between the two power supply terminals. it is possible to connect the device, enhance the ability to absorb the applied surge to the power supply terminal to which the internal resistance is connected to a relatively high power, Ru FIG improved surge resistance characteristics of resistance latchup etc. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a power supply protection circuit for an IC according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a different specific structure of the PMOS transistor in FIG.

FIG. 3 is a circuit diagram showing a modified example of the IC shown in FIG.

FIG. 4 is a circuit diagram showing another modification of the IC shown in FIG.

FIG. 5 is a circuit diagram showing an IC power supply protection circuit according to a second embodiment of the present invention.

6 is a cross-sectional view showing a different specific structure of the NMOS transistor in FIG.

7 is a circuit diagram showing a modified example of the IC of FIG.

FIG. 8 is a circuit diagram showing another modification of the IC shown in FIG.

9 is a circuit diagram showing a further modified example of the IC of FIG.

FIG. 10 is a circuit diagram showing still another modification of the IC shown in FIG.

FIG. 11 is a circuit diagram showing a power supply protection circuit for an IC according to a third embodiment of the present invention.

FIG. 12 is a circuit diagram showing a power supply protection circuit for an IC according to a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a different example of a conventional IC power protection circuit.

[Explanation of symbols]

11, 51 ... First power supply terminal, 12, 52 ... Second power supply terminal, 13, 53 ... Third power supply terminal, 54 ... Fourth power supply terminal,
P0, N0 ... MOS transistors for power supply protection, 81 ... Boost power supply circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyuki Mogi Inventor Hiroyuki Mogi 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Association In-house (56) Reference JP-A-63-301558 (JP, A) JP Heihei 3-234063 (JP, A) JP 3-206666 (JP, A) JP 1-278771 (JP, A) JP 1-148019 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/00 H01L 27/00 H03K 17/00

Claims (6)

(57) [Claims] 1. A first power supply terminal formed on a semiconductor substrate to which a predetermined power supply potential is supplied, and a power supply potential formed on the semiconductor substrate and having a potential lower or higher than that of the first power supply terminal. And a second power supply terminal that is formed on the semiconductor substrate and has a potential lower or higher than that of the first power supply terminal and that is different from the power supply potential supplied to the second power supply terminal. A third power supply terminal, to which a power supply potential is supplied, is formed on the semiconductor substrate, the source and drain are connected between the second power supply terminal and the third power supply terminal, and the gate and the substrate region are the first power supply. A power supply MOS transistor connected to the terminal, wherein the power supply potential supplied to the second and third power supply terminals is
Both the power supply potential supplied to the first power supply terminal is low
Power source or a high potential, and connecting a power source for supplying a power source potential to the second and third power source terminals.
Change the connection or the power supplied to the second power supply terminal.
The potential obtained by boosting the source potential is supplied to the third power supply terminal.
Supply, the power supplied to the second and third power supply terminals.
A semiconductor integrated circuit characterized by being used by reversing the potential relationship of source potentials . 2. The semiconductor integrated circuit according to claim 1, wherein a power supply potential lower than that of the first power supply terminal is supplied to the second power supply terminal and the third power supply terminal, and the MOS transistor is a PMOS transistor. A semiconductor integrated circuit characterized by the above. 3. The semiconductor integrated circuit according to claim 1, wherein a power supply potential higher than that of the first power supply terminal is supplied to the second power supply terminal and the third power supply terminal, and the MOS transistor is an NMOS transistor. A semiconductor integrated circuit characterized by the above. 4. The semiconductor integrated circuit according to claim 1, wherein an internal resistance of a power supply that supplies a power supply potential to the second power supply terminal and a power supply potential to the third power supply terminal. A semiconductor integrated circuit characterized by being different from the internal resistance of a power supply. 5. The semiconductor integrated circuit according to claim 4, wherein a power supply for supplying a power supply potential to the second power supply terminal and a power supply for supplying a power supply potential to the third power supply terminal is provided.
A semiconductor integrated circuit characterized in that the power supply with the higher internal resistance is a step-up power supply circuit or a step-down power supply circuit. 6. A first power supply terminal formed on a semiconductor substrate and supplied with a predetermined power supply potential, and a power supply potential formed on the semiconductor substrate and having a lower potential or a higher potential than that of the first power supply terminal. And a second power supply terminal that is formed on the semiconductor substrate and has a potential lower or higher than that of the first power supply terminal and that is different from the power supply potential supplied to the second power supply terminal. A third power supply terminal to which a power supply potential is supplied, and a semiconductor substrate or a well region in the semiconductor substrate, which is connected to the second power supply terminal and the third power supply terminal, respectively, and is connected to the semiconductor substrate or the well. the region includes an impurity region of opposite conductivity type, and said first power supply terminal on the semiconductor substrate or the well region impurity region is formed is connected to the second, third power source terminal Power supply potential is supplied, said
Both the power supply potential supplied to the first power supply terminal is low
Power source or a high potential, and connecting a power source for supplying a power source potential to the second and third power source terminals.
Change the connection or the power supplied to the second power supply terminal.
The potential obtained by boosting the source potential is supplied to the third power supply terminal.
Supply, the power supplied to the second and third power supply terminals.
A semiconductor integrated circuit characterized by being used by reversing the potential relationship of source potentials .