JPH0228362A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the potential of a power source or a ground and to prevent the breakdown of a MOS transistor by providing overvoltage absorbing circuits between each power source and grounding line being solated from each other. CONSTITUTION:As overvoltage absorbing circus, a MOS transistor 6 whose gate is connected to a line L2 and a PMOS transistor 7 whose gate is connected to a line L4 are provided between the line L2 (GND1) and the line L4 (GND2). Also, as overvoltage absorbing circuits, an NMOS transistor 8 whose gate is connected to a line L1 and an NMOS transistor 9 whose gate is connected to a line L3 are provided between the line L1 (VDD1) and the line L3 (VDD2). Most of the charge which flowed into GND 1 from an input terminal 5 flow further to GND2, and even in the case that high voltage of several kV with regard to GND or any power source is applied to the input terminal 5, voltage above the gate oxide film breakdown voltage is never applied to the gate electrode of an initial stage circuit 3. Hereby, the charge is never accumulated excessively, and breakdown of the oxide film can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having a plurality of paths (wirings and terminals) for supplying operating voltage to a plurality of MOS transistors formed on a semiconductor substrate. , relates to a semiconductor integrated circuit device that is provided separately.

[Conventional technology]

FIG. 2 is a circuit diagram of a conventional example in which the first stage circuit connected to the input terminal and the power supply and ground of the internal circuit are separated.

This conventional example uses operating voltage supply paths (hereinafter simply referred to as lines) Ll and L2 that supply a power supply voltage VDDI and a ground voltage GND1 to the first stage circuit 3, respectively, and a power supply voltage VDD2 and a ground voltage GND2 to an internal circuit 4, respectively. It is equipped with supply lines L3 and L4. Also, input terminals (e.g. external connection terminals, pads).

A lead pin etc.) 5 is connected to the gate of the first stage circuit 3, and a PMO 3) transistor 1 and an NMOS) transistor 2 are provided as an input protection circuit.

The reason why lines Ll and L3 and lines L2 and L4 are separated is to prevent fluctuations in the power supply voltage and ground voltage caused by the internal circuit 4 from being transmitted to the first stage circuit 3 and to prevent the input voltage margin of this first stage circuit 3 from deteriorating. It's for a reason. In addition, PMOS transistor 1 configuring the input protection circuit. N.M.O.
S) The transistor 2 becomes conductive when a high voltage (overvoltage) such as static electricity is applied and exceeds the reverse withstand voltage of each transistor, and the transistor 2 is connected to the power supply VDDI through the lines Ll and L2.
This is to prevent the gate oxide film of the first stage circuit 3 from being destroyed by dissipating the surge to the ground voltage GNDI.

[Problem to be solved by the invention]

Since the static electricity applied to the input terminal 5 is extremely large, the PMOS transistor 1 or NMOS transistor 2 that constitutes the input protection circuit becomes conductive, and the lines Ll and L2 become conductive.
In some cases, the protection of the first stage circuit 3 is not sufficient just by releasing the charge. That is, ray L 1 (VDDI)
t is L 2 (GNDI), and if a large amount of static electricity or other charges that have flowed into the circuit accumulate, the surge bypass (surge absorption) ability will weaken, and in this case, the gate oxide film of the first stage circuit 3 will be destroyed. , and the line Ll (V
The charge accumulated in DDI) or L2 (GNDI) is
For example, by destroying the insulating film formed on the semiconductor substrate (not shown) I:,
L4 (GND2) may flow in.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a first circuit whose input terminal is connected to an external connection terminal, and a first circuit and a first circuit for supplying a high-level operating voltage and a low-level operating voltage to the first circuit, respectively. a second voltage supply path; and a second circuit.

third and fourth voltage supply paths for respectively supplying a high level operating voltage and a low level operating voltage to the second circuit are formed on the same semiconductor substrate, the first and third voltage supply paths; The second and fourth voltage supply paths are provided between the first and third voltage supply paths and between the second and fourth voltage supply paths in a semiconductor integrated circuit device that is provided independently. The present invention is characterized in that an overvoltage absorption circuit is provided between the respective voltage supply paths, which conducts when an overvoltage is applied between the respective voltage supply paths and absorbs the overvoltage.

[Effect]

By operating the overvoltage absorption circuit provided between the power supply voltage supply path and the ground voltage supply path, charges such as static electricity and noise are quickly transferred, thereby rapidly stabilizing the power supply potential or ground potential. At the same time, it is possible to prevent destruction of the MOS transistors constituting the input stage circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The difference between this embodiment and the conventional example is that line L2 (OND
I) and line L4 (GNI12) as an overvoltage absorption circuit, an NMOS whose gate is connected to line L2
Transistor 6, PM with gate connected to line L4
An NMOS transistor 8 whose gate is connected to the line L3 serves as an overvoltage absorption circuit between the O3 transistor 7 and the life L1 (VDDI) to the line L3 (VDD2).
The point is that an NMOS transistor 9 connected to is provided. All of these MOS transistors are
It becomes conductive when a voltage of +15V or more is applied to the gate.

Next, the operation of this embodiment will be explained.

For example, consider a case where high voltage static electricity of several kV is applied to the input terminal 5. In this case, for example, due to punch-through between the source electrode and drain electrode of the NMOS transistor 2, charges flow to GNDI (line L2) below the gate oxide film breakdown voltage, and the potential of GN[l1 increases. The NMOS transistor 6 connected between GNDI and GND2 becomes conductive when the GNDI (7) voltage increases by 15V or more, and much of the charge that has flowed from the input terminal 5 to GND1 further flows to GND2. As a result, even if a high voltage of several kV is applied to the input terminal 5 with reference to any power supply or GND, the gate electrode of the first stage circuit 3 will not have a voltage higher than the gate oxide film breakdown voltage. Since no more damage is applied, destruction of the gate oxide film can be prevented. Also, NM
GND2 is also connected by the punch-through of OS transistor 7.
charge can be released to the

NMO3) Regarding transistor 8.9, the above-mentioned NMO
It is clear that it has a similar f@ to S transistor 6.7, and also NMO3) transistor, 7,8.9
In this embodiment, the threshold voltage is set to 15V, but it goes without saying that this can be changed by changing the manufacturing process to change the capability depending on the purpose.

〔Effect of the invention〕

As explained above, the present invention provides one separate power supply,
By providing an overvoltage absorption circuit during the grounding life, it is possible to stabilize the potential of the power supply or the ground, and there is an effect that it is possible to prevent destruction of the MOS transistor due to static electricity, noise, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of a semiconductor integrated circuit device of the present invention, and FIG. 2 is a circuit configuration diagram of a conventional example. l...PMOS transistor (input protection circuit), 2.
...NMO3) transistor (input protection circuit). 3... First stage circuit, 4... Internal circuit, 5... Input terminal, VDDI, VDD2... Power supply voltage (high level operating voltage), GNDI, GND2... Ground voltage (low level operating voltage) , Ll-L4... Voltage supply path (line)
.

Claims (1)

[Claims] 1. A first circuit whose input end is connected to an external connection terminal, and first and second circuits for supplying a high-level operating voltage and a low-level operating voltage to the first circuit, respectively. A second voltage supply path, a second circuit, and third and fourth voltage supply paths for respectively supplying a high-level operating voltage and a low-level operating voltage to the second circuit are formed on the same semiconductor substrate. In the semiconductor integrated circuit device, the first and third voltage supply paths and the second and fourth voltage supply paths are provided independently, respectively; and between the second and fourth voltage supply paths, an overvoltage absorption circuit is provided which conducts when an overvoltage is applied between the respective voltage supply paths and absorbs the overvoltage. Semiconductor integrated circuit device.