JPH0494568A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0494568A JPH0494568A JP2211979A JP21197990A JPH0494568A JP H0494568 A JPH0494568 A JP H0494568A JP 2211979 A JP2211979 A JP 2211979A JP 21197990 A JP21197990 A JP 21197990A JP H0494568 A JPH0494568 A JP H0494568A
- Authority
- JP
- Japan
- Prior art keywords
- line
- circuit
- output
- terminal
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 230000005611 electricity Effects 0.000 claims abstract description 11
- 230000003068 static effect Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 abstract description 11
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 7
- 230000006378 damage Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 2
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 2
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に半導体基板上
に形成された複数のＭｏＳトランジスタに電源電圧を供
給する電源ラインが複数設けられ、しかもこれらが半導
体基板上で分離されている半導体累積回路装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, a plurality of power supply lines are provided for supplying power supply voltage to a plurality of MoS transistors formed on a semiconductor substrate. The present invention relates to a semiconductor cumulative circuit device in which circuits are separated on a semiconductor substrate.
従来の半導体集積回路装置においては、複数の出力回路
が同じ電源ライン又は接地（ＧＮＤ）ライン（ここでは
、これらをまとめて電源ラインという）に接続されてい
る場合、これら複数の出力回路が動作すると、電源ライ
ンのインピーダンスによるノイズ又は、浮き落ちによっ
て出力波形にリンギングが生じ１回路特性を低下させる
。このために、半導体集積回路装置に電源電圧を供給す
る電源ラインを複数設け、しかもこれらを半導体基板上
に互いに分離し、電源ラインに接続される出力回路の数
を回路特性に影響を与えないようにしである。In conventional semiconductor integrated circuit devices, when multiple output circuits are connected to the same power supply line or ground (GND) line (hereinafter collectively referred to as power supply line), when these multiple output circuits operate, Ringing occurs in the output waveform due to noise or floating due to the impedance of the power supply line, deteriorating the characteristics of one circuit. For this purpose, multiple power lines are provided to supply power voltage to the semiconductor integrated circuit device, and these lines are separated from each other on the semiconductor substrate, and the number of output circuits connected to the power line is controlled so as not to affect the circuit characteristics. It's Nishide.
第２図はこのような複数の出力口ｎの電源ライフ３分離
した回路図を示す、第２図において、出力回蹄１．２．
出力回路群３は第１の電源ラインを精成するＶＤＤ１ラ
イン５とＧＮＤ１ライン４とに接続され、それぞれ出力
端子６．７から出力波形が出る。出力回路群３は複数の
出力回路から構成されていて、その数は回路特性上の問
題から決まってくる。FIG. 2 shows a circuit diagram of a plurality of output ports n with three separate power supply lives.
The output circuit group 3 is connected to a VDD1 line 5 and a GND1 line 4 that refine the first power supply line, and output waveforms are output from output terminals 6.7, respectively. The output circuit group 3 is composed of a plurality of output circuits, the number of which is determined based on circuit characteristics.
第２図において、同一半導体基板上に、ＧＮＤ１ライン
４．ＶＤＤＩライン５と、ＧＮＤ２ラインｌｌ、ＶＤＤ
２ライン１２とがあり、ライン４．５間に、出力回路１
，２．圧力回路群３゜内部回路１９が接続され、ライン
１１．１２間には、出力回路８，９．出力回路群１０．
内部回路２０が接続されている。出力回路１，２，８゜
９は、それぞれ２個のＭＯＳ）ランジスタの直列体から
なり、内部回路からの出力信号線１５゜１６．１７．１
８がそれぞれのゲートに印加され、その出力は外部出力
端子６．７．８．９にそれぞれ印加される。In FIG. 2, GND1 line 4. VDDI line 5, GND2 line ll, VDD
There are two lines 12 and 12, and between lines 4 and 5, output circuit 1
,2. Pressure circuit group 3° internal circuit 19 is connected, and output circuits 8, 9 . Output circuit group 10.
An internal circuit 20 is connected. Output circuits 1, 2, 8゜9 each consist of two MOS) transistors in series, and output signal lines 15゜16, 17.1 from the internal circuits.
8 is applied to their respective gates, and their outputs are applied to external output terminals 6.7.8.9, respectively.
今、出力回路群３の数が少なく、回路特性上問題ないと
きの波形図が第３図である。この場合、出力回路１．２
．３が同時に“０”を出力したときの出力回路１の波形
とＧＮＤとは、電源ラインやパラゲージのリードなどの
インピーダンスにより、出力波形２１やＧＮＤ １ライ
ンの波形２２のように振れ、またＶＤＤＩライン５の波
形２３のように振れるが、回路特性上問題はない、しか
し出力回路群の数が多い場合、第４図に示すように、Ｖ
ＤＤＩライン５の波形２６．出力波形２４及びＧＮＤ１
ライン４の波形２５はいずれも大きく振れ１時刻ｔ１に
おいて出力波形２４を“１”と判断してしまい、誤動作
を起こす。FIG. 3 is a waveform diagram when the number of output circuit groups 3 is small and there is no problem in terms of circuit characteristics. In this case, output circuit 1.2
．． The waveform of output circuit 1 and GND when 3 outputs "0" at the same time will fluctuate as shown in output waveform 21 and waveform 22 of GND 1 line due to the impedance of the power supply line, para gauge lead, etc. The waveform 23 in Figure 5 shows no problem in terms of circuit characteristics.However, when there are many output circuit groups, as shown in Figure 4, V
DDI line 5 waveform 26. Output waveform 24 and GND1
The waveforms 25 on line 4 all have a large swing, and at time t1, the output waveform 24 is determined to be "1", causing a malfunction.
このため、出力回路８．９及び圧力回路群１０は、ＶＤ
Ｄ２ライン１１とＧＮＤ２ライン１２とに分けて接続さ
れている。Therefore, the output circuit 8.9 and the pressure circuit group 10 are connected to the VD
The D2 line 11 and the GND2 line 12 are connected separately.
また、それぞれの出力回路の電流を流す能力は回路特性
上によりその最少値は決まる。Further, the minimum value of the current flowing ability of each output circuit is determined by the circuit characteristics.
しかしながら、前述した従来の回路では、二つの外部出
力端子１３．６の間に静電気が印加された場合、を荷を
放電することができず、ＧＮＤ２ライン１１及びＶＤＤ
２ライン１２に接続さている出力口Ｒ８，９及び内部回
路Ｂ２０を構成するＭＯＳ）ランジスタのゲート酸化膜
破壊を引き起こしてしまうという欠点があった。However, in the conventional circuit described above, when static electricity is applied between the two external output terminals 13.6, the load cannot be discharged, and the GND2 line 11 and VDD
This has the drawback of causing damage to the gate oxide film of the output ports R8 and R9 connected to the second line 12 and the MOS transistors constituting the internal circuit B20.
本発明は、かかる問題点に鑑みてなされたものであって
、出力端子間に入力されたノイズ又は静電気と吸収して
信頼性の優れた半導体集積回路装置を提供することにあ
る。The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor integrated circuit device that absorbs noise or static electricity input between output terminals and has excellent reliability.
本発明の半導体集積回路装置の構成は、半導体基板上に
、第１の電源ラインが接続された第１の出力回路と、第
２の電源ラインが接続された第２の出力回路とを備え、
前記第１又は第２の出力回路の出力端子に印加されるノ
イズ又はＷ９電気を吸収する保護回路が、前記第１．第
２の電源ライン間に設けられていることを特徴とする。The configuration of the semiconductor integrated circuit device of the present invention includes, on a semiconductor substrate, a first output circuit connected to a first power line and a second output circuit connected to a second power line,
A protection circuit that absorbs noise or W9 electricity applied to the output terminal of the first or second output circuit is configured to absorb noise or W9 electricity applied to the output terminal of the first or second output circuit. It is characterized in that it is provided between the second power supply lines.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の半導体集積回路装置を示す
回路図である。なお第１図において、第２図と同一部分
には同一符号を付して、重複する部分の説明を省略する
０本実施例では、互いに分離された異なる電源ライン問
に、保護回路３０を構成するＮチャネルＭＯＳ）ランジ
スタＴｒｌが接続されている。このＮチャネルＭＯＳト
ランジスタＴｒｌは、ゲートとドレインをＧＮＤ２ライ
ン１１に接続し、ソースをＧＮＤ１ライン４に接続した
もので、外部出力端子１３からＭＯＳ）ランジスタＴｒ
６のソースとトレイン間の耐圧を越える電圧が加わると
、ＭＯＳ）−ランジスタＴｒ６が導通し、ＧＮＤ２ライ
ン１１の電位が上昇し始める。この電位が＋１５Ｖ以上
になると、ＮチャネルＭＯＳ）ランジスタＴｒｌが導通
し、ＧＮＤ１ライン４の電位が上昇する。この電位がＭ
ＯＳトランジスタＴ ｒ ２のソースとドレイン間の耐
圧を越える電位以上になると、ＭＯＳ）ランジスタＴ
ｒ ２は導通する。以下パンチスルーと称する。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, the same parts as in FIG. 2 are given the same reference numerals, and explanations of overlapping parts are omitted. In this embodiment, the protection circuit 30 is configured between different power lines separated from each other. An N-channel MOS) transistor Trl is connected. This N-channel MOS transistor Trl has its gate and drain connected to the GND2 line 11 and its source connected to the GND1 line 4, and connects the external output terminal 13 to the MOS) transistor Trl.
When a voltage exceeding the breakdown voltage between the source and the train of GND2 is applied, the MOS transistor Tr6 becomes conductive and the potential of the GND2 line 11 begins to rise. When this potential becomes +15V or more, the N-channel MOS transistor Trl becomes conductive, and the potential of the GND1 line 4 rises. This potential is M
When the potential exceeds the breakdown voltage between the source and drain of the OS transistor T r 2, the MOS transistor T
r2 is conductive. Hereinafter, this will be referred to as punch-through.
なお、このＭＯＳ）ランジスタＴｒｌは、半導体基板上
に構成されているその他のＭＯＳトランジスタ群の第１
スレツシユホールド電圧より高い第２スレツシユホール
ド電圧を持つ。Note that this MOS transistor Trl is the first transistor of other MOS transistor groups configured on the semiconductor substrate.
It has a second threshold voltage higher than the threshold voltage.
以上のような構成をもつＣＭＯ３回路において、いま数
ＫＶの高電圧のノイズ又はｎ！気が外部出力端子６と接
地として、外部出力端子１３に加わると、ＧＮＤ２ライ
ン１１とＧＮＤＩライン４との間に接続されたＭＯＳト
ランジスタＴ ｒ １が、ＭＯＳトランジスタＴｒ６と
ＭＯＳトランジスタＴｒ２を通して導通し、外部出力端
子６へとｔ流が流れるようにすることができる。これに
よって、外部端子１３へ数ＫＶの高電圧が加わったとし
ても、ＧＮＤ２ライン１１とＶＤＤ２ライン１２とに接
続されている出力回路８，９，１０゜及び内部回路２０
を構成するＭＯＳ）ランジスタのゲート酸化膜の破壊を
防止することができる。In the CMO3 circuit with the above configuration, high voltage noise of several KV or n! When air is applied to the external output terminal 6 and the external output terminal 13 as ground, the MOS transistor Tr1 connected between the GND2 line 11 and the GNDI line 4 becomes conductive through the MOS transistor Tr6 and the MOS transistor Tr2. T current can be made to flow to the external output terminal 6. As a result, even if a high voltage of several KV is applied to the external terminal 13, the output circuits 8, 9, 10° and the internal circuit 20 connected to the GND2 line 11 and the VDD2 line 12
Destruction of the gate oxide film of the transistor (MOS) that constitutes the transistor can be prevented.
また、外部出力端子１３を接地として、外部出力端子６
にノイズ又は静電気が印加された場合には、ＭＯＳトラ
ンジスタＴ ｒ １のパンチスルーによって、ＧＮＤ
１ライン４からＧＮＤ：２ライン１１へとＴｈｉが流れ
、前述したと同様の効果が得られる。In addition, the external output terminal 13 is grounded, and the external output terminal 6
When noise or static electricity is applied to the GND
Thi flows from the 1st line 4 to the GND:2 line 11, and the same effect as described above is obtained.
また前記実施例では、ＧＮＤ １ライン１１とＧＮＤラ
イン４との間に保護回路２１を接続したが、ＶＤＤ１ラ
イン５とＶＤＤ２ラインとの間。Further, in the embodiment described above, the protection circuit 21 was connected between the GND 1 line 11 and the GND line 4, but the protection circuit 21 was connected between the VDD 1 line 5 and the VDD 2 line.
ＧＮＤ １ライン４のＶ Ｄ Ｄ ２ライン１２との間
。Between GND 1 line 4 and VDD 2 line 12.
ＶＤＤＩライン５とＧＮＤ２ライン１１との間に、それ
ぞれ保護回路を接続した場合でも同様な効果が得られる
。A similar effect can be obtained even when a protection circuit is connected between the VDDI line 5 and the GND2 line 11, respectively.
以上、ＭＯＳ）ランジスタＴｒｌのしきい値電圧を本実
施例では１５Ｖとしているが、これをプロセスにより変
化させ、目的に応じて能力を変えることができるのは言
うまでもない。As mentioned above, the threshold voltage of the MOS transistor Trl is set to 15 V in this embodiment, but it goes without saying that this can be changed depending on the process and the capability can be changed depending on the purpose.
本実施例によれば、外部出力端子間に接続された保護回
路が、外部出力端子間に印加されたノイズ又は静電気を
吸収するように作用する。このため、出力回路どうしの
電源ラインが分離された半導体集積回路装置においても
、出力回路及び内部回路を構成するＭＯ５Ｉ−ランジス
タのゲート酸化膜破壊を防止でき、信頼性を向上させる
ことができる。According to this embodiment, the protection circuit connected between the external output terminals acts to absorb noise or static electricity applied between the external output terminals. Therefore, even in a semiconductor integrated circuit device in which the power supply lines of the output circuits are separated from each other, damage to the gate oxide film of the MO5I transistor constituting the output circuit and the internal circuit can be prevented, and reliability can be improved.
以上の説明から明らかな如く、本発明は、電源・ＧＮＤ
ライン間に出力端子からのノイズ又は静電気を吸収する
ための保護回路を設けて吸収するようにしたことにより
、ノイズや静電気を原因としたＭＯＳトランジスタの破
壊を防止することができるという効果がある。As is clear from the above explanation, the present invention
By providing a protection circuit between the lines to absorb noise or static electricity from the output terminal, it is possible to prevent the MOS transistor from being destroyed due to noise or static electricity.
第１図は本発明の一実施例の半導体集積回路装置を示す
回路図、第２図は従来の半導体集積回路装置の回路図、
第３図は第２図の出力回路に接続しているＧＮＤを分割
したときの波形図、第４図は第２図の出力回路に接続し
ているＧＮＤを分割しないときの波形図である。
１．２．８．９・・・出力回路、３．１０・・・圧力回
路群−４，５，１１，１２・・・ライン、６．７゜１３
．１４・・・外部出力端子、１５．１６．１７゜１８・
・・内部回路からの出力信号線、１９．２０・・・内部
回路、２１・・・出力波形、２２・・・ＧＮＤ１ライン
の波形、２３・・・ＶＤＤ １ラインの波形、２４・・
・出力波形、２５・・・ＧＮＤ１ラインの波形、２６・
・・Ｖ Ｄ Ｄ １ラインの波形、３０・・・係属回路
。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional semiconductor integrated circuit device,
3 is a waveform diagram when the GND connected to the output circuit of FIG. 2 is divided, and FIG. 4 is a waveform diagram when the GND connected to the output circuit of FIG. 2 is not divided. 1.2.8.9... Output circuit, 3.10... Pressure circuit group -4, 5, 11, 12... Line, 6.7°13
．． 14...External output terminal, 15.16.17゜18.
... Output signal line from internal circuit, 19.20... Internal circuit, 21... Output waveform, 22... Waveform of GND1 line, 23... Waveform of VDD 1 line, 24...
・Output waveform, 25...GND1 line waveform, 26・
... V D D 1 line waveform, 30... Participating circuit.
Claims (1)
の出力回路と、第２の電源ラインが接続された第２の出
力回路とを備え、前記第１又は第２の出力回路の出力端
子に印加されるノイズ又は静電気を吸収する保護回路が
、前記第１、第２の電源ライン間に設けられていること
を特徴とする半導体集積回路装置。A first power supply line is connected to a first power supply line on a semiconductor substrate.
and a second output circuit connected to a second power line, the protection circuit absorbing noise or static electricity applied to the output terminal of the first or second output circuit, A semiconductor integrated circuit device, characterized in that it is provided between first and second power supply lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2211979A JPH0494568A (en) | 1990-08-10 | 1990-08-10 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2211979A JPH0494568A (en) | 1990-08-10 | 1990-08-10 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0494568A true JPH0494568A (en) | 1992-03-26 |
Family
ID=16614878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2211979A Pending JPH0494568A (en) | 1990-08-10 | 1990-08-10 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0494568A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122650A (en) * | 1993-10-22 | 1995-05-12 | Yamaha Corp | Semiconductor device |
| US5514894A (en) * | 1992-03-03 | 1996-05-07 | Nec Corporation | Protection circuit device for a semiconductor integrated circuit device |
| JPH08116026A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device |
| US5629545A (en) * | 1991-03-28 | 1997-05-13 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| US5678933A (en) * | 1995-01-20 | 1997-10-21 | Nsk Ltd. | Speed sensing rolling bearing unit |
| US5679971A (en) * | 1994-07-21 | 1997-10-21 | Hitachi, Ltd. | Semiconductor integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6336557A (en) * | 1986-07-30 | 1988-02-17 | Nec Corp | Complementary mis integrated circuit |
| JPH02113623A (en) * | 1988-10-21 | 1990-04-25 | Sharp Corp | Static electricity protecting circuit for integrated circuit |
-
1990
- 1990-08-10 JP JP2211979A patent/JPH0494568A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6336557A (en) * | 1986-07-30 | 1988-02-17 | Nec Corp | Complementary mis integrated circuit |
| JPH02113623A (en) * | 1988-10-21 | 1990-04-25 | Sharp Corp | Static electricity protecting circuit for integrated circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629545A (en) * | 1991-03-28 | 1997-05-13 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| US5514894A (en) * | 1992-03-03 | 1996-05-07 | Nec Corporation | Protection circuit device for a semiconductor integrated circuit device |
| JPH07122650A (en) * | 1993-10-22 | 1995-05-12 | Yamaha Corp | Semiconductor device |
| US5679971A (en) * | 1994-07-21 | 1997-10-21 | Hitachi, Ltd. | Semiconductor integrated circuit |
| JPH08116026A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device |
| US5678933A (en) * | 1995-01-20 | 1997-10-21 | Nsk Ltd. | Speed sensing rolling bearing unit |
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