JPH0379120A - Input protecting circuit - Google Patents

Input protecting circuit

Info

Publication number
JPH0379120A
JPH0379120A JP1215845A JP21584589A JPH0379120A JP H0379120 A JPH0379120 A JP H0379120A JP 1215845 A JP1215845 A JP 1215845A JP 21584589 A JP21584589 A JP 21584589A JP H0379120 A JPH0379120 A JP H0379120A
Authority
JP
Japan
Prior art keywords
input
pull
resistor
input protection
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1215845A
Other languages
Japanese (ja)
Inventor
Hitoshi Ogawa
斉 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP1215845A priority Critical patent/JPH0379120A/en
Publication of JPH0379120A publication Critical patent/JPH0379120A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain effective input protection by providing an input protection resistance which is interposed between an external input terminal and an internal circuit, and a pull-up or pull-down resistance which has one terminal connected to a specific power source and the other terminal connected between the external input terminal and input protection resistance. CONSTITUTION:The input protecting circuit consisting of the input protection resistance R1 is connected between an input part 2 and the internal circuit 3 and the pull-up resistance R2 which has one terminal connected to the high- potential power source VCC is connected between an input pad 2 and the input protecting circuit 1. The pull-down resistance R3 which has one terminal connected to a low-potential voltage VSS is connected between the input pad 2 and input protecting circuit 1. The input protection resistance R1 and pull-up (pull-down) resistance R2 (R3) are therefore not in voltage division relation, so the value of the input protection resistance R1 can be set irrelevantly to the value of the pull-up (pull-down) resistance R2 (R3).

Description

【発明の詳細な説明】 〔目次〕 概要 産業上の利用分野 従来の技術 発明が解決しようとする課題 (第3.4図) 課題を解決するための手段 作用 実施例 本発明の一実施例     (第1.2図)発明の効果 〔概要〕 入力保護回路に関し、 入力保護抵抗の値をプルアップ抵抗あるいはプルダウン
抵抗の値に無関係に設定でき、有効な入力保護を行うこ
とが可能な入力保護回路を提供することを目的とし、 外部入力端子と内部回路との間に介挿された入力保護抵
抗と、一端が所定の電源に接続され、他端が該外部入力
端子と該入力保護抵抗との間に接続されたプルアップあ
るいはプルダウン抵抗と、を備えて構成している。
[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention (Figure 3.4) Means for Solving the Problems Example of Action (Example of the Present Invention) Figure 1.2) Effects of the invention [Summary] Regarding the input protection circuit, an input protection circuit that can set the value of the input protection resistor regardless of the value of the pull-up resistor or pull-down resistor, and can perform effective input protection. The purpose is to provide an input protection resistor inserted between an external input terminal and an internal circuit, one end of which is connected to a predetermined power supply, and the other end of which is connected between the external input terminal and the input protection resistor. A pull-up or pull-down resistor is connected between the two.

〔産業上の利用分野〕[Industrial application field]

本発明は、入力保護回路に関し、詳しくは、入力保護抵
抗の値をプルアップ(あるいは、プルダウン)抵抗の値
に無関係に設定可能な入力保護回路に関する。
The present invention relates to an input protection circuit, and more particularly to an input protection circuit in which the value of an input protection resistor can be set independently of the value of a pull-up (or pull-down) resistor.

近時、微細加工技術の進歩に伴って半導体回路の集積度
がますます高まってきている。反面、回路の微細化は静
電破壊耐量を低下させる傾向にあり、このため、デバイ
スの製造からフィールドコースまでの全般に亘って、い
わゆるE S D (Elec−tro 5tatic
 Discharge)対策の重要性が増してきた。上
記のような静電気放電のストレスにより、集積回路には
劣化あるいは破壊が生ずる。そのメカニズムは熱的破壊
が主なものであるが、放電過程、デバイス構造によって
、いずれか弱いほうのメカニズムにより破壊が生ずるこ
とになる。この破壊電圧を向上させるために各入出力端
子には保護回路を設ける。MOSデバイスの場合、最も
破壊しやすいのはゲート絶縁膜で、Sin、の場合、7
MV/cm以上の電界が印加され、その間の消費電力が
約2μJのときゲート破壊が起こるとされている。した
がって、これを保護するため電圧をクランプするような
回路が必要となる。MO3形集積回路では、出力端子に
は比較的大きなソース・ドレインが接続されるため、こ
れが保護回路の役目をする。ソース・ドレインのpn接
合の形成に多少の注意が必要であるが、通常は良好なE
SD耐圧をもつ、一方の入力端子には意図的に保護回路
を設ける必要がある。
In recent years, the degree of integration of semiconductor circuits has been increasing with advances in microfabrication technology. On the other hand, miniaturization of circuits tends to reduce electrostatic breakdown resistance, and for this reason, so-called ESD (Electro 5 tatic
Discharge) countermeasures are becoming increasingly important. The stress of electrostatic discharge as described above causes deterioration or destruction of integrated circuits. The main mechanism is thermal destruction, but depending on the discharge process and device structure, destruction may occur by whichever is the weaker mechanism. In order to improve this breakdown voltage, each input/output terminal is provided with a protection circuit. In the case of MOS devices, the gate insulating film is the most easily destroyed, and in the case of Sin, 7
It is said that gate breakdown occurs when an electric field of MV/cm or more is applied and the power consumption during that time is about 2 μJ. Therefore, a circuit that clamps the voltage is required to protect this. In the MO3 type integrated circuit, a relatively large source/drain is connected to the output terminal, so this serves as a protection circuit. Although some care is required to form the source/drain pn junction, it usually has a good E.
It is necessary to intentionally provide a protection circuit to one input terminal that has an SD withstand voltage.

〔従来の技術〕[Conventional technology]

第3.4図は従来の入力保護回路の一例を示す図であり
、第3図は入力信号をプルアップして内部回路に伝える
プルアンプ抵抗を有する入力保護回路、第4図は入力信
号をプルダウンして内部回路に伝えるプルダウン抵抗を
有する入力保護回路である。第3図において、1は入力
パッド(外部入力端子)2と内部回路3との間に介挿さ
れた入力保護抵抗R1からなる入力保護回路であり、プ
ルアップ抵抗R2の一端は高電位側電源VCCに接続さ
れ、その他端は入力保護抵抗R1と内部回路3との間に
接続されている。同様に、第4図に示すようなプルダウ
ン抵抗R3を有する入力保護回路4では、プルダウン抵
抗R3の一端は低電位側電源Vss(GND)に接続さ
れ、その他端は入力保護抵抗R1と内部回路3との間に
接続されている。
Figure 3.4 is a diagram showing an example of a conventional input protection circuit. Figure 3 is an input protection circuit that has a pull amplifier resistor that pulls up the input signal and transmits it to the internal circuit, and Figure 4 pulls down the input signal. This is an input protection circuit with a pull-down resistor that transmits the signal to the internal circuit. In Fig. 3, 1 is an input protection circuit consisting of an input protection resistor R1 inserted between an input pad (external input terminal) 2 and an internal circuit 3, and one end of the pull-up resistor R2 is connected to the high potential side power supply. It is connected to VCC, and the other end is connected between the input protection resistor R1 and the internal circuit 3. Similarly, in the input protection circuit 4 having a pull-down resistor R3 as shown in FIG. 4, one end of the pull-down resistor R3 is connected to the low potential side power supply Vss (GND), and the other end is connected to the input protection resistor R1 and is connected between.

このような構成によれば、入力パッド2に例えば過大な
入力電流が印加されても入力保護回路1により適切に内
部回路3の保護を図ることができる。
According to such a configuration, even if, for example, an excessive input current is applied to the input pad 2, the input protection circuit 1 can appropriately protect the internal circuit 3.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このような従来の入力保護回路にあって
は、入力保護回路1と内部回路3との間にプルアップ抵
抗R1あるいはプルダウン抵抗R2を接続する構成とな
っていたため、例えば第3図の入力保護回路1ではプル
アップ抵抗R1の値に対して入力保護抵抗R2の値を十
分に小さく回路3の初段インバータのスレッシッルド電
圧)とらないと、外部入力端子である入力パッド2に“
L”レベルの信号が入力されても内部回路3の初段イン
バータが反転せず、入力保護抵抗R1の値を大きくでき
ないという問題点があった。すなわち、内部回路3の入
力INには入力保護電圧R1とプルアンプ抵抗R2とに
より分圧された電圧が入力されるため、入力保護抵抗R
1の抵抗値はプルアップ抵抗R2の抵抗値の関係で決定
せざるを得ず、入力保護抵抗R1に入力保護に十分な大
きい抵抗値を設定することが困難であった。上記不具合
は第4図に示したプルダウン抵抗R3を有する入力保護
回路1にあっても全く同様である。
However, in such a conventional input protection circuit, a pull-up resistor R1 or a pull-down resistor R2 is connected between the input protection circuit 1 and the internal circuit 3, so for example, the input protection circuit shown in FIG. In the protection circuit 1, unless the value of the input protection resistor R2 is set sufficiently small compared to the value of the pull-up resistor R1 (threshold voltage of the first stage inverter of the circuit 3), "
There was a problem in that even if an L" level signal was input, the first stage inverter of the internal circuit 3 did not invert, and the value of the input protection resistor R1 could not be increased. In other words, the input IN of the internal circuit 3 had an input protection voltage. Since the voltage divided by R1 and pull amplifier resistor R2 is input, the input protection resistor R
The resistance value of 1 must be determined in relation to the resistance value of the pull-up resistor R2, and it has been difficult to set the input protection resistor R1 to a sufficiently large resistance value for input protection. The above problem is exactly the same even in the input protection circuit 1 having the pull-down resistor R3 shown in FIG.

そこで本発明は、入力保護抵抗の値をプルアンプ抵抗あ
るいはプルダウン抵抗の値に無関係に設定でき、有効な
入力保護を行うことが可能な入力保護回路を提供するこ
とを目的としている。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an input protection circuit that can set the value of the input protection resistor regardless of the value of the pull-amplifier resistor or pull-down resistor, and can provide effective input protection.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による入力保護回路は上記目的達成のため、外部
入力端子と内部回路との間に介挿された入力保護抵抗と
、一端が所定の電源に接続され、他端が該外部入力端子
と該入力保護抵抗との間に接続されたプルアンプあるい
はプルダウン抵抗と、を備えている。
In order to achieve the above object, the input protection circuit according to the present invention includes an input protection resistor inserted between an external input terminal and an internal circuit, one end of which is connected to a predetermined power supply, and the other end of which is connected to the external input terminal and the internal circuit. It includes a pull amplifier or pull-down resistor connected between the input protection resistor and the input protection resistor.

〔作用〕 本発明では、外部入力端子と内部回路との間に入力保護
抵抗が介挿され、プルアップあるいはプルダウン抵抗の
一端は電源端子に、他端は外部入力端子と入力保護抵抗
との間に接続される。
[Function] In the present invention, an input protection resistor is inserted between the external input terminal and the internal circuit, one end of the pull-up or pull-down resistor is connected to the power supply terminal, and the other end is connected between the external input terminal and the input protection resistor. connected to.

したがって、入力保護抵抗とプルアップ(プルダウン)
抵抗とは分圧関係になくなるため、入力保護抵抗の値を
プルアップ(プルダウン)抵抗の値に無関係に設定する
ことができ、チップの保護が有効なものとなる。
Therefore, the input protection resistor and pull-up (pull-down)
Since there is no voltage division relationship with the resistor, the value of the input protection resistor can be set regardless of the value of the pull-up (pull-down) resistor, making chip protection effective.

〔実施例〕〔Example〕

以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.

第1.2図は本発明に係る入力保護回路の一実施例を示
す図である0本実施例の説明にあたり、第3.4図に示
した従来例と同一構成部分には同一符号を付している。
Fig. 1.2 is a diagram showing an embodiment of the input protection circuit according to the present invention. In explaining this embodiment, the same components as those of the conventional example shown in Fig. 3.4 are given the same reference numerals. are doing.

第1図はプルアンプ抵抗R2を有する入力保護回路であ
り、この図において、入力パッド2と内部回路3との間
に入力保護抵抗R1からなる入力保護回路1が接続され
るとともに、入力パッド2と入力保護回路1との間には
一端がVCCに接続されたプルアンプ抵抗R2が接続さ
れる。一方、第2図はプルダウン抵抗R3を有する入力
保護回路であり、この図においても第1図の場合と同様
に入力バッド2と内部回路3との間に入力保護回路1が
接続されるとともに、入力パッド2と入力保護回路1と
の間には一端がVSl+に接続されたプルダウン抵抗R
3が接続される。
FIG. 1 shows an input protection circuit having a pull amplifier resistor R2. In this figure, an input protection circuit 1 consisting of an input protection resistor R1 is connected between the input pad 2 and the internal circuit 3, and the input protection circuit 1 is connected between the input pad 2 and the internal circuit 3. A pull amplifier resistor R2 having one end connected to VCC is connected to the input protection circuit 1. On the other hand, FIG. 2 shows an input protection circuit having a pull-down resistor R3, and in this figure as well, the input protection circuit 1 is connected between the input pad 2 and the internal circuit 3, as in the case of FIG. A pull-down resistor R whose one end is connected to VSl+ is connected between the input pad 2 and the input protection circuit 1.
3 is connected.

以上の構成において、入力バッド2に“L″レベル信号
が入力された場合、入力保護抵抗R1およびプルアップ
抵抗R2の値に関係なく、内部回路3には”L”レベル
の信号が入力される。したがって、入力保護抵抗R1の
抵抗値を自由に設定することができる。
In the above configuration, when an "L" level signal is input to the input pad 2, an "L" level signal is input to the internal circuit 3 regardless of the values of the input protection resistor R1 and pull-up resistor R2. . Therefore, the resistance value of the input protection resistor R1 can be freely set.

また、第2図に示した一端がVSSに接地されたプルダ
ウン抵抗R3の場合も同様のことが言える。
Further, the same can be said of the pull-down resistor R3 shown in FIG. 2, one end of which is grounded to VSS.

以上述べたように、本実施例によれば入力保護抵抗の値
をプルアップ(プルダウン)抵抗の値に関係な(大きく
設定できるため、チップ保護に実用上極めて有用である
As described above, according to this embodiment, the value of the input protection resistor can be set to a value that is related to (larger than) the value of the pull-up (pull-down) resistor, so it is extremely useful in practice for chip protection.

第3.4図は従来の入力保護回路を示す図であり、 第3図はそのプルアップ抵抗R2を有する入力保護回路
の回路図、 第4図はそのプルダウン抵抗R3を有する入力保護回路
の回路図である。
Fig. 3.4 is a diagram showing a conventional input protection circuit, Fig. 3 is a circuit diagram of an input protection circuit having a pull-up resistor R2, and Fig. 4 is a circuit diagram of an input protection circuit having a pull-down resistor R3. It is a diagram.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、入力保護抵抗の値をプルアップ抵抗あ
るいはプルダウン抵抗の値に無関係に設定することがで
き、有効な入力保護を行うことができる。
According to the present invention, the value of the input protection resistor can be set regardless of the value of the pull-up resistor or pull-down resistor, and effective input protection can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1.2図は本発明に係る入力保護回路の一実施例を示
す図であり、 第1図はそのプルアップ抵抗R2を有する入力保護回路
の回路図、 第2図はそのプルダウン抵抗R3を有する入力保護回路
の回路図、 1・・・・・・入力保護回路、 2・・・・・・入力パッド(スト部入力端子)、3・・
・・・・内部回路、 R1・・・・・・入力保護抵抗、 R2・・・・・・プルアップ抵抗、 R3・・・・・・プルダウン抵抗、 Vcc・・・−・・高電位側電源、 VSS・・・・・・低電位側電源。 第 1 図 第 図 従来例のプルアップ抵抗R2を有する入力保護回路の回
路図 第3図 従来例のプルダウン抵抗R3を有する人力保護回路の回
路図 第4図
FIG. 1.2 is a diagram showing an embodiment of the input protection circuit according to the present invention. FIG. A circuit diagram of an input protection circuit having the following: 1... Input protection circuit, 2... Input pad (input terminal of strike part), 3...
...Internal circuit, R1...Input protection resistor, R2...Pull-up resistor, R3...Pull-down resistor, Vcc...--High potential side power supply , VSS...Low potential side power supply. Figure 1 Figure 3 A circuit diagram of a conventional input protection circuit with a pull-up resistor R2 Figure 3 A circuit diagram of a conventional human protection circuit with a pull-down resistor R3 Figure 4

Claims (1)

【特許請求の範囲】 外部入力端子と内部回路との間に介挿された入力保護抵
抗と、 一端が所定の電源に接続され、他端が該外部入力端子と
該入力保護抵抗との間に接続されたプルアップあるいは
プルダウン抵抗と、 を備えたことを特徴とする入力保護回路。
[Claims] An input protection resistor inserted between an external input terminal and an internal circuit, one end of which is connected to a predetermined power supply, and the other end of which is connected between the external input terminal and the input protection resistor. An input protection circuit comprising: a connected pull-up or pull-down resistor;
JP1215845A 1989-08-22 1989-08-22 Input protecting circuit Pending JPH0379120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1215845A JPH0379120A (en) 1989-08-22 1989-08-22 Input protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1215845A JPH0379120A (en) 1989-08-22 1989-08-22 Input protecting circuit

Publications (1)

Publication Number Publication Date
JPH0379120A true JPH0379120A (en) 1991-04-04

Family

ID=16679224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1215845A Pending JPH0379120A (en) 1989-08-22 1989-08-22 Input protecting circuit

Country Status (1)

Country Link
JP (1) JPH0379120A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350429A (en) * 1993-06-04 1994-12-22 Mitsubishi Electric Corp Signal input/output circuit for semiconductor integrated circuit
JP2002360423A (en) * 2001-06-06 2002-12-17 Minami Sangyo Kk Cooker and method of cooking using the same
JP2004173307A (en) * 2004-01-28 2004-06-17 Renesas Technology Corp Signal input/output circuit for semiconductor integrated circuit
EP1710914A1 (en) * 2005-03-15 2006-10-11 Fujitsu Limited Input protection circuit
JP2014137272A (en) * 2013-01-16 2014-07-28 Denso Corp Voltage monitoring device
JP2019193140A (en) * 2018-04-26 2019-10-31 株式会社デンソー Amplifier circuit with analog multiplexer
JP2020031309A (en) * 2018-08-22 2020-02-27 日立オートモティブシステムズ株式会社 Electronic controller

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350429A (en) * 1993-06-04 1994-12-22 Mitsubishi Electric Corp Signal input/output circuit for semiconductor integrated circuit
JP2002360423A (en) * 2001-06-06 2002-12-17 Minami Sangyo Kk Cooker and method of cooking using the same
JP2004173307A (en) * 2004-01-28 2004-06-17 Renesas Technology Corp Signal input/output circuit for semiconductor integrated circuit
EP1710914A1 (en) * 2005-03-15 2006-10-11 Fujitsu Limited Input protection circuit
KR100671861B1 (en) * 2005-03-15 2007-01-22 후지쯔 가부시끼가이샤 Input protection circuit
JP2014137272A (en) * 2013-01-16 2014-07-28 Denso Corp Voltage monitoring device
JP2019193140A (en) * 2018-04-26 2019-10-31 株式会社デンソー Amplifier circuit with analog multiplexer
WO2019207980A1 (en) * 2018-04-26 2019-10-31 株式会社デンソー Amplification circuit with analog multiplexer
US11799464B2 (en) 2018-04-26 2023-10-24 Denso Corporation Amplification circuit with analog multiplexer
JP2020031309A (en) * 2018-08-22 2020-02-27 日立オートモティブシステムズ株式会社 Electronic controller

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