JP3301278B2 - Surge protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge protection circuit for protecting a semiconductor integrated circuit from overcurrent, and more particularly to a surge protection circuit for protecting a semiconductor integrated circuit which inputs or outputs a signal having a higher potential than a power supply voltage to be used. It relates to a protection circuit.

[0002]

FIG. 6 is a diagram showing a conventional semiconductor circuit including a conventional surge protection circuit 30. As shown in FIG.

In FIG. 6, an input circuit or an output circuit 1
One input terminal or output terminal and the pad 10 are connected by wiring, and a conventional surge protection circuit 30 is connected between this wiring and GND. The surge protection circuit 30
MOS transistor 31 and N-type MOS transistor 3
2 is a circuit described in Japanese Patent Application Laid-Open No. 62-287659. Reference numeral 12 denotes an internal circuit.

In the surge protection circuit 30, an N-type MOS
The drain of the transistor 31 is connected to a wiring connecting the pad 10 to the input circuit or the output circuit 11,
The source of the S transistor 31 is connected to the drain of the N-type MOS transistor 32, and the source of the N-type MOS transistor 32 is connected to GND. The respective gates of the N-type MOS transistors 31 and 32 are both GND.
It is connected to the.

The reliability of the transistors constituting the circuit shown in FIG. 6 is guaranteed on the assumption that the transistors are used at the rated power supply voltage Vdd.

Next, the operation of the above conventional example will be described.

Assuming that the source / drain breakdown voltage in the off state when the gate of the N-type MOS transistor is grounded is Vbds, the breakdown voltage of the surge protection circuit 30 is n · Vbds (n is about 1.1 to 1.1).
2.0, n · Vbds> Vdd, where Vdd is the power supply voltage). The breakdown voltage is defined by either snapback voltage or source / drain voltage.
Here, in order to simplify the explanation, the surge protection circuit 3
The breakdown voltage of 0 is n · Vbds = 2 · Vbds
And

In an operating state where the integrated circuit is connected to a power supply,
The signal input (output) to the pad 10 is a signal having a voltage of less than 2 · Vbds, the surge protection circuit 30 does not break down, an external signal is directly input to the input circuit, and the output circuit Output signal is pad 1 as it is
Appears at 0.

In particular, in the surge protection circuit described in Japanese Patent Application Laid-Open No. 62-287659, breakdown does not occur even if a signal having a potential higher than the power supply voltage Vdd is input. For example, in a semiconductor integrated circuit of Vdd = 2.0V,
Even if a signal having a high level of 3.3 V is input, no breakdown occurs.

On the other hand, when a surge is applied to the pad 10, the surge voltage is at least several hundred volts, which is much larger than 2 · Vbds.
Both break down and the impedance drops, so that an overcurrent flows to GND and the input circuit or output circuit 1
1 (N-type MOS transistor 31)
Of the drain potential).

In this way, the surge protection circuit 30 prevents the transistors constituting the input circuit or the output circuit 11 from being destroyed.

[0012]

However, in the conventional surge protection circuit 30, the input (or output) signal of a high-level signal having a potential higher than the power supply voltage Vdd is allowed to be applied to the pad 10. Therefore, there is a problem that the lifetime guarantee period of the semiconductor integrated circuit is shorter than the case where only signals within Vdd are applied to the pad 10.

That is, when a signal having a potential higher than the power supply voltage Vdd is input (or output) to the pad 10, since the gate of the N-type MOS transistor 31 is grounded, the gate and drain of the N-type MOS transistor 31 During this period, a voltage higher than the power supply voltage Vdd is applied. Therefore, in the N-type MOS transistor 31 to which a voltage higher than the power supply voltage Vdd is applied, Vdd
The life of the element is shorter from the viewpoint of reliability than the MOS transistor which is suppressed within the range, and as a result, the life guarantee period of the semiconductor integrated circuit as a whole is shortened.

According to the present invention, n.Vdd-Vthn
(Where n is 1.1 to 2 and Vthn is the threshold voltage of an N-type MOS transistor), the gate-drain voltage of the first transistor whose drain is connected to the pad is input (output). It is an object of the present invention to provide a surge protection circuit capable of reducing the voltage between the drain and the source to the power supply voltage Vdd or lower.

[0015]

The present invention is included in a semiconductor integrated circuit operated by a high potential power supply and a low potential power supply, wherein a drain of a first transistor is connected to an input terminal or an output terminal, and The source of the transistor is second
In the surge protection circuit, the source of the second transistor is connected to the low-potential power supply or the high-potential power supply, and the gate of the second transistor is connected to the source of the second transistor. The gate of the first transistor is connected to a power supply different from the power supply to which the sources of the two transistors are connected.

[0016]

According to the present invention, since the gate of the first transistor is connected to a power supply different from the power supply to which the source of the second transistor is connected, the pad has n.Vdd-
Even if a signal having a potential of Vthn (n is 1.1 to 2 and Vthn is a threshold voltage of an N-type MOS transistor) is input (output), a signal between the gate and the drain of the first transistor whose drain is connected to the pad is provided. The voltage and the drain-source voltage can be made equal to or lower than the power supply voltage Vdd.

[0017]

FIG. 1 is a circuit diagram showing a semiconductor circuit including a surge protection circuit 20 according to an embodiment of the present invention.

The surge protection circuit 20 is connected between a wire connecting the input terminal or the output terminal of the input circuit or the output circuit 11 and the pad 10, and GND.
MOS transistor 21 and N-type MOS transistor 2
And 2. Reference numeral 12 denotes an internal circuit.

The drain of the N-type MOS transistor 21 is connected to a wiring connecting the pad 10 to the input circuit or the output circuit 11, the source of the N-type MOS transistor 21 is connected to the drain of the N-type MOS transistor 22, The gate of the type MOS transistor 21 is connected to a power supply terminal VDD to which the voltage voltage Vdd is applied.
The gate and source of the N-type MOS transistor 22 are GN
D.

The reliability of the transistors constituting the circuit of FIG. 1 is guaranteed on the assumption that the transistors are used at the rated power supply voltage Vdd.

Next, the operation of the above embodiment will be described.

In a state where the input circuit or output circuit 11 and the internal circuit 12 are protected from surges during chip transport or wire bonding, the power supply voltage VDD is not applied to the power supply terminal VDD and the power supply terminal VDD becomes floating. ing. Strictly, the power supply terminal VDD is connected to GND via the off-state resistance of the transistor of the internal circuit 12. Therefore, the gate of the N-type MOS transistor 21 is also at GND.

The source-drain breakdown voltage in the off state where the gate of the N-type MOS transistor is grounded is V
bds, N-type MOS with gate at GND potential
The source / drain breakdown voltage of the transistor 21 also becomes Vbds.

Therefore, as shown in FIG. 2, the breakdown voltage of the surge protection circuit 20 is n.Vbds (n is about 1.1 to 2.0, n.Vbds> Vdd,
Vdd is the power supply voltage).

Here, when a surge is applied to the pad 10, both the N-type MOS transistors 21 and 22 break down, an overcurrent flows to GND, and the potential of the connection node of the input circuit or the output circuit 11 (N Increase in the drain potential of the MOS transistor 21). As described above, at the time of chip transfer, wire bonding, or the like, the input circuit or the output circuit
Is prevented from being destroyed.

Next, the state of operating the integrated circuit in the above embodiment will be described.

FIG. 3 is a diagram showing voltages applied to the transistors 21 and 22 constituting the surge protection circuit 20 in a state where the integrated circuit including the surge protection circuit 20 is operating in the above embodiment.

As shown in FIG. 3, when the integrated circuit including the surge protection circuit 20 is operating, the transistors 21 and 22 constituting the surge protection circuit 20 apply only a voltage equal to or lower than the rated power supply voltage Vdd. Not applied. That is, the source / drain voltage V of the transistors 21 and 22
ds and the gate / drain voltage Vgd are all the power supply voltage Vd
d or less.

When the integrated circuit is operated, the power supply voltage Vdd is applied to the power supply terminal VDD, and the N-type MOS
The gate potential of the transistor 21 becomes the power supply voltage Vdd.

Here, when the input (output) potential of the pad 10 is equal to or lower than Vdd, the following operation is performed. The potential of the pad 10 is changed from 0 V to Vdd-Vthn (Vthn
Is the threshold voltage of an N-type MOS transistor)
The OS transistor 21 is turned on, and the source potential of the N-type MOS transistor 21 is also equal to the potential of the drain. Since the N-type MOS transistor 22 has a source / drain breakdown voltage higher than Vdd, the surge protection circuit 20 does not break down.

On the other hand, when the output (output) potential of pad 10 is higher than power supply voltage Vdd, the following operation is performed. When the potential of the pad 10 exceeds Vdd-Vthn, the source potential of the N-type MOS transistor 21 becomes Vdd
−Vthn. At this time, the source-drain voltage and the gate-source voltage of the N-type MOS transistor 22 are Vdd-Vthn, which are lower than Vdd. Further, since the source potential of the N-type MOS transistor 21 has risen to Vdd-Vthn,
The potential of the pad 10 of the transistor 21 is also 2Vdd-Vt.
Until hn, the source-drain voltage becomes Vdd or less, and the gate-source voltage becomes Vdd-Vthn.

FIG. 4 shows that the potential of the pad 10 is 2 Vdd-V
thn, the N constituting the surge protection circuit 20
FIG. 3 is a diagram showing the voltages applied to the type MOS transistors 21 and 22 by comparing the above-described embodiment with the conventional example.

In the conventional example, the N-type MOS transistor 21
Both the source-drain voltage and the gate-source voltage exceed Vdd, whereas in the above embodiment the source-drain voltage
The drain-to-drain voltage is Vdd, and the gate-to-source
dd-Vthn, Vdd-Vth between gate and drain
n and does not exceed Vdd.

The surge protection circuit 20 is included in a semiconductor integrated circuit operated by a high-potential power supply and a low-potential power supply, and a drain of the first transistor is connected to an input terminal or an output terminal. Is connected to the drain of the second transistor, and the second
Is an example of a surge protection circuit in which the source of the transistor is connected to a low-potential power supply or a high-potential power supply, and the gate of the second transistor is connected to the source of the second transistor. , The N-type MOS transistor 22 is an example of the second transistor, and the surge protection circuit 20 is connected to a power supply to which the source of the second transistor is connected. Is an example of a surge protection circuit in which the gate of the first transistor is connected to a different power supply.

In the above embodiment, the bulk, SOI (Sil
icon On Insulator) It can be applied to any integrated circuit on the substrate.

FIG. 5 is a diagram showing a measurement result of a breakdown voltage (in this case, a snap-back voltage) of a 0.5 μm CMOS by comparing the above embodiment with the conventional example.

When applied to a circuit on a bulk, pad 1
The voltage that can be applied to 0 only increases 1.1 times with respect to the protection circuit of one stage of the N-type MOS transistor. On the other hand, SO
When applied to a circuit on an I-substrate, the voltage that can be applied to the pad 10 enables 1.8 times the voltage to be applied to the protection circuit of one stage of the N-type MOS transistor. Therefore, S
Further effects can be obtained when the surge protection circuit 20 is applied to an LSI having an OI (Silicon On Insulator) structure.

Although a MOSFET is used as a transistor in the above embodiment, this MOSFET
MESFET may be used instead of T.

[0039]

According to the present invention, n.Vdd-
Even if a signal having a potential of Vthn (n is 1.1 to 2 and Vthn is a threshold voltage of an N-type MOS transistor) is input (output), a signal between the gate and the drain of the first transistor whose drain is connected to the pad is provided. The voltage and the drain-source voltage can be made equal to or lower than the power supply voltage Vdd, so that there is an effect that the lifetime of all the transistors constituting the surge protection circuit is long.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor circuit including a surge protection circuit 20 according to one embodiment of the present invention.

FIG. 2 is a diagram showing a breakdown current with respect to a voltage of a pad 10 in the embodiment.

FIG. 3 is a circuit diagram showing the operation of the integrated circuit including the surge protection circuit 20 according to the embodiment;
FIG. 3 is a diagram showing voltages applied to transistors 21 and 22 constituting the first embodiment.

FIG. 4 compares the voltage applied to the N-type MOS transistors 21 and 22 constituting the surge protection circuit 20 when the potential of the pad 10 is 2 Vdd-Vthn, by comparing the above embodiment with the conventional example. FIG.

FIG. 5 is a diagram showing actual measurement results of a breakdown voltage (in this case, a snapback voltage) of a 0.5 μm CMOS by comparing the above embodiment with the conventional example.

FIG. 6 is a diagram showing a conventional semiconductor circuit including a conventional surge protection circuit 30.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Pad, 11 ... Input or output circuit, 12 ... Internal circuit, 20 ... Surge protection circuit, 21 ... N-type MOS transistor as 1st transistor, 22 ... N-type MOS transistor as 2nd transistor.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-53-110382 (JP, A) JP-A-4-248322 (JP, A) JP-A-62-287659 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) H02H 3/22 H02H 7/20

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit which is operated by a high potential power supply and a low potential power supply, wherein a drain of a first transistor is connected to an input terminal or an output terminal, and a source of the first transistor is a second transistor. A surge protection circuit connected to a drain of the transistor, a source of the second transistor connected to a low-potential power supply or a high-potential power supply, and a gate of the second transistor connected to a source of the second transistor; A surge protection circuit, wherein the gate of the first transistor is connected to a power supply different from the power supply to which the source of the second transistor is connected. 2. The surge protection circuit according to claim 1, wherein said surge protection circuit is a circuit created on an LSI having an SOI structure.